.. |
ipcore_dir
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8f1dd1c1e2
FPGA: update project files (ISE 13.2)
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12 anni fa |
address.v
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1d928e7091
Merge branch 'udev' into develop
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10 anni fa |
bsx.v
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1d928e7091
Merge branch 'udev' into develop
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10 anni fa |
clk_test.v
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a083d80ff9
FPGA: update clock speed to 88MHz
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12 anni fa |
dac.v
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1a52da6272
FPGA: Adjust DAC I²S signal timing
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12 anni fa |
dcm.v
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f3a67ab5aa
FPGA: rework shared memory access
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12 anni fa |
main.ucf
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a083d80ff9
FPGA: update clock speed to 88MHz
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12 anni fa |
main.v
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1d928e7091
Merge branch 'udev' into develop
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10 anni fa |
main_tf.v
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a3ac555e18
FPGA: add test fixtures
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13 anni fa |
mcu_cmd.v
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968c347986
FPGA/SPI: detect end of byte via MSB toggle instead of constant compare of async input
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12 anni fa |
msu.v
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9253cc45b0
FPGA: implement MSU1 "audio error" status bit
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12 anni fa |
rtc.v
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a083d80ff9
FPGA: update clock speed to 88MHz
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12 anni fa |
sd2snes.xise
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1d928e7091
Merge branch 'udev' into develop
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10 anni fa |
sd_dma.v
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effa2a6972
FPGA/SDDMA: fix clock glitch, adjust RAM write timings
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12 anni fa |
spi.v
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968c347986
FPGA/SPI: detect end of byte via MSB toggle instead of constant compare of async input
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12 anni fa |
srtc.v
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6b3a7eb4ae
FPGA/SRTC: buffer register/address input
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12 anni fa |
upd77c25.v
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2ef480f751
FPGA/DSPx: buffer register input
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12 anni fa |
updtest_tf.v
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ed1e398851
FPGA: fix ST0010 glitches
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13 anni fa |