Godzil 1d928e7091 Merge branch 'udev' into develop 10 anni fa
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ipcore_dir 8f1dd1c1e2 FPGA: update project files (ISE 13.2) 12 anni fa
address.v 1d928e7091 Merge branch 'udev' into develop 10 anni fa
bsx.v 1d928e7091 Merge branch 'udev' into develop 10 anni fa
clk_test.v a083d80ff9 FPGA: update clock speed to 88MHz 12 anni fa
dac.v 1a52da6272 FPGA: Adjust DAC I²S signal timing 12 anni fa
dcm.v f3a67ab5aa FPGA: rework shared memory access 12 anni fa
main.ucf a083d80ff9 FPGA: update clock speed to 88MHz 12 anni fa
main.v 1d928e7091 Merge branch 'udev' into develop 10 anni fa
main_tf.v a3ac555e18 FPGA: add test fixtures 13 anni fa
mcu_cmd.v 968c347986 FPGA/SPI: detect end of byte via MSB toggle instead of constant compare of async input 12 anni fa
msu.v 9253cc45b0 FPGA: implement MSU1 "audio error" status bit 12 anni fa
rtc.v a083d80ff9 FPGA: update clock speed to 88MHz 12 anni fa
sd2snes.xise 1d928e7091 Merge branch 'udev' into develop 10 anni fa
sd_dma.v effa2a6972 FPGA/SDDMA: fix clock glitch, adjust RAM write timings 12 anni fa
spi.v 968c347986 FPGA/SPI: detect end of byte via MSB toggle instead of constant compare of async input 12 anni fa
srtc.v 6b3a7eb4ae FPGA/SRTC: buffer register/address input 12 anni fa
upd77c25.v 2ef480f751 FPGA/DSPx: buffer register input 12 anni fa
updtest_tf.v ed1e398851 FPGA: fix ST0010 glitches 13 anni fa