dcm.v 3.0 KB

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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 13:06:52 06/28/2009
  7. // Design Name:
  8. // Module Name: dcm
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module my_dcm (
  22. input CLKIN,
  23. output CLKFX,
  24. output LOCKED,
  25. input RST,
  26. output[7:0] STATUS
  27. );
  28. // DCM: Digital Clock Manager Circuit
  29. // Spartan-3
  30. // Xilinx HDL Language Template, version 11.1
  31. DCM #(
  32. .SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
  33. .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
  34. // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
  35. .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
  36. .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
  37. .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
  38. .CLKIN_PERIOD(41.667), // Specify period of input clock
  39. .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
  40. .CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
  41. .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
  42. // an integer from 0 to 15
  43. .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
  44. .DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
  45. .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
  46. .FACTORY_JF(16'hFFFF), // FACTORY JF values
  47. // .LOC("DCM_X0Y0"),
  48. .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
  49. .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
  50. ) DCM_inst (
  51. .CLK0(CLK0), // 0 degree DCM CLK output
  52. .CLK180(CLK180), // 180 degree DCM CLK output
  53. .CLK270(CLK270), // 270 degree DCM CLK output
  54. .CLK2X(CLK2X), // 2X DCM CLK output
  55. .CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
  56. .CLK90(CLK90), // 90 degree DCM CLK output
  57. .CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
  58. .CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
  59. .CLKFX180(CLKFX180), // 180 degree CLK synthesis out
  60. .LOCKED(LOCKED), // DCM LOCK status output
  61. .PSDONE(PSDONE), // Dynamic phase adjust done output
  62. .STATUS(STATUS), // 8-bit DCM status bits output
  63. .CLKFB(CLKFB), // DCM clock feedback
  64. .CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
  65. .PSCLK(PSCLK), // Dynamic phase adjust clock input
  66. .PSEN(PSEN), // Dynamic phase adjust enable input
  67. .PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
  68. .RST(RST) // DCM asynchronous reset input
  69. );
  70. endmodule