updtest_tf.v 2.5 KB

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  1. `timescale 1ns / 1ps
  2. ////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 09:28:48 05/31/2011
  7. // Design Name: upd77c25
  8. // Module Name: /home/ikari/prj/sd2snes/verilog/sd2snes/updtest.tf
  9. // Project Name: sd2snes
  10. // Target Device:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Verilog Test Fixture created by ISE for module: upd77c25
  15. //
  16. // Dependencies:
  17. //
  18. // Revision:
  19. // Revision 0.01 - File Created
  20. // Additional Comments:
  21. //
  22. ////////////////////////////////////////////////////////////////////////////////
  23. module updtest;
  24. // Inputs
  25. reg [7:0] DI;
  26. reg A0;
  27. reg nCS;
  28. reg nRD;
  29. reg nWR;
  30. reg RST;
  31. reg CLK;
  32. reg PGM_WR;
  33. reg [23:0] PGM_DI;
  34. reg [10:0] PGM_WR_ADDR;
  35. reg DAT_WR;
  36. reg [15:0] DAT_DI;
  37. reg [9:0] DAT_WR_ADDR;
  38. // debug
  39. wire [15:0] SR;
  40. wire [15:0] DR;
  41. wire [10:0] PC;
  42. wire [15:0] A;
  43. wire [15:0] B;
  44. wire [5:0] FL_A;
  45. wire [5:0] FL_B;
  46. // Outputs
  47. wire [7:0] DO;
  48. // variables
  49. integer i;
  50. // Instantiate the Unit Under Test (UUT)
  51. upd77c25 uut (
  52. .DI(DI),
  53. .DO(DO),
  54. .A0(A0),
  55. .nCS(nCS),
  56. .nRD(nRD),
  57. .nWR(nWR),
  58. .DP_nCS(1'b1),
  59. .RST(RST),
  60. .CLK(CLK),
  61. .PGM_WR(PGM_WR),
  62. .PGM_DI(PGM_DI),
  63. .PGM_WR_ADDR(PGM_WR_ADDR),
  64. .DAT_WR(DAT_WR),
  65. .DAT_DI(DAT_DI),
  66. .DAT_WR_ADDR(DAT_WR_ADDR),
  67. .SR(SR),
  68. .DR(DR),
  69. .PC(PC),
  70. .A(A),
  71. .B(B),
  72. .FL_A(FL_A),
  73. .FL_B(FL_B)
  74. );
  75. initial begin
  76. // Initialize Inputs
  77. DI = 0;
  78. A0 = 0;
  79. nCS = 0;
  80. nRD = 1;
  81. nWR = 1;
  82. RST = 1;
  83. CLK = 0;
  84. PGM_WR = 0;
  85. PGM_DI = 0;
  86. PGM_WR_ADDR = 0;
  87. DAT_WR = 0;
  88. DAT_DI = 0;
  89. DAT_WR_ADDR = 0;
  90. // Wait 100 ns for global reset to finish
  91. #1000;
  92. // Add stimulus here
  93. nRD = 0;
  94. #100 nRD = 1;
  95. for (i=0; i < 1; i = i + 1) begin
  96. #200 nRD = 0;
  97. #200 nRD = 1;
  98. end
  99. #1000 DI = 8'h02;
  100. nWR = 0;
  101. #200 nWR = 1;
  102. #3000 DI = 8'hc2;
  103. for (i=0; i < 6; i = i + 1) begin
  104. #400 nWR = 0;
  105. #400 nWR = 1;
  106. #400 nWR = 0;
  107. #400 nWR = 1;
  108. end
  109. #15000;
  110. #200 nWR = 0;
  111. #200 nWR = 1;
  112. #200 nWR = 0;
  113. #200 nWR = 1;
  114. #50000;
  115. for (i=0; i < 10; i = i + 1) begin
  116. #200 nRD = 0;
  117. #200 nRD = 1;
  118. end
  119. #200 DI = 8'h06;
  120. nWR = 0;
  121. #200 nWR = 1;
  122. #200 DI = 8'h7f;
  123. for (i=0; i < 3; i = i + 1) begin
  124. #400 nWR = 0;
  125. #400 nWR = 1;
  126. #400 nWR = 0;
  127. #400 nWR = 1;
  128. end
  129. #15000;
  130. for (i=0; i < 10; i = i + 1) begin
  131. #200 nRD = 0;
  132. #200 nRD = 1;
  133. end
  134. end
  135. always #6 CLK = ~CLK;
  136. endmodule