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@@ -31,7 +31,10 @@ module sd_dma(
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input [10:0] SD_DMA_PARTIAL_START,
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input [10:0] SD_DMA_PARTIAL_END,
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input SD_DMA_START_MID_BLOCK,
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- input SD_DMA_END_MID_BLOCK
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+ input SD_DMA_END_MID_BLOCK,
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+
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+ output [10:0] DBG_cyclecnt,
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+ output [2:0] DBG_clkcnt
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);
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reg [10:0] SD_DMA_STARTr;
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@@ -74,7 +77,11 @@ assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr;
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reg [2:0] clkcnt;
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initial clkcnt = 3'b000;
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reg [1:0] SD_CLKr;
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-always @(posedge CLK) SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
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+initial SD_CLKr = 3'b111;
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+always @(posedge CLK)
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+ if(SD_DMA_EN_rising) SD_CLKr <= 3'b111;
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+ else SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
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+
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assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr[1] : 1'bZ;
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always @(posedge CLK) begin
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@@ -116,20 +123,20 @@ always @(posedge CLK) begin
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if(SD_DMA_STATUSr) begin
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case(clkcnt[2:0])
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3'h0: begin
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- SD_DMA_SRAM_WEr <= 1'b1;
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SD_DMA_SRAM_DATAr[7:4] <= SD_DAT;
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if(cyclecnt>SD_DMA_STARTr && cyclecnt <= SD_DMA_ENDr) SD_DMA_NEXTADDRr <= 1'b1;
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end
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- 3'h1:
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+ 3'h1: begin
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SD_DMA_NEXTADDRr <= 1'b0;
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-// 3'h2:
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- 3'h3:
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- if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0;
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+ end
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+ 3'h2: if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0;
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+// 3'h3:
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3'h4:
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SD_DMA_SRAM_DATAr[3:0] <= SD_DAT;
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// 3'h5:
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// 3'h6:
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-// 3'h7:
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+ 3'h7:
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+ SD_DMA_SRAM_WEr <= 1'b1;
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endcase
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end
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end
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