clk_test.v 1.2 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152
  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 22:40:46 12/20/2010
  7. // Design Name:
  8. // Module Name: clk_test
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module clk_test(
  22. input clk,
  23. input sysclk,
  24. output [31:0] snes_sysclk_freq
  25. );
  26. reg [31:0] snes_sysclk_freq_r;
  27. assign snes_sysclk_freq = snes_sysclk_freq_r;
  28. reg [31:0] sysclk_counter;
  29. reg [31:0] sysclk_value;
  30. initial snes_sysclk_freq_r = 32'hFFFFFFFF;
  31. initial sysclk_counter = 0;
  32. initial sysclk_value = 0;
  33. reg [1:0] sysclk_sreg;
  34. always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
  35. wire sysclk_rising = (sysclk_sreg == 2'b01);
  36. always @(posedge clk) begin
  37. if(sysclk_counter < 88000000) begin
  38. sysclk_counter <= sysclk_counter + 1;
  39. if(sysclk_rising) sysclk_value <= sysclk_value + 1;
  40. end else begin
  41. snes_sysclk_freq_r <= sysclk_value;
  42. sysclk_counter <= 0;
  43. sysclk_value <= 0;
  44. end
  45. end
  46. endmodule