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@@ -30,7 +30,8 @@ module dac(
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input reset,
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output sdout,
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output lrck,
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- output mclk,
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+ output mclk,
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+ output sclk,
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output DAC_STATUS
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);
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@@ -68,14 +69,15 @@ reg [15:0] smpshift;
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assign mclk = cnt[2]; // mclk = clk/8
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assign lrck = cnt[8]; // lrck = mclk/128
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-wire sclk = cnt[3]; // sclk = lrck*32
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+assign sclk = cnt[3]; // sclk = lrck*32
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reg [2:0] lrck_sreg;
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reg [2:0] sclk_sreg;
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-wire lrck_rising = ({lrck_sreg[2:1]} == 2'b01);
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-wire lrck_falling = ({lrck_sreg[2:1]} == 2'b10);
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+wire lrck_rising = (lrck_sreg[1:0] == 2'b01);
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+wire lrck_falling = (lrck_sreg[1:0] == 2'b10);
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-wire sclk_rising = ({sclk_sreg[2:1]} == 2'b01);
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+wire sclk_rising = (sclk_sreg[1:0] == 2'b01);
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+wire sclk_falling = (sclk_sreg[1:0] == 2'b10);
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wire vol_latch_rising = (vol_latch_reg[1:0] == 2'b01);
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reg sdout_reg;
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@@ -143,17 +145,17 @@ always @(posedge clkin) begin
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end
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always @(posedge clkin) begin
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- if (lrck_rising) begin // right channel
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- smpshift <= (({16'h0, dac_data[31:16]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
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- samples <= samples + 1;
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- end else if (lrck_falling) begin // left channel
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- smpshift <= (({16'h0, dac_data[15:0]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
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- end else begin
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- if (sclk_rising) begin
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- smpcnt <= smpcnt + 1;
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- sdout_reg <= smpshift[15];
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+ if (sclk_falling) begin
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+ smpcnt <= smpcnt + 1;
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+ sdout_reg <= smpshift[15];
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+ if (lrck_rising) begin // right channel
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+ smpshift <= (({16'h0, dac_data[31:16]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
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+ samples <= samples + 1;
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+ end else if (lrck_falling) begin // left channel
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+ smpshift <= (({16'h0, dac_data[15:0]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
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+ end else begin
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smpshift <= {smpshift[14:0], 1'b0};
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- end
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+ end
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end
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end
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