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@@ -39,15 +39,27 @@ module spi(
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reg [7:0] cmd_data_r;
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reg [7:0] param_data_r;
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-reg [1:0] SSELr; always @(posedge clk) SSELr <= {SSELr[0], SSEL};
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+reg [2:0] SSELr;
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+reg [2:0] SSELSCKr;
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+
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+always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
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+always @(posedge SCK) SSELSCKr <= {SSELSCKr[1:0], SSEL};
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+
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+wire SSEL_inactive = SSELr[1];
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wire SSEL_active = ~SSELr[1]; // SSEL is active low
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-wire SSEL_startmessage = (SSELr[1:0]==2'b10); // message starts at falling edge
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-wire SSEL_endmessage = (SSELr[1:0]==2'b01); // message stops at rising edge
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+wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
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+wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
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assign endmessage = SSEL_endmessage;
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assign startmessage = SSEL_startmessage;
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// bit count for one SPI byte + byte count for the message
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reg [2:0] bitcnt;
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+initial bitcnt = 3'b000;
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+wire bitcnt_msb = bitcnt[2];
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+reg [2:0] bitcnt_wrap_r;
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+always @(posedge clk) bitcnt_wrap_r <= {bitcnt_wrap_r[1:0], bitcnt_msb};
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+wire byte_received_sync = (bitcnt_wrap_r[2:1] == 2'b10);
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+
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reg [31:0] byte_cnt_r;
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reg byte_received; // high when a byte has been received
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@@ -56,23 +68,26 @@ reg [7:0] byte_data_received;
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assign bit_cnt = bitcnt;
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always @(posedge SCK) begin
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- if(SSEL) bitcnt <= 3'b000;
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- else begin
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- bitcnt <= bitcnt + 3'b001;
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- byte_data_received <= {byte_data_received[6:0], MOSI};
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+ if(SSELSCKr[1]) bitcnt <= 3'b000;
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+ else bitcnt <= bitcnt + 3'b001;
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+end
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+
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+always @(posedge SCK) begin
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+ if(~SSELSCKr[1]) begin
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+ byte_data_received <= {byte_data_received[6:0], MOSI};
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end
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- if(~SSEL && bitcnt==3'b111) byte_received <= 1'b1;
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+ if(~SSELSCKr[1] && bitcnt==3'b111) byte_received <= 1'b1;
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else byte_received <= 1'b0;
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end
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-reg [1:0] byte_received_r;
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-always @(posedge clk) byte_received_r <= {byte_received_r[0], byte_received};
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-wire byte_received_sync = (byte_received_r == 2'b01);
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+//reg [2:0] byte_received_r;
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+//always @(posedge clk) byte_received_r <= {byte_received_r[1:0], byte_received};
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+//wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
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always @(posedge clk) begin
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- if(~SSEL_active)
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+ if(SSEL_inactive) begin
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byte_cnt_r <= 16'h0000;
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- else if(byte_received_sync) begin
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+ end else if(byte_received_sync) begin
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byte_cnt_r <= byte_cnt_r + 16'h0001;
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end
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end
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