Commit History

Author SHA1 Message Date
  Godzil 8d58ca0f7b Big code cleanup and re-indented, finally ! (Thanks astyle!) 10 years ago
  Godzil 7e0186d7a0 Automatically generate the fpga bit .h file 10 years ago
  Godzil 1d928e7091 Merge branch 'udev' into develop 10 years ago
  Godzil 043eeea399 Automate cfgware.h file generation. Will automatically search the .bit file from sd2sneslite rle it and convert to .h file. 11 years ago
  Godzil c4ef438cac Update openocd interface to match my own interface 12 years ago
  Maximilian Rehkopf 82998d7a48 PCB/Rev.E2: Add BOM 11 years ago
  Maximilian Rehkopf 32a0a50c54 update changelog for 0.1.4a 11 years ago
  Maximilian Rehkopf b8d3b952ad firmware: bump version no. to 0.1.4a 11 years ago
  Maximilian Rehkopf e97396adc9 menu: fix DMA initialization (sprite glitches in some games) 11 years ago
  mrehkopf a72476ea6c Merge pull request #24 from Godzil/develop 11 years ago
  Maximilian Rehkopf d47858083a FPGA/Cx4: update user constraints for changed system clock 11 years ago
  Maximilian Rehkopf a7ac2f8900 update changelog 11 years ago
  Maximilian Rehkopf c80bdfbf59 Firmware: do not turn off write LED in case of periodic SRAM saving 11 years ago
  Maximilian Rehkopf a9ea821c0d Firmware: implement MSU1 interface changes 11 years ago
  Maximilian Rehkopf 9baa4b7f9f Firmware: move SaveRAM to $E00000 11 years ago
  Maximilian Rehkopf 2ef480f751 FPGA/DSPx: buffer register input 11 years ago
  Maximilian Rehkopf 6b3a7eb4ae FPGA/SRTC: buffer register/address input 11 years ago
  Maximilian Rehkopf effa2a6972 FPGA/SDDMA: fix clock glitch, adjust RAM write timings 11 years ago
  Maximilian Rehkopf 9253cc45b0 FPGA: implement MSU1 "audio error" status bit 11 years ago
  Maximilian Rehkopf 9fbe61bad1 FPGA: Use internal clock instead of SNES master clock for $213F RMW timing 11 years ago
  Maximilian Rehkopf 968c347986 FPGA/SPI: detect end of byte via MSB toggle instead of constant compare of async input 11 years ago
  Maximilian Rehkopf c231c8b821 FPGA: misc cleanup 11 years ago
  Maximilian Rehkopf 60d7a08117 FPGA: Adjust Cx4 timing to new master clock rate 11 years ago
  Maximilian Rehkopf 7df6909266 FPGA: rework shared memory access FSM 11 years ago
  Maximilian Rehkopf 006ea8c44a FPGA: debug wires 11 years ago
  Maximilian Rehkopf 684e2c3b81 FPGA/BSX: fix checksum registers 11 years ago
  Maximilian Rehkopf 3af05cef91 FPGA/sd2sneslite: add missing file mcu_cmd.v; remove avr_cmd.v 11 years ago
  Maximilian Rehkopf a083d80ff9 FPGA: update clock speed to 88MHz 11 years ago
  Maximilian Rehkopf 8148f5567c FPGA: properly synchronize external signals 11 years ago
  Maximilian Rehkopf 1a52da6272 FPGA: Adjust DAC I²S signal timing 11 years ago