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@@ -248,167 +248,226 @@ always @(posedge CLK2) begin
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else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0;
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end
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-wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr;
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+reg RQ_MCU_RDYr;
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+initial RQ_MCU_RDYr = 1'b1;
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+assign MCU_RDY = RQ_MCU_RDYr;
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-assign ROM_ADDR = (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
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-assign ROM_ADDR0 = (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
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+reg ROM_SAr;
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+initial ROM_SAr = 1'b1;
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+//wire ROM_SA = SNES_FAKE_CLK | ((STATE == ST_IDLE) ^ (~RQ_MCU_RDYr & SNES_cycle_end));
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+wire ROM_SA = ROM_SAr;
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+
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+assign ROM_ADDR = (ROM_SA) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
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+assign ROM_ADDR0 = (ROM_SA) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
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reg ROM_WEr;
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initial ROM_WEr = 1'b1;
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+reg ROM_DOUT_ENr;
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+initial ROM_DOUT_ENr = 1'b0;
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-reg RQ_MCU_RDYr;
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-initial RQ_MCU_RDYr = 1'b1;
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-assign MCU_RDY = RQ_MCU_RDYr;
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+reg[17:0] SNES_DEAD_CNTr;
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+initial SNES_DEAD_CNTr = 0;
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always @(posedge CLK2) begin
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if(MCU_RRQ) begin
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MCU_RD_PENDr <= 1'b1;
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- RQ_MCU_RDYr <= 1'b0;
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+ RQ_MCU_RDYr <= 1'b0;
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+ ROM_ADDRr <= MCU_ADDR;
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end else if(MCU_WRQ) begin
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MCU_WR_PENDr <= 1'b1;
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- RQ_MCU_RDYr <= 1'b0;
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+ RQ_MCU_RDYr <= 1'b0;
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+ ROM_ADDRr <= MCU_ADDR;
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end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
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MCU_RD_PENDr <= 1'b0;
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- MCU_WR_PENDr <= 1'b0;
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- RQ_MCU_RDYr <= 1'b1;
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+ MCU_WR_PENDr <= 1'b0;
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+ RQ_MCU_RDYr <= 1'b1;
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end
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end
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+always @(posedge CLK2) begin
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+ if(~SNES_CPU_CLK) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
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+ else SNES_DEAD_CNTr <= 17'h0;
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+end
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+
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+always @(posedge CLK2) begin
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+ if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
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+ else if(SNES_CPU_CLK) SNES_DEADr <= 1'b0;
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+end
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+
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reg snes_wr_cycle;
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always @(posedge CLK2) begin
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- if(SNES_cycle_start) begin
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- STATE <= ST_SNES_RD_ADDR;
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- end else if(SNES_WR_start) begin
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- STATE <= ST_SNES_WR_ADDR;
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- end else begin
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- case(STATE)
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- ST_IDLE: begin
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- ROM_ADDRr <= MAPPED_SNES_ADDR;
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- if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
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- else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
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- else STATE <= ST_IDLE;
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- end
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- ST_SNES_RD_ADDR: begin
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- STATE <= ST_SNES_RD_WAIT;
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- ST_MEM_DELAYr <= ROM_RD_WAIT;
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- end
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- ST_SNES_RD_WAIT: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
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- else STATE <= ST_SNES_RD_WAIT;
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- if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
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- else SNES_DINr <= ROM_DATA[15:8];
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- end
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- ST_SNES_RD_END: begin
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- STATE <= ST_IDLE;
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- if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
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- else SNES_DINr <= ROM_DATA[15:8];
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- end
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- ST_SNES_WR_ADDR: begin
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- ROM_WEr <= (!IS_SAVERAM);
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- snes_wr_cycle <= 1'b1;
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- STATE <= ST_SNES_WR_WAIT1;
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- ST_MEM_DELAYr <= ROM_WR_WAIT1;
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- end
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- ST_SNES_WR_WAIT1: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA;
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- else STATE <= ST_SNES_WR_WAIT1;
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+ if(SNES_DEADr & SNES_CPU_CLK) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
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+ else
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+ case(STATE)
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+ ST_IDLE: begin
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+ ROM_SAr <= 1'b1;
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+ ROM_DOUT_ENr <= 1'b0;
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+ if(SNES_cycle_start & ~SNES_WRITE) begin
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+ STATE <= ST_SNES_WR_ADDR;
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+ if(IS_SAVERAM) begin
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+ ROM_WEr <= 1'b0;
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+ ROM_DOUT_ENr <= 1'b1;
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+ end
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+ end else if(SNES_cycle_start) begin
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+// STATE <= ST_SNES_RD_ADDR;
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+ STATE <= ST_SNES_RD_END;
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+ SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
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+ end else if(SNES_DEADr & MCU_RD_PENDr) begin
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+ STATE <= ST_MCU_RD_ADDR;
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+ end else if(SNES_DEADr & MCU_WR_PENDr) begin
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+ STATE <= ST_MCU_WR_ADDR;
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end
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- ST_SNES_WR_DATA: begin
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- ROM_DOUTr <= SNES_DATA;
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+ end
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+ ST_SNES_RD_ADDR: begin
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+ ST_MEM_DELAYr <= ROM_RD_WAIT;
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+ STATE <= ST_SNES_RD_WAIT;
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+ end
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+ ST_SNES_RD_WAIT: begin
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+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
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+// if(ST_MEM_DELAYr == 0) begin
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+// end
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+// else STATE <= ST_SNES_RD_WAIT;
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+ end
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+
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+ ST_SNES_WR_ADDR: begin
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+ ST_MEM_DELAYr <= ROM_WR_WAIT1;
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+ STATE <= ST_SNES_WR_WAIT1;
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+ end
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+ ST_SNES_WR_WAIT1: begin
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+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
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+ if(ST_MEM_DELAYr == 0) begin
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ST_MEM_DELAYr <= ROM_WR_WAIT2;
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- STATE <= ST_SNES_WR_WAIT2;
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+ STATE <= ST_SNES_WR_WAIT2;
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+ ROM_DOUTr <= SNES_DATA;
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end
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- ST_SNES_WR_WAIT2: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END;
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- else STATE <= ST_SNES_WR_WAIT2;
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- end
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- ST_SNES_WR_END: begin
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- STATE <= ST_IDLE;
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+ else STATE <= ST_SNES_WR_WAIT1;
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+ end
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+ ST_SNES_WR_WAIT2: begin
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+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
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+ if(ST_MEM_DELAYr == 0) begin
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+ STATE <= ST_SNES_WR_END;
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ROM_WEr <= 1'b1;
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- snes_wr_cycle <= 1'b0;
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- end
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- ST_MCU_RD_ADDR: begin
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- ROM_ADDRr <= MCU_ADDR;
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- STATE <= ST_MCU_RD_WAIT;
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- ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
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- end
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- ST_MCU_RD_WAIT: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) begin
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- STATE <= ST_MCU_RD_WAIT2;
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- ST_MEM_DELAYr <= 4'h2;
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- end
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- else STATE <= ST_MCU_RD_WAIT;
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- if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0];
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- else MCU_DINr <= ROM_DATA[15:8];
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- end
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- ST_MCU_RD_WAIT2: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) begin
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- STATE <= ST_MCU_RD_END;
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- end else STATE <= ST_MCU_RD_WAIT2;
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- end
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- ST_MCU_RD_END: begin
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- STATE <= ST_IDLE;
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- end
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- ST_MCU_WR_ADDR: begin
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- ROM_ADDRr <= MCU_ADDR;
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- STATE <= ST_MCU_WR_WAIT;
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- ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
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- ROM_DOUTr <= MCU_DOUT;
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- ROM_WEr <= 1'b0;
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end
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- ST_MCU_WR_WAIT: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) begin
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- ROM_WEr <= 1'b1;
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- STATE <= ST_MCU_WR_WAIT2;
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- ST_MEM_DELAYr <= 4'h2;
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- end
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- else STATE <= ST_MCU_WR_WAIT;
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- end
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- ST_MCU_WR_WAIT2: begin
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- ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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- if(ST_MEM_DELAYr == 4'h0) begin
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- STATE <= ST_MCU_WR_END;
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- end else STATE <= ST_MCU_WR_WAIT2;
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+ else STATE <= ST_SNES_WR_WAIT2;
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+ end
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+ ST_SNES_RD_END, ST_SNES_WR_END: begin
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+ ROM_DOUT_ENr <= 1'b0;
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+ if(MCU_RD_PENDr) begin
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+ STATE <= ST_MCU_RD_ADDR;
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+ end else if(MCU_WR_PENDr) begin
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+ STATE <= ST_MCU_WR_ADDR;
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+ end else STATE <= ST_IDLE;
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+ end
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+ ST_MCU_RD_ADDR: begin
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+ ROM_SAr <= 1'b0;
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+ ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
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+ STATE <= ST_MCU_RD_WAIT;
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+ end
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+ ST_MCU_RD_WAIT: begin
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+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
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+ if(ST_MEM_DELAYr == 0) begin
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+ STATE <= ST_MCU_RD_END;
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end
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- ST_MCU_WR_END: begin
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- STATE <= ST_IDLE;
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+ else STATE <= ST_MCU_RD_WAIT;
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+ end
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+ ST_MCU_RD_END: begin
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+ MCU_DINr <= ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
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+ STATE <= ST_IDLE;
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+ end
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+
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+ ST_MCU_WR_ADDR: begin
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+ ROM_DOUTr <= MCU_DOUT;
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+ ROM_SAr <= 1'b0;
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+ ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
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+ STATE <= ST_MCU_WR_WAIT;
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+ ROM_DOUT_ENr <= 1'b1;
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+ ROM_WEr <= 1'b0;
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+ end
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+ ST_MCU_WR_WAIT: begin
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+ ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
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+ if(ST_MEM_DELAYr == 0) begin
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+ ROM_WEr <= 1'b1;
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+ STATE <= ST_MCU_WR_END;
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end
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+ else STATE <= ST_MCU_WR_WAIT;
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+ end
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+ ST_MCU_WR_END: begin
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+ ROM_DOUT_ENr <= 1'b0;
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+ STATE <= ST_IDLE;
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+ end
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+ endcase
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+end
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- endcase
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- end
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+reg ROM_WE_1;
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+
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+always @(posedge CLK2) begin
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+ ROM_WE_1 <= ROM_WE;
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end
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assign ROM_DATA[7:0] = ROM_ADDR0
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- ?(!ROM_WE ? ROM_DOUTr : 8'bZ)
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+ ?(ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ)
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:8'bZ;
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assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
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- :(!ROM_WE ? ROM_DOUTr : 8'bZ);
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-
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-assign ROM_WE = ROM_WEr | (ASSERT_SNES_ADDR & ~snes_wr_cycle);
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+ :(ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
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+
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+assign ROM_WE = ROM_WEr;
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+
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+// OE always active. Overridden by WE when needed.
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assign ROM_OE = 1'b0;
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assign ROM_CE = 1'b0;
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-assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
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-assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
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+assign ROM_BHE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
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+assign ROM_BLE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
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assign SNES_DATABUS_OE = ((IS_ROM & SNES_CS)
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|(!IS_ROM & !IS_SAVERAM)
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- |(SNES_READ & SNES_WRITE)
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+ |(SNES_READr[0] & SNES_WRITEr[0])
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);
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-assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
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+assign SNES_DATABUS_DIR = (!SNES_READr[0])
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+ ? 1'b1
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+ : 1'b0;
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assign SNES_IRQ = 1'b0;
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assign p113_out = 1'b0;
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+/*
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+wire [35:0] CONTROL0;
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+
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+icon icon (
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+ .CONTROL0(CONTROL0) // INOUT BUS [35:0]
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+);
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+
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+ila_srtc ila (
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+ .CONTROL(CONTROL0), // INOUT BUS [35:0]
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+ .CLK(CLK2), // IN
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+ .TRIG0(SNES_ADDR), // IN BUS [23:0]
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+ .TRIG1(SNES_DATA), // IN BUS [7:0]
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+ .TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, ROM_WEr, ROM_WE, ROM_DOUT_ENr, ROM_SA, DBG_mcu_nextaddr, SNES_DATABUS_DIR, SNES_DATABUS_OE}), // IN BUS [15:0]
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+ .TRIG3({bsx_data_ovr, SPI_SCK, SPI_MISO, SPI_MOSI, spi_cmd_ready, spi_param_ready, spi_input_data, SD_DAT}), // IN BUS [17:0]
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+ .TRIG4(ROM_ADDRr), // IN BUS [23:0]
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+ .TRIG5(ROM_DATA), // IN BUS [15:0]
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+ .TRIG6(MCU_DINr), // IN BUS [7:0]
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+ .TRIG7(spi_byte_cnt[3:0])
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+);
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+*/
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+/*
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+ila_srtc ila (
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+ .CONTROL(CONTROL0), // INOUT BUS [35:0]
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+ .CLK(CLK2), // IN
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+ .TRIG0(SD_DMA_DBG_cyclecnt), // IN BUS [23:0]
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+ .TRIG1(SD_DMA_SRAM_DATA), // IN BUS [7:0]
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+ .TRIG2({SPI_SCK, SPI_MOSI, SPI_MISO, spi_cmd_ready, SD_DMA_SRAM_WE, SD_DMA_EN, SD_CLK, SD_DAT, SD_DMA_NEXTADDR, SD_DMA_STATUS, 3'b000}), // IN BUS [15:0]
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+ .TRIG3({spi_cmd_data, spi_param_data}), // IN BUS [17:0]
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+ .TRIG4(ROM_ADDRr), // IN BUS [23:0]
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+ .TRIG5(ROM_DATA), // IN BUS [15:0]
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+ .TRIG6(MCU_DINr), // IN BUS [7:0]
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+ .TRIG7(ST_MEM_DELAYr)
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+);
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+*/
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+
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endmodule
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