Browse Source

FPGA: debug wires

Maximilian Rehkopf 12 years ago
parent
commit
006ea8c44a

+ 68 - 9
verilog/sd2snes/main.v

@@ -148,6 +148,18 @@ wire [9:0] bs_page;
 wire [8:0] bs_page_offset;
 wire bs_page_enable;
 
+
+wire [4:0] DBG_srtc_state;
+wire DBG_srtc_we_rising;
+wire [3:0] DBG_srtc_ptr;
+wire [5:0] DBG_srtc_we_sreg;
+wire [13:0] DBG_msu_address;
+wire DBG_msu_reg_oe_rising;
+wire DBG_msu_reg_oe_falling;
+wire DBG_msu_reg_we_rising;
+wire [2:0] SD_DMA_DBG_clkcnt;
+wire [10:0] SD_DMA_DBG_cyclecnt;
+
 sd_dma snes_sd_dma(
   .CLK(CLK2),
   .SD_DAT(SD_DAT),
@@ -161,7 +173,9 @@ sd_dma snes_sd_dma(
   .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
   .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
   .SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
-  .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK)
+  .SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
+  .DBG_cyclecnt(SD_DMA_DBG_cyclecnt),
+  .DBG_clkcnt(SD_DMA_DBG_clkcnt)
 );
 
 wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
@@ -193,7 +207,11 @@ srtc snes_srtc (
   .enable(srtc_enable),
   .rtc_data_out(srtc_rtc_data_out),
   .rtc_we(srtc_rtc_we),
-  .reset(srtc_reset)
+  .reset(srtc_reset),
+  .srtc_state(DBG_srtc_state),
+  .srtc_reg_we_rising(DBG_srtc_we_rising),
+  .srtc_rtc_ptr(DBG_srtc_ptr),
+  .srtc_we_sreg(DBG_srtc_we_sreg)
 );
 
 rtc snes_rtc (
@@ -225,7 +243,12 @@ msu snes_msu (
   .status_set_bits(msu_status_set_bits),
   .status_reset_we(msu_status_reset_we),
   .msu_address_ext(msu_ptr_addr),
-  .msu_address_ext_write(msu_addr_reset)
+  .msu_address_ext_write(msu_addr_reset),
+  .DBG_msu_reg_oe_rising(DBG_msu_reg_oe_rising),
+  .DBG_msu_reg_oe_falling(DBG_msu_reg_oe_falling),
+  .DBG_msu_reg_we_rising(DBG_msu_reg_we_rising),
+  .DBG_msu_address(DBG_msu_address),
+  .DBG_msu_address_ext_write_rising(DBG_msu_address_ext_write_rising)
 );
 
 bsx snes_bsx(
@@ -349,7 +372,8 @@ mcu_cmd snes_mcu_cmd(
   .mcu_rrq(MCU_RRQ),
   .mcu_wrq(MCU_WRQ),
   .mcu_rq_rdy(MCU_RDY),
-  .region_out(mcu_region)
+  .region_out(mcu_region),
+  .DBG_mcu_nextaddr(DBG_mcu_nextaddr)
 );
 
 wire [7:0] DCM_STATUS;
@@ -693,18 +717,53 @@ assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 :
                          srtc_enable ? (SNES_READ & SNES_WRITE) :
 								 bs_page_enable ? (SNES_READ) :
                          r213f_enable & !SNES_PARD ? 1'b0 :
+								 (snescmd_wr_enable | snescmd_rd_enable) & !SNES_PARD ? 1'b0 :
                          ((IS_ROM & SNES_CS)
                           |(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR)
-                          |(SNES_READ & SNES_WRITE)
+                          |(SNES_READr[0] & SNES_WRITEr[0])
                          );
 
-assign SNES_DATABUS_DIR = (!SNES_READ | (!SNES_PARD & r213f_enable))
-                           ? 1'b1 ^ r213f_forceread
+assign SNES_DATABUS_DIR = (!SNES_READr[0] | (!SNES_PARD & (r213f_enable | snescmd_rd_enable)))
+                           ? 1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
                            : 1'b0;
 
-assign IRQ_DIR = 1'b0;
-assign SNES_IRQ = 1'bZ;
+assign SNES_IRQ = 1'b0;
 
 assign p113_out = 1'b0;
 
+/*
+wire [35:0] CONTROL0;
+
+icon icon (
+    .CONTROL0(CONTROL0) // INOUT BUS [35:0]
+);
+
+ila_srtc ila (
+    .CONTROL(CONTROL0), // INOUT BUS [35:0]
+    .CLK(CLK2), // IN
+    .TRIG0(SNES_ADDR), // IN BUS [23:0]
+    .TRIG1(SNES_DATA), // IN BUS [7:0]
+    .TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, ROM_WEr, ROM_WE, ROM_DOUT_ENr, ROM_SA, DBG_mcu_nextaddr, SNES_DATABUS_DIR, SNES_DATABUS_OE}),	 // IN BUS [15:0]
+    .TRIG3({bsx_data_ovr, SPI_SCK, SPI_MISO, SPI_MOSI, spi_cmd_ready, spi_param_ready, spi_input_data, SD_DAT}), // IN BUS [17:0]
+    .TRIG4(ROM_ADDRr), // IN BUS [23:0]
+    .TRIG5(ROM_DATA), // IN BUS [15:0]
+    .TRIG6(MCU_DINr), // IN BUS [7:0]
+	 .TRIG7(spi_byte_cnt[3:0])
+);
+*/
+/*
+ila_srtc ila (
+    .CONTROL(CONTROL0), // INOUT BUS [35:0]
+    .CLK(CLK2), // IN
+    .TRIG0(SD_DMA_DBG_cyclecnt), // IN BUS [23:0]
+    .TRIG1(SD_DMA_SRAM_DATA), // IN BUS [7:0]
+    .TRIG2({SPI_SCK, SPI_MOSI, SPI_MISO, spi_cmd_ready, SD_DMA_SRAM_WE, SD_DMA_EN, SD_CLK, SD_DAT, SD_DMA_NEXTADDR, SD_DMA_STATUS, 3'b000}),	 // IN BUS [15:0]
+    .TRIG3({spi_cmd_data, spi_param_data}), // IN BUS [17:0]
+    .TRIG4(ROM_ADDRr), // IN BUS [23:0]
+    .TRIG5(ROM_DATA), // IN BUS [15:0]
+    .TRIG6(MCU_DINr), // IN BUS [7:0]
+	 .TRIG7(ST_MEM_DELAYr)
+);
+*/
+
 endmodule

+ 5 - 1
verilog/sd2snes/mcu_cmd.v

@@ -97,7 +97,10 @@ module mcu_cmd(
   
   output reg region_out,
   // SNES sync/clk
-  input snes_sysclk
+  input snes_sysclk,
+  
+  // debug
+  output DBG_mcu_nextaddr
 );
 
 initial begin
@@ -545,4 +548,5 @@ assign mcu_mapper = MAPPER_BUF;
 assign rom_mask_out = ROM_MASK;
 assign saveram_mask_out = SAVERAM_MASK;
 
+assign DBG_mcu_nextaddr = mcu_nextaddr;
 endmodule

+ 22 - 3
verilog/sd2snes/msu.v

@@ -38,7 +38,13 @@ module msu(
   input [5:0] status_set_bits,
   input status_reset_we,
   input [13:0] msu_address_ext,
-  input msu_address_ext_write
+  input msu_address_ext_write,
+  
+  output DBG_msu_reg_oe_rising,
+  output DBG_msu_reg_oe_falling,
+  output DBG_msu_reg_we_rising,
+  output [13:0] DBG_msu_address,
+  output DBG_msu_address_ext_write_rising
 );
 
 reg [2:0] reg_addr_r [3:0];
@@ -96,14 +102,27 @@ reg audio_busy_r;
 reg data_start_r;
 reg data_busy_r;
 reg ctrl_start_r;
+reg audio_error_r;
 reg [1:0] audio_ctrl_r;
 reg [1:0] audio_status_r;
 
 initial begin
-  audio_busy_r <= 1'b1;
-  data_busy_r <= 1'b1;
+  audio_busy_r = 1'b1;
+  data_busy_r = 1'b1;
+  audio_error_r = 1'b0;
+  volume_r = 8'h00;
+  addr_out_r = 32'h00000000;
+  track_out_r = 16'h0000;
+  data_start_r = 1'b0;
+  audio_start_r = 1'b0;
 end
 
+assign DBG_msu_address = msu_address;
+assign DBG_msu_reg_oe_rising = reg_oe_rising;
+assign DBG_msu_reg_oe_falling = reg_oe_falling;
+assign DBG_msu_reg_we_rising = reg_we_rising;
+assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
+
 assign status_out = {msu_address_r[13], // 6
                      audio_start_r,     // 5
                      data_start_r,      // 4

+ 4 - 1
verilog/sd2snes/sd_dma.v

@@ -31,7 +31,10 @@ module sd_dma(
   input [10:0] SD_DMA_PARTIAL_START,
   input [10:0] SD_DMA_PARTIAL_END,
   input SD_DMA_START_MID_BLOCK,
-  input SD_DMA_END_MID_BLOCK
+  input SD_DMA_END_MID_BLOCK,
+  
+  output [10:0] DBG_cyclecnt,
+  output [2:0] DBG_clkcnt
 );
 
 reg [10:0] SD_DMA_STARTr;

+ 7 - 1
verilog/sd2snes/srtc.v

@@ -29,7 +29,13 @@ module srtc(
   input reg_oe,
   input enable,
   output rtc_we,
-  input reset
+  input reset,
+  
+  /* DEBUG */
+  output [4:0] srtc_state,
+  output srtc_reg_we_rising,
+  output [3:0] srtc_rtc_ptr,
+  output [5:0] srtc_we_sreg
 );
 
 reg [59:0] rtc_data_r;

+ 79 - 14
verilog/sd2snes_cx4/main.v

@@ -607,44 +607,109 @@ always @(posedge SYSCLK2) begin
   end
 end
 
+always @(posedge CLK2) begin
+  if(SNES_WR_end & snescmd_wr_enable) begin
+    snescmd_regs[SNES_ADDR[3:0]] <= SNES_DATA;
+  end
+end
+
+reg ROM_WE_1;
+reg MCU_WRITE_1;
+
+always @(posedge CLK2) begin
+  ROM_WE_1 <= ROM_WE;
+  MCU_WRITE_1<= MCU_WRITE;
+end
+
 assign ROM_DATA[7:0] = ROM_ADDR0
-                       ?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
-                                        : (!ROM_WE ? ROM_DOUTr : 8'bZ)
+                       ?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
+							                   /*: ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA */
+                                        : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
                         )
                        :8'bZ;
 
 assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
-                        :(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
-                                         : (!ROM_WE ? ROM_DOUTr : 8'bZ)
+                        :(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
+								                 /*:  ((~SNES_WRITE & (IS_WRITABLE | IS_FLASHWR)) ? SNES_DATA */
+                                         : (ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ) //)
                          );
 
 assign ROM_WE = SD_DMA_TO_ROM
                 ?MCU_WRITE
-                :ROM_WEr | (ASSERT_SNES_ADDR & ~snes_wr_cycle);
+                :/*(SNES_FAKE_CLK & (IS_WRITABLE | IS_FLASHWR)) ? SNES_WRITE :*/ ROM_WEr;
 
 // OE always active. Overridden by WE when needed.
 assign ROM_OE = 1'b0;
 
 assign ROM_CE = 1'b0;
 
-assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
-assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
+assign ROM_BHE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
+assign ROM_BLE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
 
 assign SNES_DATABUS_OE = msu_enable ? 1'b0 :
                          cx4_enable ? 1'b0 :
-                         (cx4_active & cx4_vect_enable) ? 1'b0 :
+								 (cx4_active & cx4_vect_enable) ? 1'b0 :
                          r213f_enable & !SNES_PARD ? 1'b0 :
-                         ((!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
-                          |(SNES_READ & SNES_WRITE)
+								 (snescmd_wr_enable | snescmd_rd_enable) & !SNES_PARD ? 1'b0 :
+                         ((IS_ROM & SNES_CS)
+                          |(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
+                          |(SNES_READr[0] & SNES_WRITEr[0])
                          );
 
-assign SNES_DATABUS_DIR = (!SNES_READ | (!SNES_PARD & r213f_enable))
-                           ? 1'b1 ^ r213f_forceread
+assign SNES_DATABUS_DIR = (!SNES_READr[0] | (!SNES_PARD & (r213f_enable | snescmd_rd_enable)))
+                           ? 1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
                            : 1'b0;
 
-assign IRQ_DIR = 1'b0;
-assign SNES_IRQ = 1'bZ;
+assign SNES_IRQ = 1'b0;
 
 assign p113_out = 1'b0;
 
+/*
+wire [35:0] CONTROL0;
+
+icon icon (
+    .CONTROL0(CONTROL0) // INOUT BUS [35:0]
+);
+
+ila ila (
+    .CONTROL(CONTROL0), // INOUT BUS [35:0]
+    .CLK(CLK2), // IN
+    .TRIG0(SNES_ADDR), // IN BUS [23:0]
+    .TRIG1(SNES_DATA), // IN BUS [7:0]
+    .TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, cx4_active, ROM_WE, ROM_DOUT_ENr, ROM_SA, CX4_RRQ, CX4_RDY, ROM_CA}), // IN BUS [15:0]
+    .TRIG3(ROM_ADDRr), // IN BUS [23:0]
+    .TRIG4(CX4_ADDRr), // IN BUS [23:0]
+    .TRIG5(ROM_DATA), // IN BUS [15:0]
+    .TRIG6(CX4_DINr), // IN BUS [7:0]
+    .TRIG7(STATE) // IN BUS [21:0]
+);*/
+/*
+ila ila (
+    .CONTROL(CONTROL0), // INOUT BUS [35:0]
+    .CLK(CLK2), // IN
+    .TRIG0(SNES_ADDR), // IN BUS [23:0]
+    .TRIG1(SNES_DATA), // IN BUS [7:0]
+    .TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, ROM_WEr, ROM_WE, ROM_DOUT_ENr, ROM_SA, DBG_mcu_nextaddr, SNES_DATABUS_DIR, SNES_DATABUS_OE}),	 // IN BUS [15:0]
+    .TRIG3({bsx_data_ovr, SPI_SCK, SPI_MISO, SPI_MOSI, spi_cmd_ready, spi_param_ready, spi_input_data, SD_DAT}), // IN BUS [17:0]
+    .TRIG4(ROM_ADDRr), // IN BUS [23:0]
+    .TRIG5(ROM_DATA), // IN BUS [15:0]
+    .TRIG6(MCU_DINr), // IN BUS [7:0]
+	 .TRIG7(spi_byte_cnt[3:0])
+);
+*/
+/*
+ila_srtc ila (
+    .CONTROL(CONTROL0), // INOUT BUS [35:0]
+    .CLK(CLK2), // IN
+    .TRIG0(SD_DMA_DBG_cyclecnt), // IN BUS [23:0]
+    .TRIG1(SD_DMA_SRAM_DATA), // IN BUS [7:0]
+    .TRIG2({SPI_SCK, SPI_MOSI, SPI_MISO, spi_cmd_ready, SD_DMA_SRAM_WE, SD_DMA_EN, SD_CLK, SD_DAT, SD_DMA_NEXTADDR, SD_DMA_STATUS, 3'b000}),	 // IN BUS [15:0]
+    .TRIG3({spi_cmd_data, spi_param_data}), // IN BUS [17:0]
+    .TRIG4(ROM_ADDRr), // IN BUS [23:0]
+    .TRIG5(ROM_DATA), // IN BUS [15:0]
+    .TRIG6(MCU_DINr), // IN BUS [7:0]
+	 .TRIG7(ST_MEM_DELAYr)
+);
+*/
+
 endmodule

+ 22 - 3
verilog/sd2snes_cx4/msu.v

@@ -38,7 +38,13 @@ module msu(
   input [5:0] status_set_bits,
   input status_reset_we,
   input [13:0] msu_address_ext,
-  input msu_address_ext_write
+  input msu_address_ext_write,
+  
+  output DBG_msu_reg_oe_rising,
+  output DBG_msu_reg_oe_falling,
+  output DBG_msu_reg_we_rising,
+  output [13:0] DBG_msu_address,
+  output DBG_msu_address_ext_write_rising
 );
 
 reg [2:0] reg_addr_r [3:0];
@@ -96,14 +102,27 @@ reg audio_busy_r;
 reg data_start_r;
 reg data_busy_r;
 reg ctrl_start_r;
+reg audio_error_r;
 reg [1:0] audio_ctrl_r;
 reg [1:0] audio_status_r;
 
 initial begin
-  audio_busy_r <= 1'b1;
-  data_busy_r <= 1'b1;
+  audio_busy_r = 1'b1;
+  data_busy_r = 1'b1;
+  audio_error_r = 1'b0;
+  volume_r = 8'h00;
+  addr_out_r = 32'h00000000;
+  track_out_r = 16'h0000;
+  data_start_r = 1'b0;
+  audio_start_r = 1'b0;
 end
 
+assign DBG_msu_address = msu_address;
+assign DBG_msu_reg_oe_rising = reg_oe_rising;
+assign DBG_msu_reg_oe_falling = reg_oe_falling;
+assign DBG_msu_reg_we_rising = reg_we_rising;
+assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
+
 assign status_out = {msu_address_r[13], // 6
                      audio_start_r,     // 5
                      data_start_r,      // 4

+ 175 - 116
verilog/sd2sneslite/main.v

@@ -248,167 +248,226 @@ always @(posedge CLK2) begin
   else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0;
 end
 
-wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr;
+reg RQ_MCU_RDYr;
+initial RQ_MCU_RDYr = 1'b1;
+assign MCU_RDY = RQ_MCU_RDYr;
 
-assign ROM_ADDR  = (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
-assign ROM_ADDR0 = (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
+reg ROM_SAr;
+initial ROM_SAr = 1'b1;
+//wire ROM_SA = SNES_FAKE_CLK | ((STATE == ST_IDLE) ^ (~RQ_MCU_RDYr & SNES_cycle_end));
+wire ROM_SA = ROM_SAr;
+
+assign ROM_ADDR  = (ROM_SA) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
+assign ROM_ADDR0 = (ROM_SA) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
 
 reg ROM_WEr;
 initial ROM_WEr = 1'b1;
+reg ROM_DOUT_ENr;
+initial ROM_DOUT_ENr = 1'b0;
 
-reg RQ_MCU_RDYr;
-initial RQ_MCU_RDYr = 1'b1;
-assign MCU_RDY = RQ_MCU_RDYr;
+reg[17:0] SNES_DEAD_CNTr;
+initial SNES_DEAD_CNTr = 0;
 
 always @(posedge CLK2) begin
   if(MCU_RRQ) begin
     MCU_RD_PENDr <= 1'b1;
-	 RQ_MCU_RDYr <= 1'b0;
+    RQ_MCU_RDYr <= 1'b0;
+    ROM_ADDRr <= MCU_ADDR;
   end else if(MCU_WRQ) begin
     MCU_WR_PENDr <= 1'b1;
-	 RQ_MCU_RDYr <= 1'b0;
+    RQ_MCU_RDYr <= 1'b0;
+    ROM_ADDRr <= MCU_ADDR;
   end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
     MCU_RD_PENDr <= 1'b0;
-	 MCU_WR_PENDr <= 1'b0;
-	 RQ_MCU_RDYr <= 1'b1;
+    MCU_WR_PENDr <= 1'b0;
+    RQ_MCU_RDYr <= 1'b1;
   end
 end
 
+always @(posedge CLK2) begin
+  if(~SNES_CPU_CLK) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
+  else SNES_DEAD_CNTr <= 17'h0;
+end
+
+always @(posedge CLK2) begin
+  if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
+  else if(SNES_CPU_CLK) SNES_DEADr <= 1'b0;
+end
+
 reg snes_wr_cycle;
 
 always @(posedge CLK2) begin
-  if(SNES_cycle_start) begin
-    STATE <= ST_SNES_RD_ADDR;
-  end else if(SNES_WR_start) begin
-    STATE <= ST_SNES_WR_ADDR;
-  end else begin
-    case(STATE)
-	   ST_IDLE: begin
-		  ROM_ADDRr <= MAPPED_SNES_ADDR;
-		  if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
-		  else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
-        else STATE <= ST_IDLE;
-		end
-		ST_SNES_RD_ADDR: begin
-		  STATE <= ST_SNES_RD_WAIT;
-		  ST_MEM_DELAYr <= ROM_RD_WAIT;
-		end
-		ST_SNES_RD_WAIT: begin
-		  ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-		  if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
-		  else STATE <= ST_SNES_RD_WAIT;
-		  if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
-		  else SNES_DINr <= ROM_DATA[15:8];
-		end
-		ST_SNES_RD_END: begin
-		  STATE <= ST_IDLE;
-		  if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
-		  else SNES_DINr <= ROM_DATA[15:8];
-		end
-      ST_SNES_WR_ADDR: begin
-        ROM_WEr <= (!IS_SAVERAM);
-        snes_wr_cycle <= 1'b1;
-		  STATE <= ST_SNES_WR_WAIT1;
-		  ST_MEM_DELAYr <= ROM_WR_WAIT1;
-		end
-		ST_SNES_WR_WAIT1: begin
-		  ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-		  if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA;
-		  else STATE <= ST_SNES_WR_WAIT1;
+  if(SNES_DEADr & SNES_CPU_CLK) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
+  else
+  case(STATE)
+    ST_IDLE: begin
+	   ROM_SAr <= 1'b1;
+		ROM_DOUT_ENr <= 1'b0;
+	   if(SNES_cycle_start & ~SNES_WRITE) begin
+		  STATE <= ST_SNES_WR_ADDR;
+		  if(IS_SAVERAM) begin
+		    ROM_WEr <= 1'b0;
+          ROM_DOUT_ENr <= 1'b1;
+        end
+		end else if(SNES_cycle_start) begin
+//		  STATE <= ST_SNES_RD_ADDR;		  
+        STATE <= ST_SNES_RD_END;
+        SNES_DOUTr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
+		end else if(SNES_DEADr & MCU_RD_PENDr) begin
+		  STATE <= ST_MCU_RD_ADDR;
+		end else if(SNES_DEADr & MCU_WR_PENDr) begin
+		  STATE <= ST_MCU_WR_ADDR;
 		end
-		ST_SNES_WR_DATA: begin
-        ROM_DOUTr <= SNES_DATA;
+	 end
+	 ST_SNES_RD_ADDR: begin
+	   ST_MEM_DELAYr <= ROM_RD_WAIT;
+		STATE <= ST_SNES_RD_WAIT;
+	 end
+	 ST_SNES_RD_WAIT: begin
+	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
+//		if(ST_MEM_DELAYr == 0) begin
+//		end
+//		else STATE <= ST_SNES_RD_WAIT;
+	 end
+	 
+	 ST_SNES_WR_ADDR: begin
+	   ST_MEM_DELAYr <= ROM_WR_WAIT1;
+	   STATE <= ST_SNES_WR_WAIT1;
+	 end
+	 ST_SNES_WR_WAIT1: begin
+	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
+		if(ST_MEM_DELAYr == 0) begin
 		  ST_MEM_DELAYr <= ROM_WR_WAIT2;
-		  STATE <= ST_SNES_WR_WAIT2;
+        STATE <= ST_SNES_WR_WAIT2;
+		  ROM_DOUTr <= SNES_DATA;
 		end
-      ST_SNES_WR_WAIT2: begin
-		  ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-		  if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END;
-		  else STATE <= ST_SNES_WR_WAIT2;
-		end
-		ST_SNES_WR_END: begin
-		  STATE <= ST_IDLE;
+		else STATE <= ST_SNES_WR_WAIT1;
+	 end
+	 ST_SNES_WR_WAIT2: begin
+	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
+		if(ST_MEM_DELAYr == 0) begin
+        STATE <= ST_SNES_WR_END;
 		  ROM_WEr <= 1'b1;
-		  snes_wr_cycle <= 1'b0;
-		end
-		ST_MCU_RD_ADDR: begin
-		  ROM_ADDRr <= MCU_ADDR;
-		  STATE <= ST_MCU_RD_WAIT;
-		  ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
-		end
-		ST_MCU_RD_WAIT: begin
-		  ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-		  if(ST_MEM_DELAYr == 4'h0) begin
-		    STATE <= ST_MCU_RD_WAIT2;
-			 ST_MEM_DELAYr <= 4'h2;
-		  end
-		  else STATE <= ST_MCU_RD_WAIT;
-		  if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0];
-		  else MCU_DINr <= ROM_DATA[15:8];
-      end
-		ST_MCU_RD_WAIT2: begin
-		  ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-		  if(ST_MEM_DELAYr == 4'h0) begin
-		    STATE <= ST_MCU_RD_END;
-		  end else STATE <= ST_MCU_RD_WAIT2;
-		end
-		ST_MCU_RD_END: begin
-		  STATE <= ST_IDLE;
-		end
-		ST_MCU_WR_ADDR: begin
-		  ROM_ADDRr <= MCU_ADDR;
-		  STATE <= ST_MCU_WR_WAIT;
-		  ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
-		  ROM_DOUTr <= MCU_DOUT;
-		  ROM_WEr <= 1'b0;
 		end
-		ST_MCU_WR_WAIT: begin
-		  ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-		  if(ST_MEM_DELAYr == 4'h0) begin
-          ROM_WEr <= 1'b1;
-		    STATE <= ST_MCU_WR_WAIT2;
-			 ST_MEM_DELAYr <= 4'h2;
-		  end
-		  else STATE <= ST_MCU_WR_WAIT;
-      end
-		ST_MCU_WR_WAIT2: begin
-		  ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
-		  if(ST_MEM_DELAYr == 4'h0) begin
-		    STATE <= ST_MCU_WR_END;
-        end else STATE <= ST_MCU_WR_WAIT2;
+		else STATE <= ST_SNES_WR_WAIT2;
+    end
+	 ST_SNES_RD_END, ST_SNES_WR_END: begin
+	   ROM_DOUT_ENr <= 1'b0;		
+      if(MCU_RD_PENDr) begin
+        STATE <= ST_MCU_RD_ADDR;
+      end else if(MCU_WR_PENDr) begin
+        STATE <= ST_MCU_WR_ADDR;
+      end else STATE <= ST_IDLE;
+    end
+    ST_MCU_RD_ADDR: begin
+      ROM_SAr <= 1'b0;
+		ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
+		STATE <= ST_MCU_RD_WAIT;
+	 end
+	 ST_MCU_RD_WAIT: begin
+	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
+		if(ST_MEM_DELAYr == 0) begin
+        STATE <= ST_MCU_RD_END;
 		end
-		ST_MCU_WR_END: begin
-		  STATE <= ST_IDLE;
+		else STATE <= ST_MCU_RD_WAIT;
+	 end
+	 ST_MCU_RD_END: begin
+      MCU_DINr <= ROM_ADDRr[0] ? ROM_DATA[7:0] : ROM_DATA[15:8];
+	   STATE <= ST_IDLE;
+	 end
+	 
+	 ST_MCU_WR_ADDR: begin
+      ROM_DOUTr <= MCU_DOUT;
+      ROM_SAr <= 1'b0;
+	   ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
+		STATE <= ST_MCU_WR_WAIT;
+		ROM_DOUT_ENr <= 1'b1;
+		ROM_WEr <= 1'b0;
+	 end
+	 ST_MCU_WR_WAIT: begin
+	   ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
+		if(ST_MEM_DELAYr == 0) begin
+		  ROM_WEr <= 1'b1;
+		  STATE <= ST_MCU_WR_END;
 		end
+		else STATE <= ST_MCU_WR_WAIT;	 
+	 end
+	 ST_MCU_WR_END: begin
+		ROM_DOUT_ENr <= 1'b0;
+	   STATE <= ST_IDLE;
+	 end
+  endcase
+end
 
-	 endcase
-  end
+reg ROM_WE_1;
+
+always @(posedge CLK2) begin
+  ROM_WE_1 <= ROM_WE;
 end
 
 assign ROM_DATA[7:0] = ROM_ADDR0
-                       ?(!ROM_WE ? ROM_DOUTr : 8'bZ)
+                       ?(ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ)
                        :8'bZ;
 
 assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
-                        :(!ROM_WE ? ROM_DOUTr : 8'bZ);
-                         
-assign ROM_WE = ROM_WEr | (ASSERT_SNES_ADDR & ~snes_wr_cycle);
+                        :(ROM_DOUT_ENr ? ROM_DOUTr : 8'bZ);
+
+assign ROM_WE = ROM_WEr;
+
+// OE always active. Overridden by WE when needed.
 assign ROM_OE = 1'b0;
 
 assign ROM_CE = 1'b0;
 
-assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
-assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
+assign ROM_BHE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ ROM_ADDR0 /*: 1'b0*/;
+assign ROM_BLE = /*(~SD_DMA_TO_ROM & ~ROM_WE & ~ROM_SA) ?*/ !ROM_ADDR0 /*: 1'b0*/;
 
 assign SNES_DATABUS_OE = ((IS_ROM & SNES_CS)
                           |(!IS_ROM & !IS_SAVERAM)
-                          |(SNES_READ & SNES_WRITE)
+                          |(SNES_READr[0] & SNES_WRITEr[0])
                          );
 
-assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
+assign SNES_DATABUS_DIR = (!SNES_READr[0])
+                           ? 1'b1
+                           : 1'b0;
 
 assign SNES_IRQ = 1'b0;
 
 assign p113_out = 1'b0;
 
+/*
+wire [35:0] CONTROL0;
+
+icon icon (
+    .CONTROL0(CONTROL0) // INOUT BUS [35:0]
+);
+
+ila_srtc ila (
+    .CONTROL(CONTROL0), // INOUT BUS [35:0]
+    .CLK(CLK2), // IN
+    .TRIG0(SNES_ADDR), // IN BUS [23:0]
+    .TRIG1(SNES_DATA), // IN BUS [7:0]
+    .TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, ROM_WEr, ROM_WE, ROM_DOUT_ENr, ROM_SA, DBG_mcu_nextaddr, SNES_DATABUS_DIR, SNES_DATABUS_OE}),	 // IN BUS [15:0]
+    .TRIG3({bsx_data_ovr, SPI_SCK, SPI_MISO, SPI_MOSI, spi_cmd_ready, spi_param_ready, spi_input_data, SD_DAT}), // IN BUS [17:0]
+    .TRIG4(ROM_ADDRr), // IN BUS [23:0]
+    .TRIG5(ROM_DATA), // IN BUS [15:0]
+    .TRIG6(MCU_DINr), // IN BUS [7:0]
+	 .TRIG7(spi_byte_cnt[3:0])
+);
+*/
+/*
+ila_srtc ila (
+    .CONTROL(CONTROL0), // INOUT BUS [35:0]
+    .CLK(CLK2), // IN
+    .TRIG0(SD_DMA_DBG_cyclecnt), // IN BUS [23:0]
+    .TRIG1(SD_DMA_SRAM_DATA), // IN BUS [7:0]
+    .TRIG2({SPI_SCK, SPI_MOSI, SPI_MISO, spi_cmd_ready, SD_DMA_SRAM_WE, SD_DMA_EN, SD_CLK, SD_DAT, SD_DMA_NEXTADDR, SD_DMA_STATUS, 3'b000}),	 // IN BUS [15:0]
+    .TRIG3({spi_cmd_data, spi_param_data}), // IN BUS [17:0]
+    .TRIG4(ROM_ADDRr), // IN BUS [23:0]
+    .TRIG5(ROM_DATA), // IN BUS [15:0]
+    .TRIG6(MCU_DINr), // IN BUS [7:0]
+	 .TRIG7(ST_MEM_DELAYr)
+);
+*/
+
 endmodule