msu.v 5.8 KB

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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 14:55:04 12/14/2010
  7. // Design Name:
  8. // Module Name: msu
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module msu(
  22. input clkin,
  23. input enable,
  24. input [13:0] pgm_address,
  25. input [7:0] pgm_data,
  26. input pgm_we,
  27. input [2:0] reg_addr,
  28. input [7:0] reg_data_in,
  29. output [7:0] reg_data_out,
  30. input reg_oe,
  31. input reg_we,
  32. output [6:0] status_out,
  33. output [7:0] volume_out,
  34. output volume_latch_out,
  35. output [31:0] addr_out,
  36. output [15:0] track_out,
  37. input [5:0] status_reset_bits,
  38. input [5:0] status_set_bits,
  39. input status_reset_we,
  40. input [13:0] msu_address_ext,
  41. input msu_address_ext_write,
  42. output DBG_msu_reg_oe_rising,
  43. output DBG_msu_reg_oe_falling,
  44. output DBG_msu_reg_we_rising,
  45. output [13:0] DBG_msu_address,
  46. output DBG_msu_address_ext_write_rising
  47. );
  48. reg [2:0] reg_addr_r [3:0];
  49. always @(posedge clkin) begin
  50. reg_addr_r[3] <= reg_addr_r[2];
  51. reg_addr_r[2] <= reg_addr_r[1];
  52. reg_addr_r[1] <= reg_addr_r[0];
  53. reg_addr_r[0] <= reg_addr;
  54. end
  55. reg [1:0] status_reset_we_r;
  56. always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
  57. wire status_reset_en = (status_reset_we_r == 2'b01);
  58. reg [13:0] msu_address_r;
  59. wire [13:0] msu_address = msu_address_r;
  60. initial msu_address_r = 13'b0;
  61. wire [7:0] msu_data;
  62. reg [7:0] msu_data_r;
  63. reg [2:0] msu_address_ext_write_sreg;
  64. always @(posedge clkin)
  65. msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[1:0], msu_address_ext_write};
  66. wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[2:1] == 2'b01);
  67. reg [4:0] reg_enable_sreg;
  68. initial reg_enable_sreg = 5'b11111;
  69. always @(posedge clkin) reg_enable_sreg <= {reg_enable_sreg[3:0], enable};
  70. reg [5:0] reg_oe_sreg;
  71. always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[4:0], reg_oe};
  72. wire reg_oe_rising = reg_enable_sreg[4] && (reg_oe_sreg[5:1] == 5'b00001);
  73. wire reg_oe_falling = reg_enable_sreg[1] && (reg_oe_sreg[5:1] == 5'b11110);
  74. reg [5:0] reg_we_sreg;
  75. always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[4:0], reg_we};
  76. wire reg_we_rising = reg_enable_sreg[4] && (reg_we_sreg[5:1] == 5'b00001);
  77. reg [31:0] addr_out_r;
  78. assign addr_out = addr_out_r;
  79. reg [15:0] track_out_r;
  80. assign track_out = track_out_r;
  81. reg [7:0] volume_r;
  82. assign volume_out = volume_r;
  83. reg volume_start_r;
  84. assign volume_latch_out = volume_start_r;
  85. reg audio_start_r;
  86. reg audio_busy_r;
  87. reg data_start_r;
  88. reg data_busy_r;
  89. reg ctrl_start_r;
  90. reg audio_error_r;
  91. reg [1:0] audio_ctrl_r;
  92. reg [1:0] audio_status_r;
  93. initial begin
  94. audio_busy_r = 1'b1;
  95. data_busy_r = 1'b1;
  96. audio_error_r = 1'b0;
  97. volume_r = 8'h00;
  98. addr_out_r = 32'h00000000;
  99. track_out_r = 16'h0000;
  100. data_start_r = 1'b0;
  101. audio_start_r = 1'b0;
  102. end
  103. assign DBG_msu_address = msu_address;
  104. assign DBG_msu_reg_oe_rising = reg_oe_rising;
  105. assign DBG_msu_reg_oe_falling = reg_oe_falling;
  106. assign DBG_msu_reg_we_rising = reg_we_rising;
  107. assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
  108. assign status_out = {msu_address_r[13], // 6
  109. audio_start_r, // 5
  110. data_start_r, // 4
  111. volume_start_r, // 3
  112. audio_ctrl_r, // 2:1
  113. ctrl_start_r}; // 0
  114. initial msu_address_r = 14'h1234;
  115. msu_databuf snes_msu_databuf (
  116. .clka(clkin),
  117. .wea(~pgm_we), // Bus [0 : 0]
  118. .addra(pgm_address), // Bus [13 : 0]
  119. .dina(pgm_data), // Bus [7 : 0]
  120. .clkb(clkin),
  121. .addrb(msu_address), // Bus [13 : 0]
  122. .doutb(msu_data)
  123. ); // Bus [7 : 0]
  124. reg [7:0] data_out_r;
  125. assign reg_data_out = data_out_r;
  126. always @(posedge clkin) begin
  127. case(reg_addr_r[3])
  128. 3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, 4'b0001};
  129. 3'h1: data_out_r <= msu_data;
  130. 3'h2: data_out_r <= 8'h53;
  131. 3'h3: data_out_r <= 8'h2d;
  132. 3'h4: data_out_r <= 8'h4d;
  133. 3'h5: data_out_r <= 8'h53;
  134. 3'h6: data_out_r <= 8'h55;
  135. 3'h7: data_out_r <= 8'h31;
  136. endcase
  137. end
  138. always @(posedge clkin) begin
  139. if(reg_we_rising) begin
  140. case(reg_addr_r[1])
  141. 3'h0: addr_out_r[7:0] <= reg_data_in;
  142. 3'h1: addr_out_r[15:8] <= reg_data_in;
  143. 3'h2: addr_out_r[23:16] <= reg_data_in;
  144. 3'h3: begin
  145. addr_out_r[31:24] <= reg_data_in;
  146. data_start_r <= 1'b1;
  147. data_busy_r <= 1'b1;
  148. end
  149. 3'h4: begin
  150. track_out_r[7:0] <= reg_data_in;
  151. end
  152. 3'h5: begin
  153. track_out_r[15:8] <= reg_data_in;
  154. audio_start_r <= 1'b1;
  155. audio_busy_r <= 1'b1;
  156. end
  157. 3'h6: begin
  158. volume_r <= reg_data_in;
  159. volume_start_r <= 1'b1;
  160. end
  161. 3'h7: begin
  162. if(!audio_busy_r) begin
  163. audio_ctrl_r <= reg_data_in[1:0];
  164. ctrl_start_r <= 1'b1;
  165. end
  166. end
  167. endcase
  168. end else if (status_reset_en) begin
  169. audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
  170. if(status_reset_bits[5]) audio_start_r <= 1'b0;
  171. data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
  172. if(status_reset_bits[4]) data_start_r <= 1'b0;
  173. // volume_start_r <= (volume_start_r | status_set_bits[3]) & ~status_reset_bits[3];
  174. audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
  175. ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
  176. end else begin
  177. volume_start_r <= 1'b0;
  178. end
  179. end
  180. always @(posedge clkin) begin
  181. if(msu_address_ext_write_rising)
  182. msu_address_r <= msu_address_ext;
  183. else if(reg_addr_r[3] == 3'h1 && reg_oe_rising) begin
  184. msu_address_r <= msu_address_r + 1;
  185. end
  186. end
  187. endmodule