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FPGA/Cx4: update user constraints for changed system clock

Maximilian Rehkopf 11 years ago
parent
commit
d47858083a
1 changed files with 2 additions and 2 deletions
  1. 2 2
      verilog/sd2snes_cx4/main.ucf

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+ 2 - 2
verilog/sd2snes_cx4/main.ucf


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