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FPGA/Cx4: update user constraints for changed system clock
Maximilian Rehkopf
11 years ago
parent
a7ac2f8900
commit
d47858083a
1 changed files
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2 additions
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2 deletions
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verilog/sd2snes_cx4/main.ucf
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verilog/sd2snes_cx4/main.ucf
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