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@@ -90,8 +90,8 @@
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#define DMADone (1<<8)
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#define DownComplete (1<<9)
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#define UpComplete (1<<10)
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-#define DMAInProgress (1<<11) /* DMA controller is still busy.*/
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-#define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/
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+#define DMAInProgress (1<<11) /* DMA controller is still busy.*/
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+#define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/
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/* Polling Registers */
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@@ -100,17 +100,17 @@
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/* Register window 0 offets */
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-#define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */
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-#define Wn0EepromData 12 /* Window 0: EEPROM results register. */
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-#define IntrStatus 0x0E /* Valid in all windows. */
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+#define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */
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+#define Wn0EepromData 12 /* Window 0: EEPROM results register. */
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+#define IntrStatus 0x0E /* Valid in all windows. */
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/* Register window 0 EEPROM bits */
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#define EEPROM_Read 0x80
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#define EEPROM_WRITE 0x40
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#define EEPROM_ERASE 0xC0
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-#define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */
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-#define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */
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+#define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */
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+#define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */
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/* EEPROM locations. */
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@@ -135,7 +135,7 @@
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#define RxStatus 0x18
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#define Timer 0x1A
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#define TxStatus 0x1B
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-#define TxFree 0x1C /* Remaining free bytes in Tx buffer. */
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+#define TxFree 0x1C /* Remaining free bytes in Tx buffer. */
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/* Register Window 2 */
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@@ -143,23 +143,23 @@
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/* Register Window 3: MAC/config bits */
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-#define Wn3_Config 0 /* Internal Configuration */
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+#define Wn3_Config 0 /* Internal Configuration */
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#define Wn3_MAC_Ctrl 6
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#define Wn3_Options 8
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#define BFEXT(value, offset, bitcount) \
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((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
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-#define BFINS(lhs, rhs, offset, bitcount) \
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+#define BFINS(lhs, rhs, offset, bitcount) \
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(((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
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(((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
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-#define RAM_SIZE(v) BFEXT(v, 0, 3)
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+#define RAM_SIZE(v) BFEXT(v, 0, 3)
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#define RAM_WIDTH(v) BFEXT(v, 3, 1)
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-#define RAM_SPEED(v) BFEXT(v, 4, 2)
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-#define ROM_SIZE(v) BFEXT(v, 6, 2)
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+#define RAM_SPEED(v) BFEXT(v, 4, 2)
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+#define ROM_SIZE(v) BFEXT(v, 6, 2)
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#define RAM_SPLIT(v) BFEXT(v, 16, 2)
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-#define XCVR(v) BFEXT(v, 20, 4)
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+#define XCVR(v) BFEXT(v, 20, 4)
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#define AUTOSELECT(v) BFEXT(v, 24, 1)
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/* Register Window 4: Xcvr/media bits */
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@@ -186,20 +186,20 @@
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#define DownListPtr 0x24
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#define FragAddr 0x28
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#define FragLen 0x2c
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-#define TxFreeThreshold 0x2f
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+#define TxFreeThreshold 0x2f
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#define UpPktStatus 0x30
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-#define UpListPtr 0x38
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+#define UpListPtr 0x38
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/* The Rx and Tx descriptor lists. */
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-#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
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-#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
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+#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
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+#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
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struct rx_desc_3com {
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- u32 next; /* Last entry points to 0 */
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- u32 status; /* FSH -> Frame Start Header */
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- u32 addr; /* Up to 63 addr/len pairs possible */
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- u32 length; /* Set LAST_FRAG to indicate last pair */
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+ u32 next; /* Last entry points to 0 */
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+ u32 status; /* FSH -> Frame Start Header */
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+ u32 addr; /* Up to 63 addr/len pairs possible */
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+ u32 length; /* Set LAST_FRAG to indicate last pair */
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};
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/* Values for the Rx status entry. */
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@@ -214,8 +214,8 @@ struct rx_desc_3com {
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#define UDPChksumValid (1<<31)
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struct tx_desc_3com {
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- u32 next; /* Last entry points to 0 */
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- u32 status; /* bits 0:12 length, others see below */
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+ u32 next; /* Last entry points to 0 */
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+ u32 status; /* bits 0:12 length, others see below */
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u32 addr;
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u32 length;
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};
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@@ -227,7 +227,7 @@ struct tx_desc_3com {
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#define AddIPChksum 0x02000000
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#define AddTCPChksum 0x04000000
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#define AddUDPChksum 0x08000000
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-#define TxIntrUploaded 0x80000000 /* IRQ when in FIFO, but maybe not sent. */
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+#define TxIntrUploaded 0x80000000 /* IRQ when in FIFO, but maybe not sent. */
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/* XCVR Types */
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@@ -240,19 +240,19 @@ struct tx_desc_3com {
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#define XCVR_MII 6
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#define XCVR_NWAY 8
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#define XCVR_ExtMII 9
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-#define XCVR_Default 10 /* I don't think this is correct -> should have been 0x10 if Auto Negotiate */
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+#define XCVR_Default 10 /* I don't think this is correct -> should have been 0x10 if Auto Negotiate */
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-struct descriptor { /* A generic descriptor. */
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- u32 next; /* Last entry points to 0 */
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- u32 status; /* FSH -> Frame Start Header */
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- u32 addr; /* Up to 63 addr/len pairs possible */
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- u32 length; /* Set LAST_FRAG to indicate last pair */
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+struct descriptor { /* A generic descriptor. */
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+ u32 next; /* Last entry points to 0 */
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+ u32 status; /* FSH -> Frame Start Header */
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+ u32 addr; /* Up to 63 addr/len pairs possible */
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+ u32 length; /* Set LAST_FRAG to indicate last pair */
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};
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/* Misc. definitions */
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-#define NUM_RX_DESC PKTBUFSRX * 10
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-#define NUM_TX_DESC 1 /* Number of TX descriptors */
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+#define NUM_RX_DESC PKTBUFSRX * 10
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+#define NUM_TX_DESC 1 /* Number of TX descriptors */
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#define TOUT_LOOP 1000000
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@@ -266,17 +266,17 @@ struct descriptor { /* A generic descriptor. */
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#undef ETH_DEBUG
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#ifdef ETH_DEBUG
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-#define PRINTF(fmt,args...) printf (fmt ,##args)
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+#define PRINTF(fmt,args...) printf (fmt ,##args)
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#else
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#define PRINTF(fmt,args...)
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#endif
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-static struct rx_desc_3com *rx_ring; /* RX descriptor ring */
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-static struct tx_desc_3com *tx_ring; /* TX descriptor ring */
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-static u8 rx_buffer[NUM_RX_DESC][PKTSIZE_ALIGN]; /* storage for the incoming messages */
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-static int rx_next = 0; /* RX descriptor ring pointer */
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-static int tx_next = 0; /* TX descriptor ring pointer */
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+static struct rx_desc_3com *rx_ring; /* RX descriptor ring */
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+static struct tx_desc_3com *tx_ring; /* TX descriptor ring */
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+static u8 rx_buffer[NUM_RX_DESC][PKTSIZE_ALIGN];/* storage for the incoming messages */
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+static int rx_next = 0; /* RX descriptor ring pointer */
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+static int tx_next = 0; /* TX descriptor ring pointer */
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static int tx_threshold;
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static void init_rx_ring(struct eth_device* dev);
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@@ -369,171 +369,163 @@ static int issue_and_wait(struct eth_device* dev, int command)
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return 0;
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}
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-/* Determine network media type and set up 3com accordingly */
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+/* Determine network media type and set up 3com accordingly */
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/* I think I'm going to start with something known first like 10baseT */
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-static int auto_negotiate(struct eth_device* dev)
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+static int auto_negotiate (struct eth_device *dev)
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{
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- int i;
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+ int i;
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- EL3WINDOW(dev, 1);
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+ EL3WINDOW (dev, 1);
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- /* Wait for Auto negotiation to complete */
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- for (i = 0; i <= 1000; i++)
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- {
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- if (ETH_INW(dev, 2) & 0x04)
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- break;
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- udelay(100);
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+ /* Wait for Auto negotiation to complete */
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+ for (i = 0; i <= 1000; i++) {
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+ if (ETH_INW (dev, 2) & 0x04)
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+ break;
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+ udelay (100);
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- if (i == 1000)
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- {
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- PRINTF("Error: Auto negotiation failed\n");
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- return 0;
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+ if (i == 1000) {
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+ PRINTF ("Error: Auto negotiation failed\n");
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+ return 0;
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+ }
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}
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- }
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- return 1;
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+ return 1;
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}
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-void eth_interrupt(struct eth_device *dev)
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+void eth_interrupt (struct eth_device *dev)
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{
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- u16 status = ETH_STATUS(dev);
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+ u16 status = ETH_STATUS (dev);
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- printf("eth0: status = 0x%04x\n", status);
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+ printf ("eth0: status = 0x%04x\n", status);
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- if (!(status & IntLatch))
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- return;
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+ if (!(status & IntLatch))
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+ return;
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+
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+ if (status & (1 << 6)) {
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+ ETH_CMD (dev, AckIntr | (1 << 6));
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+ printf ("Acknowledged Interrupt command\n");
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+ }
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+
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+ if (status & DownComplete) {
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+ ETH_CMD (dev, AckIntr | DownComplete);
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+ printf ("Acknowledged DownComplete\n");
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+ }
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+
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+ if (status & UpComplete) {
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+ ETH_CMD (dev, AckIntr | UpComplete);
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+ printf ("Acknowledged UpComplete\n");
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+ }
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- if (status & (1<<6))
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- {
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- ETH_CMD(dev, AckIntr | (1<<6));
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- printf("Acknowledged Interrupt command\n");
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- }
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-
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- if (status & DownComplete)
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- {
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- ETH_CMD(dev, AckIntr | DownComplete);
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- printf("Acknowledged DownComplete\n");
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- }
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-
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- if (status & UpComplete)
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- {
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- ETH_CMD(dev, AckIntr | UpComplete);
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- printf("Acknowledged UpComplete\n");
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- }
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-
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- ETH_CMD(dev, AckIntr | IntLatch);
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- printf("Acknowledged IntLatch\n");
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+ ETH_CMD (dev, AckIntr | IntLatch);
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+ printf ("Acknowledged IntLatch\n");
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}
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-int eth_3com_initialize(bd_t *bis)
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+int eth_3com_initialize (bd_t * bis)
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{
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u32 eth_iobase = 0, status;
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int card_number = 0, ret;
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- struct eth_device* dev;
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+ struct eth_device *dev;
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pci_dev_t devno;
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char *s;
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- s = getenv("3com_base");
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+ s = getenv ("3com_base");
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/* Find ethernet controller on the PCI bus */
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- if ((devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0)) < 0)
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- {
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- PRINTF("Error: Cannot find the ethernet device on the PCI bus\n");
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+ if ((devno =
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+ pci_find_device (PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C,
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+ 0)) < 0) {
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+ PRINTF ("Error: Cannot find the ethernet device on the PCI bus\n");
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goto Done;
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}
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- if (s)
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- {
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- unsigned long base = atoi(s);
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- pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, base | 0x01);
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+ if (s) {
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+ unsigned long base = atoi (s);
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+
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+ pci_write_config_dword (devno, PCI_BASE_ADDRESS_0,
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+ base | 0x01);
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}
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- ret = pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, ð_iobase);
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+ ret = pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, ð_iobase);
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eth_iobase &= ~0xf;
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- PRINTF("eth: 3Com Found at Address: 0x%x\n", eth_iobase);
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+ PRINTF ("eth: 3Com Found at Address: 0x%x\n", eth_iobase);
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- pci_write_config_dword(devno, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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+ pci_write_config_dword (devno, PCI_COMMAND,
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+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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+ PCI_COMMAND_MASTER);
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- /* Check if I/O accesses and Bus Mastering are enabled */
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+ /* Check if I/O accesses and Bus Mastering are enabled */
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- ret = pci_read_config_dword(devno, PCI_COMMAND, &status);
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+ ret = pci_read_config_dword (devno, PCI_COMMAND, &status);
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- if (!(status & PCI_COMMAND_IO))
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- {
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- printf("Error: Cannot enable IO access.\n");
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+ if (!(status & PCI_COMMAND_IO)) {
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+ printf ("Error: Cannot enable IO access.\n");
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goto Done;
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}
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- if (!(status & PCI_COMMAND_MEMORY))
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- {
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- printf("Error: Cannot enable MEMORY access.\n");
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+ if (!(status & PCI_COMMAND_MEMORY)) {
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+ printf ("Error: Cannot enable MEMORY access.\n");
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goto Done;
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}
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- if (!(status & PCI_COMMAND_MASTER))
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- {
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- printf("Error: Cannot enable Bus Mastering.\n");
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+ if (!(status & PCI_COMMAND_MASTER)) {
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+ printf ("Error: Cannot enable Bus Mastering.\n");
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goto Done;
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}
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- dev = (struct eth_device*) malloc(sizeof(*dev)); /*struct eth_device)); */
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+ dev = (struct eth_device *) malloc (sizeof (*dev)); /*struct eth_device)); */
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- sprintf(dev->name, "3Com 3c920c#%d", card_number);
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+ sprintf (dev->name, "3Com 3c920c#%d", card_number);
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dev->iobase = eth_iobase;
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- dev->priv = (void*) devno;
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- dev->init = eth_3com_init;
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- dev->halt = eth_3com_halt;
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- dev->send = eth_3com_send;
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- dev->recv = eth_3com_recv;
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+ dev->priv = (void *) devno;
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+ dev->init = eth_3com_init;
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+ dev->halt = eth_3com_halt;
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+ dev->send = eth_3com_send;
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+ dev->recv = eth_3com_recv;
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- eth_register(dev);
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+ eth_register (dev);
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-/* { */
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-/* char interrupt; */
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-/* devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */
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-/* pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */
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+/* { */
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+/* char interrupt; */
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+/* devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */
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+/* pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */
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-/* printf("Installing eth0 interrupt handler to %d\n", interrupt); */
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-/* irq_install_handler(interrupt, eth_interrupt, dev); */
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-/* } */
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+/* printf("Installing eth0 interrupt handler to %d\n", interrupt); */
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+/* irq_install_handler(interrupt, eth_interrupt, dev); */
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+/* } */
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card_number++;
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/* Set the latency timer for value */
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- s = getenv("3com_latency");
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- if (s)
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- {
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- ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, (unsigned char)atoi(s));
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|
- }
|
|
|
- else ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x0a);
|
|
|
+ s = getenv ("3com_latency");
|
|
|
+ if (s) {
|
|
|
+ ret = pci_write_config_byte (devno, PCI_LATENCY_TIMER,
|
|
|
+ (unsigned char) atoi (s));
|
|
|
+ } else
|
|
|
+ ret = pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x0a);
|
|
|
|
|
|
- read_hw_addr(dev, bis); /* get the MAC address from Window 2*/
|
|
|
+ read_hw_addr (dev, bis); /* get the MAC address from Window 2 */
|
|
|
|
|
|
/* Reset the ethernet controller */
|
|
|
|
|
|
PRINTF ("Issuing reset command....\n");
|
|
|
- if (!issue_and_wait(dev, TotalReset))
|
|
|
- {
|
|
|
- printf("Error: Cannot reset ethernet controller.\n");
|
|
|
+ if (!issue_and_wait (dev, TotalReset)) {
|
|
|
+ printf ("Error: Cannot reset ethernet controller.\n");
|
|
|
goto Done;
|
|
|
- }
|
|
|
- else
|
|
|
+ } else
|
|
|
PRINTF ("Ethernet controller reset.\n");
|
|
|
|
|
|
/* allocate memory for rx and tx rings */
|
|
|
|
|
|
- if(!(rx_ring = memalign(sizeof(struct rx_desc_3com) * NUM_RX_DESC, 16)))
|
|
|
- {
|
|
|
+ if (!(rx_ring = memalign (sizeof (struct rx_desc_3com) * NUM_RX_DESC, 16))) {
|
|
|
PRINTF ("Cannot allocate memory for RX_RING.....\n");
|
|
|
goto Done;
|
|
|
}
|
|
|
|
|
|
- if (!(tx_ring = memalign(sizeof(struct tx_desc_3com) * NUM_TX_DESC, 16)))
|
|
|
- {
|
|
|
+ if (!(tx_ring = memalign (sizeof (struct tx_desc_3com) * NUM_TX_DESC, 16))) {
|
|
|
PRINTF ("Cannot allocate memory for TX_RING.....\n");
|
|
|
goto Done;
|
|
|
}
|
|
@@ -543,219 +535,208 @@ Done:
|
|
|
}
|
|
|
|
|
|
|
|
|
-static int eth_3com_init(struct eth_device* dev, bd_t *bis)
|
|
|
+static int eth_3com_init (struct eth_device *dev, bd_t * bis)
|
|
|
{
|
|
|
int i, status = 0;
|
|
|
int tx_cur, loop;
|
|
|
u16 status_enable, intr_enable;
|
|
|
struct descriptor *ias_cmd;
|
|
|
|
|
|
- /* Determine what type of network the machine is connected to */
|
|
|
- /* presently drops the connect to 10Mbps */
|
|
|
+ /* Determine what type of network the machine is connected to */
|
|
|
+ /* presently drops the connect to 10Mbps */
|
|
|
|
|
|
- if (!auto_negotiate(dev))
|
|
|
- {
|
|
|
- printf("Error: Cannot determine network media.\n");
|
|
|
+ if (!auto_negotiate (dev)) {
|
|
|
+ printf ("Error: Cannot determine network media.\n");
|
|
|
goto Done;
|
|
|
}
|
|
|
|
|
|
- issue_and_wait(dev, TxReset);
|
|
|
- issue_and_wait(dev, RxReset|0x04);
|
|
|
+ issue_and_wait (dev, TxReset);
|
|
|
+ issue_and_wait (dev, RxReset | 0x04);
|
|
|
|
|
|
/* Switch to register set 7 for normal use. */
|
|
|
- EL3WINDOW(dev, 7);
|
|
|
+ EL3WINDOW (dev, 7);
|
|
|
|
|
|
/* Initialize Rx and Tx rings */
|
|
|
|
|
|
- init_rx_ring(dev);
|
|
|
- purge_tx_ring(dev);
|
|
|
+ init_rx_ring (dev);
|
|
|
+ purge_tx_ring (dev);
|
|
|
|
|
|
- ETH_CMD(dev, SetRxFilter | RxStation | RxBroadcast | RxProm);
|
|
|
+ ETH_CMD (dev, SetRxFilter | RxStation | RxBroadcast | RxProm);
|
|
|
|
|
|
- issue_and_wait(dev,SetTxStart|0x07ff);
|
|
|
+ issue_and_wait (dev, SetTxStart | 0x07ff);
|
|
|
|
|
|
/* Below sets which indication bits to be seen. */
|
|
|
|
|
|
- status_enable = SetStatusEnb | HostError | DownComplete | UpComplete | (1<<6);
|
|
|
- ETH_CMD(dev, status_enable);
|
|
|
+ status_enable =
|
|
|
+ SetStatusEnb | HostError | DownComplete | UpComplete | (1 <<
|
|
|
+ 6);
|
|
|
+ ETH_CMD (dev, status_enable);
|
|
|
|
|
|
/* Below sets no bits are to cause an interrupt since this is just polling */
|
|
|
|
|
|
- intr_enable = SetIntrEnb;
|
|
|
+ intr_enable = SetIntrEnb;
|
|
|
/* intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6); */
|
|
|
- ETH_CMD(dev, intr_enable);
|
|
|
- ETH_OUTB(dev, 127, UpPoll);
|
|
|
+ ETH_CMD (dev, intr_enable);
|
|
|
+ ETH_OUTB (dev, 127, UpPoll);
|
|
|
|
|
|
/* Ack all pending events, and set active indicator mask */
|
|
|
|
|
|
- ETH_CMD(dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq);
|
|
|
- ETH_CMD(dev, intr_enable);
|
|
|
+ ETH_CMD (dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq);
|
|
|
+ ETH_CMD (dev, intr_enable);
|
|
|
|
|
|
/* Tell the adapter where the RX ring is located */
|
|
|
|
|
|
- issue_and_wait(dev,UpStall); /* Stall and set the UplistPtr */
|
|
|
- ETH_OUTL(dev, (u32)&rx_ring[rx_next], UpListPtr);
|
|
|
- ETH_CMD(dev, RxEnable); /* Enable the receiver. */
|
|
|
- issue_and_wait(dev,UpUnstall);
|
|
|
+ issue_and_wait (dev, UpStall); /* Stall and set the UplistPtr */
|
|
|
+ ETH_OUTL (dev, (u32) & rx_ring[rx_next], UpListPtr);
|
|
|
+ ETH_CMD (dev, RxEnable); /* Enable the receiver. */
|
|
|
+ issue_and_wait (dev, UpUnstall);
|
|
|
|
|
|
/* Send the Individual Address Setup frame */
|
|
|
|
|
|
- tx_cur = tx_next;
|
|
|
- tx_next = ((tx_next+1) % NUM_TX_DESC);
|
|
|
+ tx_cur = tx_next;
|
|
|
+ tx_next = ((tx_next + 1) % NUM_TX_DESC);
|
|
|
|
|
|
- ias_cmd = (struct descriptor *)&tx_ring[tx_cur];
|
|
|
- ias_cmd->status = cpu_to_le32(1<<31); /* set DnIndicate bit. */
|
|
|
- ias_cmd->next = 0;
|
|
|
- ias_cmd->addr = cpu_to_le32((u32)&bis->bi_enetaddr[0]);
|
|
|
- ias_cmd->length = cpu_to_le32(6 | LAST_FRAG);
|
|
|
+ ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
|
|
|
+ ias_cmd->status = cpu_to_le32 (1 << 31); /* set DnIndicate bit. */
|
|
|
+ ias_cmd->next = 0;
|
|
|
+ ias_cmd->addr = cpu_to_le32 ((u32) & bis->bi_enetaddr[0]);
|
|
|
+ ias_cmd->length = cpu_to_le32 (6 | LAST_FRAG);
|
|
|
|
|
|
/* Tell the adapter where the TX ring is located */
|
|
|
|
|
|
- ETH_CMD(dev, TxEnable); /* Enable transmitter. */
|
|
|
- issue_and_wait(dev, DownStall); /* Stall and set the DownListPtr. */
|
|
|
- ETH_OUTL(dev, (u32)&tx_ring[tx_cur], DownListPtr);
|
|
|
- issue_and_wait(dev, DownUnstall);
|
|
|
- for (i=0; !(ETH_STATUS(dev) & DownComplete); i++)
|
|
|
- {
|
|
|
- if (i >= TOUT_LOOP)
|
|
|
- {
|
|
|
- PRINTF("TX Ring status (Init): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status));
|
|
|
- PRINTF("ETH_STATUS: 0x%x\n", ETH_STATUS(dev));
|
|
|
+ ETH_CMD (dev, TxEnable); /* Enable transmitter. */
|
|
|
+ issue_and_wait (dev, DownStall); /* Stall and set the DownListPtr. */
|
|
|
+ ETH_OUTL (dev, (u32) & tx_ring[tx_cur], DownListPtr);
|
|
|
+ issue_and_wait (dev, DownUnstall);
|
|
|
+ for (i = 0; !(ETH_STATUS (dev) & DownComplete); i++) {
|
|
|
+ if (i >= TOUT_LOOP) {
|
|
|
+ PRINTF ("TX Ring status (Init): 0x%4x\n",
|
|
|
+ le32_to_cpu (tx_ring[tx_cur].status));
|
|
|
+ PRINTF ("ETH_STATUS: 0x%x\n", ETH_STATUS (dev));
|
|
|
goto Done;
|
|
|
}
|
|
|
}
|
|
|
- if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */
|
|
|
- {
|
|
|
- ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */
|
|
|
- issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */
|
|
|
- ETH_OUTL(dev, 0, DownListPtr);
|
|
|
- issue_and_wait(dev, DownUnstall);
|
|
|
+ if (ETH_STATUS (dev) & DownComplete) { /* If DownLoad Complete ACK the bit */
|
|
|
+ ETH_CMD (dev, AckIntr | DownComplete); /* acknowledge the indication bit */
|
|
|
+ issue_and_wait (dev, DownStall); /* stall and clear DownListPtr */
|
|
|
+ ETH_OUTL (dev, 0, DownListPtr);
|
|
|
+ issue_and_wait (dev, DownUnstall);
|
|
|
}
|
|
|
status = 1;
|
|
|
-
|
|
|
Done:
|
|
|
return status;
|
|
|
}
|
|
|
|
|
|
-int eth_3com_send(struct eth_device* dev, volatile void *packet, int length)
|
|
|
+int eth_3com_send (struct eth_device *dev, volatile void *packet, int length)
|
|
|
{
|
|
|
int i, status = 0;
|
|
|
int tx_cur;
|
|
|
|
|
|
- if (length <= 0)
|
|
|
- {
|
|
|
- PRINTF("eth: bad packet size: %d\n", length);
|
|
|
+ if (length <= 0) {
|
|
|
+ PRINTF ("eth: bad packet size: %d\n", length);
|
|
|
goto Done;
|
|
|
}
|
|
|
|
|
|
- tx_cur = tx_next;
|
|
|
- tx_next = (tx_next+1) % NUM_TX_DESC;
|
|
|
+ tx_cur = tx_next;
|
|
|
+ tx_next = (tx_next + 1) % NUM_TX_DESC;
|
|
|
|
|
|
- tx_ring[tx_cur].status = cpu_to_le32(1<<31); /* set DnIndicate bit */
|
|
|
- tx_ring[tx_cur].next = 0;
|
|
|
- tx_ring[tx_cur].addr = cpu_to_le32(((u32) packet));
|
|
|
- tx_ring[tx_cur].length = cpu_to_le32(length | LAST_FRAG);
|
|
|
+ tx_ring[tx_cur].status = cpu_to_le32 (1 << 31); /* set DnIndicate bit */
|
|
|
+ tx_ring[tx_cur].next = 0;
|
|
|
+ tx_ring[tx_cur].addr = cpu_to_le32 (((u32) packet));
|
|
|
+ tx_ring[tx_cur].length = cpu_to_le32 (length | LAST_FRAG);
|
|
|
|
|
|
/* Send the packet */
|
|
|
|
|
|
- issue_and_wait(dev, DownStall); /* stall and set the DownListPtr */
|
|
|
- ETH_OUTL(dev, (u32) &tx_ring[tx_cur], DownListPtr);
|
|
|
- issue_and_wait(dev, DownUnstall);
|
|
|
+ issue_and_wait (dev, DownStall); /* stall and set the DownListPtr */
|
|
|
+ ETH_OUTL (dev, (u32) & tx_ring[tx_cur], DownListPtr);
|
|
|
+ issue_and_wait (dev, DownUnstall);
|
|
|
|
|
|
- for (i=0; !(ETH_STATUS(dev) & DownComplete); i++)
|
|
|
- {
|
|
|
- if (i >= TOUT_LOOP)
|
|
|
- {
|
|
|
- PRINTF("TX Ring status (send): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status));
|
|
|
+ for (i = 0; !(ETH_STATUS (dev) & DownComplete); i++) {
|
|
|
+ if (i >= TOUT_LOOP) {
|
|
|
+ PRINTF ("TX Ring status (send): 0x%4x\n",
|
|
|
+ le32_to_cpu (tx_ring[tx_cur].status));
|
|
|
goto Done;
|
|
|
}
|
|
|
}
|
|
|
- if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */
|
|
|
- {
|
|
|
- ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */
|
|
|
- issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */
|
|
|
- ETH_OUTL(dev, 0, DownListPtr);
|
|
|
- issue_and_wait(dev, DownUnstall);
|
|
|
+ if (ETH_STATUS (dev) & DownComplete) { /* If DownLoad Complete ACK the bit */
|
|
|
+ ETH_CMD (dev, AckIntr | DownComplete); /* acknowledge the indication bit */
|
|
|
+ issue_and_wait (dev, DownStall); /* stall and clear DownListPtr */
|
|
|
+ ETH_OUTL (dev, 0, DownListPtr);
|
|
|
+ issue_and_wait (dev, DownUnstall);
|
|
|
}
|
|
|
- status=1;
|
|
|
- Done:
|
|
|
+ status = 1;
|
|
|
+Done:
|
|
|
return status;
|
|
|
}
|
|
|
|
|
|
-void PrintPacket (uchar *packet, int length)
|
|
|
+void PrintPacket (uchar * packet, int length)
|
|
|
{
|
|
|
-int loop;
|
|
|
-uchar *ptr;
|
|
|
+ int loop;
|
|
|
+ uchar *ptr;
|
|
|
|
|
|
printf ("Printing packet of length %x.\n\n", length);
|
|
|
ptr = packet;
|
|
|
- for (loop = 1; loop <= length; loop++)
|
|
|
- {
|
|
|
+ for (loop = 1; loop <= length; loop++) {
|
|
|
printf ("%2x ", *ptr++);
|
|
|
- if ((loop % 40)== 0)
|
|
|
+ if ((loop % 40) == 0)
|
|
|
printf ("\n");
|
|
|
}
|
|
|
}
|
|
|
|
|
|
-int eth_3com_recv(struct eth_device* dev)
|
|
|
+int eth_3com_recv (struct eth_device *dev)
|
|
|
{
|
|
|
u16 stat = 0;
|
|
|
u32 status;
|
|
|
int rx_prev, length = 0;
|
|
|
|
|
|
- while (!(ETH_STATUS(dev) & UpComplete)) /* wait on receipt of packet */
|
|
|
+ while (!(ETH_STATUS (dev) & UpComplete)) /* wait on receipt of packet */
|
|
|
;
|
|
|
|
|
|
- status = le32_to_cpu(rx_ring[rx_next].status); /* packet status */
|
|
|
+ status = le32_to_cpu (rx_ring[rx_next].status); /* packet status */
|
|
|
|
|
|
- while (status & (1<<15))
|
|
|
- {
|
|
|
+ while (status & (1 << 15)) {
|
|
|
/* A packet has been received */
|
|
|
|
|
|
- if (status & (1<<15))
|
|
|
- {
|
|
|
+ if (status & (1 << 15)) {
|
|
|
/* A valid frame received */
|
|
|
|
|
|
- length = le32_to_cpu(rx_ring[rx_next].status) & 0x1fff; /* length is in bits 0 - 12 */
|
|
|
+ length = le32_to_cpu (rx_ring[rx_next].status) & 0x1fff; /* length is in bits 0 - 12 */
|
|
|
|
|
|
/* Pass the packet up to the protocol layers */
|
|
|
|
|
|
- NetReceive((uchar *)le32_to_cpu(rx_ring[rx_next].addr), length);
|
|
|
- rx_ring[rx_next].status = 0; /* clear the status word */
|
|
|
- ETH_CMD(dev, AckIntr | UpComplete);
|
|
|
- issue_and_wait(dev, UpUnstall);
|
|
|
- }
|
|
|
- else
|
|
|
- if (stat & HostError)
|
|
|
- {
|
|
|
+ NetReceive ((uchar *)
|
|
|
+ le32_to_cpu (rx_ring[rx_next].addr),
|
|
|
+ length);
|
|
|
+ rx_ring[rx_next].status = 0; /* clear the status word */
|
|
|
+ ETH_CMD (dev, AckIntr | UpComplete);
|
|
|
+ issue_and_wait (dev, UpUnstall);
|
|
|
+ } else if (stat & HostError) {
|
|
|
/* There was an error */
|
|
|
|
|
|
- printf("Rx error status: 0x%4x\n", stat);
|
|
|
- init_rx_ring(dev);
|
|
|
+ printf ("Rx error status: 0x%4x\n", stat);
|
|
|
+ init_rx_ring (dev);
|
|
|
goto Done;
|
|
|
}
|
|
|
|
|
|
rx_prev = rx_next;
|
|
|
rx_next = (rx_next + 1) % NUM_RX_DESC;
|
|
|
- stat = ETH_STATUS(dev); /* register status */
|
|
|
- status = le32_to_cpu(rx_ring[rx_next].status); /* packet status */
|
|
|
+ stat = ETH_STATUS (dev); /* register status */
|
|
|
+ status = le32_to_cpu (rx_ring[rx_next].status); /* packet status */
|
|
|
}
|
|
|
-
|
|
|
Done:
|
|
|
return length;
|
|
|
}
|
|
|
|
|
|
-void eth_3com_halt(struct eth_device* dev)
|
|
|
+void eth_3com_halt (struct eth_device *dev)
|
|
|
{
|
|
|
- if (!(dev->iobase))
|
|
|
- {
|
|
|
+ if (!(dev->iobase)) {
|
|
|
goto Done;
|
|
|
}
|
|
|
|
|
|
- issue_and_wait(dev, DownStall); /* shut down transmit and receive */
|
|
|
- issue_and_wait(dev, UpStall);
|
|
|
- issue_and_wait(dev, RxDisable);
|
|
|
- issue_and_wait(dev, TxDisable);
|
|
|
+ issue_and_wait (dev, DownStall); /* shut down transmit and receive */
|
|
|
+ issue_and_wait (dev, UpStall);
|
|
|
+ issue_and_wait (dev, RxDisable);
|
|
|
+ issue_and_wait (dev, TxDisable);
|
|
|
|
|
|
/* free(tx_ring); /###* release memory allocated to the DPD and UPD rings */
|
|
|
/* free(rx_ring); */
|
|
@@ -764,41 +745,41 @@ Done:
|
|
|
return;
|
|
|
}
|
|
|
|
|
|
-static void init_rx_ring(struct eth_device* dev)
|
|
|
+static void init_rx_ring (struct eth_device *dev)
|
|
|
{
|
|
|
int i;
|
|
|
|
|
|
- PRINTF("Initializing rx_ring. rx_buffer = %p\n", rx_buffer);
|
|
|
- issue_and_wait(dev, UpStall);
|
|
|
+ PRINTF ("Initializing rx_ring. rx_buffer = %p\n", rx_buffer);
|
|
|
+ issue_and_wait (dev, UpStall);
|
|
|
|
|
|
- for (i = 0; i < NUM_RX_DESC; i++)
|
|
|
- {
|
|
|
- rx_ring[i].next = cpu_to_le32(((u32) &rx_ring[(i+1) % NUM_RX_DESC]));
|
|
|
- rx_ring[i].status = 0;
|
|
|
- rx_ring[i].addr = cpu_to_le32(((u32) &rx_buffer[i][0]));
|
|
|
- rx_ring[i].length = cpu_to_le32(PKTSIZE_ALIGN | LAST_FRAG);
|
|
|
+ for (i = 0; i < NUM_RX_DESC; i++) {
|
|
|
+ rx_ring[i].next =
|
|
|
+ cpu_to_le32 (((u32) &
|
|
|
+ rx_ring[(i + 1) % NUM_RX_DESC]));
|
|
|
+ rx_ring[i].status = 0;
|
|
|
+ rx_ring[i].addr = cpu_to_le32 (((u32) & rx_buffer[i][0]));
|
|
|
+ rx_ring[i].length = cpu_to_le32 (PKTSIZE_ALIGN | LAST_FRAG);
|
|
|
}
|
|
|
rx_next = 0;
|
|
|
}
|
|
|
|
|
|
-static void purge_tx_ring(struct eth_device* dev)
|
|
|
+static void purge_tx_ring (struct eth_device *dev)
|
|
|
{
|
|
|
int i;
|
|
|
|
|
|
- PRINTF("Purging tx_ring.\n");
|
|
|
+ PRINTF ("Purging tx_ring.\n");
|
|
|
|
|
|
- tx_next = 0;
|
|
|
+ tx_next = 0;
|
|
|
|
|
|
- for (i = 0; i < NUM_TX_DESC; i++)
|
|
|
- {
|
|
|
- tx_ring[i].next = 0;
|
|
|
- tx_ring[i].status = 0;
|
|
|
- tx_ring[i].addr = 0;
|
|
|
- tx_ring[i].length = 0;
|
|
|
+ for (i = 0; i < NUM_TX_DESC; i++) {
|
|
|
+ tx_ring[i].next = 0;
|
|
|
+ tx_ring[i].status = 0;
|
|
|
+ tx_ring[i].addr = 0;
|
|
|
+ tx_ring[i].length = 0;
|
|
|
}
|
|
|
}
|
|
|
|
|
|
-static void read_hw_addr(struct eth_device* dev, bd_t *bis)
|
|
|
+static void read_hw_addr (struct eth_device *dev, bd_t * bis)
|
|
|
{
|
|
|
u8 hw_addr[ETH_ALEN];
|
|
|
unsigned int eeprom[0x40];
|
|
@@ -807,77 +788,77 @@ static void read_hw_addr(struct eth_device* dev, bd_t *bis)
|
|
|
|
|
|
/* Read the station address from the EEPROM. */
|
|
|
|
|
|
- EL3WINDOW(dev, 0);
|
|
|
- for (i = 0; i < 0x40; i++)
|
|
|
- {
|
|
|
- ETH_OUTW(dev, EEPROM_Read + i, Wn0EepromCmd);
|
|
|
+ EL3WINDOW (dev, 0);
|
|
|
+ for (i = 0; i < 0x40; i++) {
|
|
|
+ ETH_OUTW (dev, EEPROM_Read + i, Wn0EepromCmd);
|
|
|
/* Pause for at least 162 us. for the read to take place. */
|
|
|
- for (timer = 10; timer >= 0; timer--)
|
|
|
- {
|
|
|
- udelay(162);
|
|
|
- if ((ETH_INW(dev, Wn0EepromCmd) & 0x8000) == 0)
|
|
|
+ for (timer = 10; timer >= 0; timer--) {
|
|
|
+ udelay (162);
|
|
|
+ if ((ETH_INW (dev, Wn0EepromCmd) & 0x8000) == 0)
|
|
|
break;
|
|
|
}
|
|
|
- eeprom[i] = ETH_INW(dev, Wn0EepromData);
|
|
|
+ eeprom[i] = ETH_INW (dev, Wn0EepromData);
|
|
|
}
|
|
|
|
|
|
/* Checksum calculation. I'm not sure about this part and there seems to be a bug on the 3com side of things */
|
|
|
|
|
|
for (i = 0; i < 0x21; i++)
|
|
|
- checksum ^= eeprom[i];
|
|
|
+ checksum ^= eeprom[i];
|
|
|
checksum = (checksum ^ (checksum >> 8)) & 0xff;
|
|
|
|
|
|
if (checksum != 0xbb)
|
|
|
- printf(" *** INVALID EEPROM CHECKSUM %4.4x *** \n", checksum);
|
|
|
+ printf (" *** INVALID EEPROM CHECKSUM %4.4x *** \n",
|
|
|
+ checksum);
|
|
|
|
|
|
- for (i = 0, j = 0; i < 3; i++)
|
|
|
- {
|
|
|
- hw_addr[j++] = (u8)((eeprom[i+10] >> 8) & 0xff);
|
|
|
- hw_addr[j++] = (u8)(eeprom[i+10] & 0xff);
|
|
|
+ for (i = 0, j = 0; i < 3; i++) {
|
|
|
+ hw_addr[j++] = (u8) ((eeprom[i + 10] >> 8) & 0xff);
|
|
|
+ hw_addr[j++] = (u8) (eeprom[i + 10] & 0xff);
|
|
|
}
|
|
|
|
|
|
/* MAC Address is in window 2, write value from EEPROM to window 2 */
|
|
|
|
|
|
- EL3WINDOW(dev, 2);
|
|
|
+ EL3WINDOW (dev, 2);
|
|
|
for (i = 0; i < 6; i++)
|
|
|
- ETH_OUTB(dev, hw_addr[i], i);
|
|
|
+ ETH_OUTB (dev, hw_addr[i], i);
|
|
|
|
|
|
- for (j = 0; j < ETH_ALEN; j+=2)
|
|
|
- {
|
|
|
- hw_addr[j] = (u8)(ETH_INW(dev, j) & 0xff);
|
|
|
- hw_addr[j+1] = (u8)((ETH_INW(dev, j) >> 8) & 0xff);
|
|
|
+ for (j = 0; j < ETH_ALEN; j += 2) {
|
|
|
+ hw_addr[j] = (u8) (ETH_INW (dev, j) & 0xff);
|
|
|
+ hw_addr[j + 1] = (u8) ((ETH_INW (dev, j) >> 8) & 0xff);
|
|
|
}
|
|
|
|
|
|
- for (i=0;i<ETH_ALEN;i++)
|
|
|
- {
|
|
|
- if (hw_addr[i] != bis->bi_enetaddr[i])
|
|
|
- {
|
|
|
-/* printf("Warning: HW address don't match:\n"); */
|
|
|
-/* printf("Address in 3Com Window 2 is " */
|
|
|
-/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */
|
|
|
-/* hw_addr[0], hw_addr[1], hw_addr[2], */
|
|
|
-/* hw_addr[3], hw_addr[4], hw_addr[5]); */
|
|
|
-/* printf("Address used by U-Boot is " */
|
|
|
-/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */
|
|
|
-/* bis->bi_enetaddr[0], bis->bi_enetaddr[1], */
|
|
|
-/* bis->bi_enetaddr[2], bis->bi_enetaddr[3], */
|
|
|
-/* bis->bi_enetaddr[4], bis->bi_enetaddr[5]); */
|
|
|
-/* goto Done; */
|
|
|
- char buffer[256];
|
|
|
- if (bis->bi_enetaddr[0] == 0 && bis->bi_enetaddr[1] == 0 &&
|
|
|
- bis->bi_enetaddr[2] == 0 && bis->bi_enetaddr[3] == 0 &&
|
|
|
- bis->bi_enetaddr[4] == 0 && bis->bi_enetaddr[5] == 0)
|
|
|
- {
|
|
|
-
|
|
|
- sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X",
|
|
|
- hw_addr[0], hw_addr[1], hw_addr[2],
|
|
|
- hw_addr[3], hw_addr[4], hw_addr[5]);
|
|
|
- setenv("ethaddr", buffer);
|
|
|
- }
|
|
|
+ for (i = 0; i < ETH_ALEN; i++) {
|
|
|
+ if (hw_addr[i] != bis->bi_enetaddr[i]) {
|
|
|
+/* printf("Warning: HW address don't match:\n"); */
|
|
|
+/* printf("Address in 3Com Window 2 is " */
|
|
|
+/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */
|
|
|
+/* hw_addr[0], hw_addr[1], hw_addr[2], */
|
|
|
+/* hw_addr[3], hw_addr[4], hw_addr[5]); */
|
|
|
+/* printf("Address used by U-Boot is " */
|
|
|
+/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */
|
|
|
+/* bis->bi_enetaddr[0], bis->bi_enetaddr[1], */
|
|
|
+/* bis->bi_enetaddr[2], bis->bi_enetaddr[3], */
|
|
|
+/* bis->bi_enetaddr[4], bis->bi_enetaddr[5]); */
|
|
|
+/* goto Done; */
|
|
|
+ char buffer[256];
|
|
|
+
|
|
|
+ if (bis->bi_enetaddr[0] == 0
|
|
|
+ && bis->bi_enetaddr[1] == 0
|
|
|
+ && bis->bi_enetaddr[2] == 0
|
|
|
+ && bis->bi_enetaddr[3] == 0
|
|
|
+ && bis->bi_enetaddr[4] == 0
|
|
|
+ && bis->bi_enetaddr[5] == 0) {
|
|
|
+
|
|
|
+ sprintf (buffer,
|
|
|
+ "%02X:%02X:%02X:%02X:%02X:%02X",
|
|
|
+ hw_addr[0], hw_addr[1], hw_addr[2],
|
|
|
+ hw_addr[3], hw_addr[4], hw_addr[5]);
|
|
|
+ setenv ("ethaddr", buffer);
|
|
|
+ }
|
|
|
}
|
|
|
}
|
|
|
|
|
|
- for(i=0; i<ETH_ALEN; i++) dev->enetaddr[i] = hw_addr[i];
|
|
|
+ for (i = 0; i < ETH_ALEN; i++)
|
|
|
+ dev->enetaddr[i] = hw_addr[i];
|
|
|
|
|
|
Done:
|
|
|
return;
|