makalu.c 14 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <ppc4xx.h>
  25. #include <ppc405.h>
  26. #include <libfdt.h>
  27. #include <asm/processor.h>
  28. #include <asm/gpio.h>
  29. #include <asm/io.h>
  30. #include <fdt_support.h>
  31. #if defined(CONFIG_PCI)
  32. #include <pci.h>
  33. #include <asm/4xx_pcie.h>
  34. #endif
  35. DECLARE_GLOBAL_DATA_PTR;
  36. extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  37. /*
  38. * Board early initialization function
  39. */
  40. int board_early_init_f (void)
  41. {
  42. u32 val;
  43. /*--------------------------------------------------------------------+
  44. | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
  45. +--------------------------------------------------------------------+
  46. +---------------------------------------------------------------------+
  47. |Interrupt| Source | Pol. | Sensi.| Crit. |
  48. +---------+-----------------------------------+-------+-------+-------+
  49. | IRQ 00 | UART0 | High | Level | Non |
  50. | IRQ 01 | UART1 | High | Level | Non |
  51. | IRQ 02 | IIC0 | High | Level | Non |
  52. | IRQ 03 | TBD | High | Level | Non |
  53. | IRQ 04 | TBD | High | Level | Non |
  54. | IRQ 05 | EBM | High | Level | Non |
  55. | IRQ 06 | BGI | High | Level | Non |
  56. | IRQ 07 | IIC1 | Rising| Edge | Non |
  57. | IRQ 08 | SPI | High | Lvl/ed| Non |
  58. | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
  59. | IRQ 10 | MAL TX EOB | High | Level | Non |
  60. | IRQ 11 | MAL RX EOB | High | Level | Non |
  61. | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
  62. | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
  63. | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
  64. | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
  65. | IRQ 16 | PCIE0 AL | high | Level | Non |
  66. | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
  67. | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
  68. | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
  69. | IRQ 20 | PCIE0 TCR | High | Level | Non |
  70. | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
  71. | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
  72. | IRQ 23 | Security EIP-94 | High | Level | Non |
  73. | IRQ 24 | EMAC0 interrupt | High | Level | Non |
  74. | IRQ 25 | EMAC1 interrupt | High | Level | Non |
  75. | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
  76. | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
  77. | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
  78. | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
  79. | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
  80. | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
  81. |----------------------------------------------------------------------
  82. | IRQ 32 | MAL Serr | High | Level | Non |
  83. | IRQ 33 | MAL Txde | High | Level | Non |
  84. | IRQ 34 | MAL Rxde | High | Level | Non |
  85. | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
  86. | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
  87. | IRQ 37 | EBC | High |Lvl Edg| Non |
  88. | IRQ 38 | NDFC | High | Level | Non |
  89. | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
  90. | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
  91. | IRQ 41 | PCIE1 AL | high | Level | Non |
  92. | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
  93. | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
  94. | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
  95. | IRQ 45 | PCIE1 TCR | High | Level | Non |
  96. | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
  97. | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
  98. | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
  99. | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
  100. | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
  101. | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
  102. | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
  103. | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
  104. | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
  105. | IRQ 55 | Serial ROM | High | Level | Non |
  106. | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
  107. | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
  108. | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
  109. | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
  110. | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
  111. | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
  112. | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
  113. |----------------------------------------------------------------------
  114. | IRQ 64 | PE0 AL | High | Level | Non |
  115. | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
  116. | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
  117. | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
  118. | IRQ 68 | PE0 TCR | High | Level | Non |
  119. | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
  120. | IRQ 70 | PE0 DCR Error | High | Level | Non |
  121. | IRQ 71 | Reserved | N/A | N/A | Non |
  122. | IRQ 72 | PE1 AL | High | Level | Non |
  123. | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
  124. | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
  125. | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
  126. | IRQ 76 | PE1 TCR | High | Level | Non |
  127. | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
  128. | IRQ 78 | PE1 DCR Error | High | Level | Non |
  129. | IRQ 79 | Reserved | N/A | N/A | Non |
  130. | IRQ 80 | PE2 AL | High | Level | Non |
  131. | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
  132. | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
  133. | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
  134. | IRQ 84 | PE2 TCR | High | Level | Non |
  135. | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
  136. | IRQ 86 | PE2 DCR Error | High | Level | Non |
  137. | IRQ 87 | Reserved | N/A | N/A | Non |
  138. | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
  139. | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
  140. | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
  141. | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
  142. | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
  143. | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
  144. | IRQ 94 | Reserved | N/A | N/A | Non |
  145. | IRQ 95 | Reserved | N/A | N/A | Non |
  146. |---------------------------------------------------------------------
  147. +---------+-----------------------------------+-------+-------+------*/
  148. /*--------------------------------------------------------------------+
  149. | Initialise UIC registers. Clear all interrupts. Disable all
  150. | interrupts.
  151. | Set critical interrupt values. Set interrupt polarities. Set
  152. | interrupt trigger levels. Make bit 0 High priority. Clear all
  153. | interrupts again.
  154. +-------------------------------------------------------------------*/
  155. mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
  156. mtdcr (uic2er, 0x00000000); /* disable all interrupts */
  157. mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
  158. mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
  159. mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
  160. mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
  161. mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
  162. mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
  163. mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
  164. mtdcr (uic1er, 0x00000000); /* disable all interrupts */
  165. mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
  166. mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
  167. mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
  168. mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
  169. mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
  170. mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
  171. mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
  172. mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
  173. /* Except cascade UIC0 and UIC1 */
  174. mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
  175. mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
  176. mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
  177. mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
  178. mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
  179. mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
  180. /*
  181. * Note: Some cores are still in reset when the chip starts, so
  182. * take them out of reset
  183. */
  184. mtsdr(SDR0_SRST, 0);
  185. /* Reset PCIe slots */
  186. gpio_write_bit(CFG_GPIO_PCIE_RST, 0);
  187. udelay(100);
  188. gpio_write_bit(CFG_GPIO_PCIE_RST, 1);
  189. /*
  190. * Configure PFC (Pin Function Control) registers
  191. * -> Enable USB
  192. */
  193. val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
  194. mtsdr(SDR0_PFC1, val);
  195. return 0;
  196. }
  197. int misc_init_r(void)
  198. {
  199. #ifdef CFG_ENV_IS_IN_FLASH
  200. /* Monitor protection ON by default */
  201. flash_protect(FLAG_PROTECT_SET,
  202. -CFG_MONITOR_LEN,
  203. 0xffffffff,
  204. &flash_info[0]);
  205. #endif
  206. return 0;
  207. }
  208. int checkboard (void)
  209. {
  210. char *s = getenv("serial#");
  211. printf("Board: Makalu - AMCC PPC405EX Evaluation Board");
  212. if (s != NULL) {
  213. puts(", serial# ");
  214. puts(s);
  215. }
  216. putc('\n');
  217. return (0);
  218. }
  219. /*************************************************************************
  220. * pci_pre_init
  221. *
  222. * This routine is called just prior to registering the hose and gives
  223. * the board the opportunity to check things. Returning a value of zero
  224. * indicates that things are bad & PCI initialization should be aborted.
  225. *
  226. * Different boards may wish to customize the pci controller structure
  227. * (add regions, override default access routines, etc) or perform
  228. * certain pre-initialization actions.
  229. *
  230. ************************************************************************/
  231. #if defined(CONFIG_PCI)
  232. int pci_pre_init(struct pci_controller * hose )
  233. {
  234. return 0;
  235. }
  236. #endif /* defined(CONFIG_PCI) */
  237. #ifdef CONFIG_PCI
  238. static struct pci_controller pcie_hose[2] = {{0},{0}};
  239. void pcie_setup_hoses(int busno)
  240. {
  241. struct pci_controller *hose;
  242. int i, bus;
  243. int ret = 0;
  244. bus = busno;
  245. char *env;
  246. unsigned int delay;
  247. for (i = 0; i < 2; i++) {
  248. if (is_end_point(i))
  249. ret = ppc4xx_init_pcie_endport(i);
  250. else
  251. ret = ppc4xx_init_pcie_rootport(i);
  252. if (ret) {
  253. printf("PCIE%d: initialization as %s failed\n", i,
  254. is_end_point(i) ? "endpoint" : "root-complex");
  255. continue;
  256. }
  257. hose = &pcie_hose[i];
  258. hose->first_busno = bus;
  259. hose->last_busno = bus;
  260. hose->current_busno = bus;
  261. /* setup mem resource */
  262. pci_set_region(hose->regions + 0,
  263. CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
  264. CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
  265. CFG_PCIE_MEMSIZE,
  266. PCI_REGION_MEM);
  267. hose->region_count = 1;
  268. pci_register_hose(hose);
  269. if (is_end_point(i)) {
  270. ppc4xx_setup_pcie_endpoint(hose, i);
  271. /*
  272. * Reson for no scanning is endpoint can not generate
  273. * upstream configuration accesses.
  274. */
  275. } else {
  276. ppc4xx_setup_pcie_rootpoint(hose, i);
  277. env = getenv ("pciscandelay");
  278. if (env != NULL) {
  279. delay = simple_strtoul(env, NULL, 10);
  280. if (delay > 5)
  281. printf("Warning, expect noticable delay before "
  282. "PCIe scan due to 'pciscandelay' value!\n");
  283. mdelay(delay * 1000);
  284. }
  285. /*
  286. * Config access can only go down stream
  287. */
  288. hose->last_busno = pci_hose_scan(hose);
  289. bus = hose->last_busno + 1;
  290. }
  291. }
  292. }
  293. #endif
  294. #if defined(CONFIG_POST)
  295. /*
  296. * Returns 1 if keys pressed to start the power-on long-running tests
  297. * Called from board_init_f().
  298. */
  299. int post_hotkeys_pressed(void)
  300. {
  301. return 0; /* No hotkeys supported */
  302. }
  303. #endif /* CONFIG_POST */
  304. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  305. void ft_board_setup(void *blob, bd_t *bd)
  306. {
  307. u32 val[4];
  308. int rc;
  309. ft_cpu_setup(blob, bd);
  310. /* Fixup NOR mapping */
  311. val[0] = 0; /* chip select number */
  312. val[1] = 0; /* always 0 */
  313. val[2] = gd->bd->bi_flashstart;
  314. val[3] = gd->bd->bi_flashsize;
  315. rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
  316. val, sizeof(val), 1);
  317. if (rc)
  318. printf("Unable to update property NOR mapping, err=%s\n",
  319. fdt_strerror(rc));
  320. }
  321. #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */