katmai.c 23 KB

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  1. /*
  2. * (C) Copyright 2007-2008
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. */
  24. #include <common.h>
  25. #include <ppc4xx.h>
  26. #include <i2c.h>
  27. #include <libfdt.h>
  28. #include <fdt_support.h>
  29. #include <asm/processor.h>
  30. #include <asm/io.h>
  31. #include <asm/gpio.h>
  32. #include <asm/4xx_pcie.h>
  33. DECLARE_GLOBAL_DATA_PTR;
  34. int board_early_init_f (void)
  35. {
  36. unsigned long mfr;
  37. /*----------------------------------------------------------------------+
  38. * Interrupt controller setup for the Katmai 440SPe Evaluation board.
  39. *-----------------------------------------------------------------------+
  40. *-----------------------------------------------------------------------+
  41. * Interrupt | Source | Pol. | Sensi.| Crit. |
  42. *-----------+-----------------------------------+-------+-------+-------+
  43. * IRQ 00 | UART0 | High | Level | Non |
  44. * IRQ 01 | UART1 | High | Level | Non |
  45. * IRQ 02 | IIC0 | High | Level | Non |
  46. * IRQ 03 | IIC1 | High | Level | Non |
  47. * IRQ 04 | PCI0X0 MSG IN | High | Level | Non |
  48. * IRQ 05 | PCI0X0 CMD Write | High | Level | Non |
  49. * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non |
  50. * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non |
  51. * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non |
  52. * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |
  53. * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |
  54. * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |
  55. * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non |
  56. * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non |
  57. * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non |
  58. * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non |
  59. * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |
  60. * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |
  61. * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |
  62. * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non |
  63. * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non |
  64. * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non |
  65. * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non |
  66. * IRQ 23 | I2O Inbound Doorbell | High | Level | Non |
  67. * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non |
  68. * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non |
  69. * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non |
  70. * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non |
  71. * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non |
  72. * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non |
  73. * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |
  74. * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |
  75. *------------------------------------------------------------------------
  76. * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non |
  77. * IRQ 33 | MAL Serr | High | Level | Non |
  78. * IRQ 34 | MAL Txde | High | Level | Non |
  79. * IRQ 35 | MAL Rxde | High | Level | Non |
  80. * IRQ 36 | DMC CE or DMC UE | High | Level | Non |
  81. * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non |
  82. * IRQ 38 | MAL TX EOB | High | Level | Non |
  83. * IRQ 39 | MAL RX EOB | High | Level | Non |
  84. * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non |
  85. * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non |
  86. * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non |
  87. * IRQ 43 | L2 Cache | Risin | Edge | Non |
  88. * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non |
  89. * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non |
  90. * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non |
  91. * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
  92. * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
  93. * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non |
  94. * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non |
  95. * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non |
  96. * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
  97. * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non |
  98. * IRQ 54 | DMA Error | High | Level | Non |
  99. * IRQ 55 | DMA I2O Error | High | Level | Non |
  100. * IRQ 56 | Serial ROM | High | Level | Non |
  101. * IRQ 57 | PCIX0 Error | High | Edge | Non |
  102. * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non |
  103. * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non |
  104. * IRQ 60 | EMAC0 Interrupt | High | Level | Non |
  105. * IRQ 61 | EMAC0 Wake-up | High | Level | Non |
  106. * IRQ 62 | Reserved | High | Level | Non |
  107. * IRQ 63 | XOR | High | Level | Non |
  108. *-----------------------------------------------------------------------
  109. * IRQ 64 | PE0 AL | High | Level | Non |
  110. * IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
  111. * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
  112. * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
  113. * IRQ 68 | PE0 TCR | High | Level | Non |
  114. * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
  115. * IRQ 70 | PE0 DCR Error | High | Level | Non |
  116. * IRQ 71 | Reserved | N/A | N/A | Non |
  117. * IRQ 72 | PE1 AL | High | Level | Non |
  118. * IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
  119. * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
  120. * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
  121. * IRQ 76 | PE1 TCR | High | Level | Non |
  122. * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
  123. * IRQ 78 | PE1 DCR Error | High | Level | Non |
  124. * IRQ 79 | Reserved | N/A | N/A | Non |
  125. * IRQ 80 | PE2 AL | High | Level | Non |
  126. * IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
  127. * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
  128. * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
  129. * IRQ 84 | PE2 TCR | High | Level | Non |
  130. * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
  131. * IRQ 86 | PE2 DCR Error | High | Level | Non |
  132. * IRQ 87 | Reserved | N/A | N/A | Non |
  133. * IRQ 88 | External IRQ(5) | Progr | Progr | Non |
  134. * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
  135. * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
  136. * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
  137. * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
  138. * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
  139. * IRQ 94 | Reserved | N/A | N/A | Non |
  140. * IRQ 95 | Reserved | N/A | N/A | Non |
  141. *-----------------------------------------------------------------------
  142. * IRQ 96 | PE0 INTA | High | Level | Non |
  143. * IRQ 97 | PE0 INTB | High | Level | Non |
  144. * IRQ 98 | PE0 INTC | High | Level | Non |
  145. * IRQ 99 | PE0 INTD | High | Level | Non |
  146. * IRQ 100 | PE1 INTA | High | Level | Non |
  147. * IRQ 101 | PE1 INTB | High | Level | Non |
  148. * IRQ 102 | PE1 INTC | High | Level | Non |
  149. * IRQ 103 | PE1 INTD | High | Level | Non |
  150. * IRQ 104 | PE2 INTA | High | Level | Non |
  151. * IRQ 105 | PE2 INTB | High | Level | Non |
  152. * IRQ 106 | PE2 INTC | High | Level | Non |
  153. * IRQ 107 | PE2 INTD | Risin | Edge | Non |
  154. * IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non |
  155. * IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non |
  156. * IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non |
  157. * IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non |
  158. * IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non |
  159. * IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non |
  160. * IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non |
  161. * IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non |
  162. * IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non |
  163. * IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non |
  164. * IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non |
  165. * IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non |
  166. * IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non |
  167. * IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non |
  168. * IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non |
  169. * IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non |
  170. * IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non |
  171. * IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non |
  172. * IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non |
  173. * IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non |
  174. *-----------+-----------------------------------+-------+-------+-------+ */
  175. /*-------------------------------------------------------------------------+
  176. * Put UICs in PowerPC440SPemode.
  177. * Initialise UIC registers. Clear all interrupts. Disable all interrupts.
  178. * Set critical interrupt values. Set interrupt polarities. Set interrupt
  179. * trigger levels. Make bit 0 High priority. Clear all interrupts again.
  180. *------------------------------------------------------------------------*/
  181. mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
  182. mtdcr (uic3er, 0x00000000); /* disable all interrupts */
  183. mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical interrupts: */
  184. mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities*/
  185. mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
  186. mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
  187. mtdcr (uic3sr, 0x00000000); /* clear all interrupts*/
  188. mtdcr (uic3sr, 0xffffffff); /* clear all interrupts*/
  189. mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
  190. mtdcr (uic2er, 0x00000000); /* disable all interrupts*/
  191. mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
  192. mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities*/
  193. mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
  194. mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
  195. mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
  196. mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
  197. mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts*/
  198. mtdcr (uic1er, 0x00000000); /* disable all interrupts*/
  199. mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
  200. mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
  201. mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels*/
  202. mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
  203. mtdcr (uic1sr, 0x00000000); /* clear all interrupts*/
  204. mtdcr (uic1sr, 0xffffffff); /* clear all interrupts*/
  205. mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
  206. mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted cascade to be checked */
  207. mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical interrupts*/
  208. mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities*/
  209. mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
  210. mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
  211. mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/
  212. mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/
  213. mfsdr(sdr_mfr, mfr);
  214. mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
  215. mtsdr(sdr_mfr, mfr);
  216. mtsdr(SDR0_PFC0, CFG_PFC0);
  217. out32(GPIO0_OR, CFG_GPIO_OR);
  218. out32(GPIO0_ODR, CFG_GPIO_ODR);
  219. out32(GPIO0_TCR, CFG_GPIO_TCR);
  220. return 0;
  221. }
  222. int checkboard (void)
  223. {
  224. char *s = getenv("serial#");
  225. printf("Board: Katmai - AMCC 440SPe Evaluation Board");
  226. if (s != NULL) {
  227. puts(", serial# ");
  228. puts(s);
  229. }
  230. putc('\n');
  231. return 0;
  232. }
  233. /*
  234. * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
  235. * board specific values.
  236. */
  237. u32 ddr_wrdtr(u32 default_val) {
  238. return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
  239. }
  240. u32 ddr_clktr(u32 default_val) {
  241. return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
  242. }
  243. #if defined(CFG_DRAM_TEST)
  244. int testdram (void)
  245. {
  246. uint *pstart = (uint *) 0x00000000;
  247. uint *pend = (uint *) 0x08000000;
  248. uint *p;
  249. for (p = pstart; p < pend; p++)
  250. *p = 0xaaaaaaaa;
  251. for (p = pstart; p < pend; p++) {
  252. if (*p != 0xaaaaaaaa) {
  253. printf ("SDRAM test fails at: %08x\n", (uint) p);
  254. return 1;
  255. }
  256. }
  257. for (p = pstart; p < pend; p++)
  258. *p = 0x55555555;
  259. for (p = pstart; p < pend; p++) {
  260. if (*p != 0x55555555) {
  261. printf ("SDRAM test fails at: %08x\n", (uint) p);
  262. return 1;
  263. }
  264. }
  265. return 0;
  266. }
  267. #endif
  268. /*************************************************************************
  269. * pci_pre_init
  270. *
  271. * This routine is called just prior to registering the hose and gives
  272. * the board the opportunity to check things. Returning a value of zero
  273. * indicates that things are bad & PCI initialization should be aborted.
  274. *
  275. * Different boards may wish to customize the pci controller structure
  276. * (add regions, override default access routines, etc) or perform
  277. * certain pre-initialization actions.
  278. *
  279. ************************************************************************/
  280. #if defined(CONFIG_PCI)
  281. int pci_pre_init(struct pci_controller * hose )
  282. {
  283. unsigned long strap;
  284. /*-------------------------------------------------------------------+
  285. * The katmai board is always configured as the host & requires the
  286. * PCI arbiter to be enabled.
  287. *-------------------------------------------------------------------*/
  288. mfsdr(sdr_sdstp1, strap);
  289. if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
  290. printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
  291. return 0;
  292. }
  293. return 1;
  294. }
  295. #endif /* defined(CONFIG_PCI) */
  296. /*************************************************************************
  297. * pci_target_init
  298. *
  299. * The bootstrap configuration provides default settings for the pci
  300. * inbound map (PIM). But the bootstrap config choices are limited and
  301. * may not be sufficient for a given board.
  302. *
  303. ************************************************************************/
  304. #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
  305. void pci_target_init(struct pci_controller * hose )
  306. {
  307. /*-------------------------------------------------------------------+
  308. * Disable everything
  309. *-------------------------------------------------------------------*/
  310. out32r( PCIX0_PIM0SA, 0 ); /* disable */
  311. out32r( PCIX0_PIM1SA, 0 ); /* disable */
  312. out32r( PCIX0_PIM2SA, 0 ); /* disable */
  313. out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
  314. /*-------------------------------------------------------------------+
  315. * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
  316. * strapping options to not support sizes such as 128/256 MB.
  317. *-------------------------------------------------------------------*/
  318. out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
  319. out32r( PCIX0_PIM0LAH, 0 );
  320. out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
  321. out32r( PCIX0_BAR0, 0 );
  322. /*-------------------------------------------------------------------+
  323. * Program the board's subsystem id/vendor id
  324. *-------------------------------------------------------------------*/
  325. out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
  326. out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
  327. out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
  328. }
  329. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
  330. #if defined(CONFIG_PCI)
  331. /*************************************************************************
  332. * is_pci_host
  333. *
  334. * This routine is called to determine if a pci scan should be
  335. * performed. With various hardware environments (especially cPCI and
  336. * PPMC) it's insufficient to depend on the state of the arbiter enable
  337. * bit in the strap register, or generic host/adapter assumptions.
  338. *
  339. * Rather than hard-code a bad assumption in the general 440 code, the
  340. * 440 pci code requires the board to decide at runtime.
  341. *
  342. * Return 0 for adapter mode, non-zero for host (monarch) mode.
  343. *
  344. *
  345. ************************************************************************/
  346. int is_pci_host(struct pci_controller *hose)
  347. {
  348. /* The katmai board is always configured as host. */
  349. return 1;
  350. }
  351. int katmai_pcie_card_present(int port)
  352. {
  353. u32 val;
  354. val = in32(GPIO0_IR);
  355. switch (port) {
  356. case 0:
  357. return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT0));
  358. case 1:
  359. return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT1));
  360. case 2:
  361. return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT2));
  362. default:
  363. return 0;
  364. }
  365. }
  366. static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
  367. void pcie_setup_hoses(int busno)
  368. {
  369. struct pci_controller *hose;
  370. int i, bus;
  371. int ret = 0;
  372. char *env;
  373. unsigned int delay;
  374. /*
  375. * assume we're called after the PCIX hose is initialized, which takes
  376. * bus ID 0 and therefore start numbering PCIe's from 1.
  377. */
  378. bus = busno;
  379. for (i = 0; i <= 2; i++) {
  380. /* Check for katmai card presence */
  381. if (!katmai_pcie_card_present(i))
  382. continue;
  383. if (is_end_point(i))
  384. ret = ppc4xx_init_pcie_endport(i);
  385. else
  386. ret = ppc4xx_init_pcie_rootport(i);
  387. if (ret) {
  388. printf("PCIE%d: initialization as %s failed\n", i,
  389. is_end_point(i) ? "endpoint" : "root-complex");
  390. continue;
  391. }
  392. hose = &pcie_hose[i];
  393. hose->first_busno = bus;
  394. hose->last_busno = bus;
  395. hose->current_busno = bus;
  396. /* setup mem resource */
  397. pci_set_region(hose->regions + 0,
  398. CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
  399. CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
  400. CFG_PCIE_MEMSIZE,
  401. PCI_REGION_MEM);
  402. hose->region_count = 1;
  403. pci_register_hose(hose);
  404. if (is_end_point(i)) {
  405. ppc4xx_setup_pcie_endpoint(hose, i);
  406. /*
  407. * Reson for no scanning is endpoint can not generate
  408. * upstream configuration accesses.
  409. */
  410. } else {
  411. ppc4xx_setup_pcie_rootpoint(hose, i);
  412. env = getenv ("pciscandelay");
  413. if (env != NULL) {
  414. delay = simple_strtoul(env, NULL, 10);
  415. if (delay > 5)
  416. printf("Warning, expect noticable delay before "
  417. "PCIe scan due to 'pciscandelay' value!\n");
  418. mdelay(delay * 1000);
  419. }
  420. /*
  421. * Config access can only go down stream
  422. */
  423. hose->last_busno = pci_hose_scan(hose);
  424. bus = hose->last_busno + 1;
  425. }
  426. }
  427. }
  428. #endif /* defined(CONFIG_PCI) */
  429. int misc_init_f (void)
  430. {
  431. uint reg;
  432. #if defined(CONFIG_STRESS)
  433. uint i ;
  434. uint disp;
  435. #endif
  436. /* minimal init for PCIe */
  437. #if 0 /* test-only: test endpoint at some time, for now rootpoint only */
  438. /* pci express 0 Endpoint Mode */
  439. mfsdr(SDR0_PE0DLPSET, reg);
  440. reg &= (~0x00400000);
  441. mtsdr(SDR0_PE0DLPSET, reg);
  442. #else
  443. /* pci express 0 Rootpoint Mode */
  444. mfsdr(SDR0_PE0DLPSET, reg);
  445. reg |= 0x00400000;
  446. mtsdr(SDR0_PE0DLPSET, reg);
  447. #endif
  448. /* pci express 1 Rootpoint Mode */
  449. mfsdr(SDR0_PE1DLPSET, reg);
  450. reg |= 0x00400000;
  451. mtsdr(SDR0_PE1DLPSET, reg);
  452. /* pci express 2 Rootpoint Mode */
  453. mfsdr(SDR0_PE2DLPSET, reg);
  454. reg |= 0x00400000;
  455. mtsdr(SDR0_PE2DLPSET, reg);
  456. #if defined(CONFIG_STRESS)
  457. /*
  458. * All this setting done by linux only needed by stress an charac. test
  459. * procedure
  460. * PCIe 1 Rootpoint PCIe2 Endpoint
  461. * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level
  462. */
  463. for (i=0,disp=0; i<8; i++,disp+=3) {
  464. mfsdr(SDR0_PE0HSSSET1L0+disp, reg);
  465. reg |= 0x33000000;
  466. mtsdr(SDR0_PE0HSSSET1L0+disp, reg);
  467. }
  468. /*PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
  469. for (i=0,disp=0; i<4; i++,disp+=3) {
  470. mfsdr(SDR0_PE1HSSSET1L0+disp, reg);
  471. reg |= 0x33000000;
  472. mtsdr(SDR0_PE1HSSSET1L0+disp, reg);
  473. }
  474. /*PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
  475. for (i=0,disp=0; i<4; i++,disp+=3) {
  476. mfsdr(SDR0_PE2HSSSET1L0+disp, reg);
  477. reg |= 0x33000000;
  478. mtsdr(SDR0_PE2HSSSET1L0+disp, reg);
  479. }
  480. reg = 0x21242222;
  481. mtsdr(SDR0_PE2UTLSET1, reg);
  482. reg = 0x11000000;
  483. mtsdr(SDR0_PE2UTLSET2, reg);
  484. /* pci express 1 Endpoint Mode */
  485. reg = 0x00004000;
  486. mtsdr(SDR0_PE2DLPSET, reg);
  487. mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
  488. #endif
  489. return 0;
  490. }
  491. #ifdef CONFIG_POST
  492. /*
  493. * Returns 1 if keys pressed to start the power-on long-running tests
  494. * Called from board_init_f().
  495. */
  496. int post_hotkeys_pressed(void)
  497. {
  498. return (ctrlc());
  499. }
  500. #endif
  501. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  502. void ft_board_setup(void *blob, bd_t *bd)
  503. {
  504. u32 val[4];
  505. int rc;
  506. ft_cpu_setup(blob, bd);
  507. /* Fixup NOR mapping */
  508. val[0] = 0; /* chip select number */
  509. val[1] = 0; /* always 0 */
  510. val[2] = gd->bd->bi_flashstart;
  511. val[3] = gd->bd->bi_flashsize;
  512. rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
  513. val, sizeof(val), 1);
  514. if (rc)
  515. printf("Unable to update property NOR mapping, err=%s\n",
  516. fdt_strerror(rc));
  517. }
  518. #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */