lowlevel_init.S 12 KB

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  1. /*
  2. * Most of this taken from Redboot hal_platform_setup.h with cleanup
  3. *
  4. * NOTE: I haven't clean this up considerably, just enough to get it
  5. * running. See hal_platform_setup.h for the source. See
  6. * board/cradle/lowlevel_init.S for another PXA250 setup that is
  7. * much cleaner.
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #include <config.h>
  28. #include <version.h>
  29. #include <asm/arch/pxa-regs.h>
  30. DRAM_SIZE: .long CFG_DRAM_SIZE
  31. /* wait for coprocessor write complete */
  32. .macro CPWAIT reg
  33. mrc p15,0,\reg,c2,c0,0
  34. mov \reg,\reg
  35. sub pc,pc,#4
  36. .endm
  37. /*
  38. * Memory setup
  39. */
  40. .globl lowlevel_init
  41. lowlevel_init:
  42. /* Set up GPIO pins first ----------------------------------------- */
  43. ldr r0, =GPSR0
  44. ldr r1, =CFG_GPSR0_VAL
  45. str r1, [r0]
  46. ldr r0, =GPSR1
  47. ldr r1, =CFG_GPSR1_VAL
  48. str r1, [r0]
  49. ldr r0, =GPSR2
  50. ldr r1, =CFG_GPSR2_VAL
  51. str r1, [r0]
  52. ldr r0, =GPCR0
  53. ldr r1, =CFG_GPCR0_VAL
  54. str r1, [r0]
  55. ldr r0, =GPCR1
  56. ldr r1, =CFG_GPCR1_VAL
  57. str r1, [r0]
  58. ldr r0, =GPCR2
  59. ldr r1, =CFG_GPCR2_VAL
  60. str r1, [r0]
  61. ldr r0, =GPDR0
  62. ldr r1, =CFG_GPDR0_VAL
  63. str r1, [r0]
  64. ldr r0, =GPDR1
  65. ldr r1, =CFG_GPDR1_VAL
  66. str r1, [r0]
  67. ldr r0, =GPDR2
  68. ldr r1, =CFG_GPDR2_VAL
  69. str r1, [r0]
  70. ldr r0, =GAFR0_L
  71. ldr r1, =CFG_GAFR0_L_VAL
  72. str r1, [r0]
  73. ldr r0, =GAFR0_U
  74. ldr r1, =CFG_GAFR0_U_VAL
  75. str r1, [r0]
  76. ldr r0, =GAFR1_L
  77. ldr r1, =CFG_GAFR1_L_VAL
  78. str r1, [r0]
  79. ldr r0, =GAFR1_U
  80. ldr r1, =CFG_GAFR1_U_VAL
  81. str r1, [r0]
  82. ldr r0, =GAFR2_L
  83. ldr r1, =CFG_GAFR2_L_VAL
  84. str r1, [r0]
  85. ldr r0, =GAFR2_U
  86. ldr r1, =CFG_GAFR2_U_VAL
  87. str r1, [r0]
  88. ldr r0, =PSSR /* enable GPIO pins */
  89. ldr r1, =CFG_PSSR_VAL
  90. str r1, [r0]
  91. /* ---------------------------------------------------------------- */
  92. /* Enable memory interface */
  93. /* */
  94. /* The sequence below is based on the recommended init steps */
  95. /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
  96. /* Chapter 10. */
  97. /* ---------------------------------------------------------------- */
  98. /* ---------------------------------------------------------------- */
  99. /* Step 1: Wait for at least 200 microsedonds to allow internal */
  100. /* clocks to settle. Only necessary after hard reset... */
  101. /* FIXME: can be optimized later */
  102. /* ---------------------------------------------------------------- */
  103. ldr r3, =OSCR /* reset the OS Timer Count to zero */
  104. mov r2, #0
  105. str r2, [r3]
  106. ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
  107. /* so 0x300 should be plenty */
  108. 1:
  109. ldr r2, [r3]
  110. cmp r4, r2
  111. bgt 1b
  112. mem_init:
  113. ldr r1, =MEMC_BASE /* get memory controller base addr. */
  114. /* ---------------------------------------------------------------- */
  115. /* Step 2a: Initialize Asynchronous static memory controller */
  116. /* ---------------------------------------------------------------- */
  117. /* MSC registers: timing, bus width, mem type */
  118. /* MSC0: nCS(0,1) */
  119. ldr r2, =CFG_MSC0_VAL
  120. str r2, [r1, #MSC0_OFFSET]
  121. ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
  122. /* that data latches */
  123. /* MSC1: nCS(2,3) */
  124. ldr r2, =CFG_MSC1_VAL
  125. str r2, [r1, #MSC1_OFFSET]
  126. ldr r2, [r1, #MSC1_OFFSET]
  127. /* MSC2: nCS(4,5) */
  128. ldr r2, =CFG_MSC2_VAL
  129. str r2, [r1, #MSC2_OFFSET]
  130. ldr r2, [r1, #MSC2_OFFSET]
  131. /* ---------------------------------------------------------------- */
  132. /* Step 2b: Initialize Card Interface */
  133. /* ---------------------------------------------------------------- */
  134. /* MECR: Memory Expansion Card Register */
  135. ldr r2, =CFG_MECR_VAL
  136. str r2, [r1, #MECR_OFFSET]
  137. ldr r2, [r1, #MECR_OFFSET]
  138. /* MCMEM0: Card Interface slot 0 timing */
  139. ldr r2, =CFG_MCMEM0_VAL
  140. str r2, [r1, #MCMEM0_OFFSET]
  141. ldr r2, [r1, #MCMEM0_OFFSET]
  142. /* MCMEM1: Card Interface slot 1 timing */
  143. ldr r2, =CFG_MCMEM1_VAL
  144. str r2, [r1, #MCMEM1_OFFSET]
  145. ldr r2, [r1, #MCMEM1_OFFSET]
  146. /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
  147. ldr r2, =CFG_MCATT0_VAL
  148. str r2, [r1, #MCATT0_OFFSET]
  149. ldr r2, [r1, #MCATT0_OFFSET]
  150. /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
  151. ldr r2, =CFG_MCATT1_VAL
  152. str r2, [r1, #MCATT1_OFFSET]
  153. ldr r2, [r1, #MCATT1_OFFSET]
  154. /* MCIO0: Card Interface I/O Space Timing, slot 0 */
  155. ldr r2, =CFG_MCIO0_VAL
  156. str r2, [r1, #MCIO0_OFFSET]
  157. ldr r2, [r1, #MCIO0_OFFSET]
  158. /* MCIO1: Card Interface I/O Space Timing, slot 1 */
  159. ldr r2, =CFG_MCIO1_VAL
  160. str r2, [r1, #MCIO1_OFFSET]
  161. ldr r2, [r1, #MCIO1_OFFSET]
  162. /* ---------------------------------------------------------------- */
  163. /* Step 2c: Write FLYCNFG FIXME: what's that??? */
  164. /* ---------------------------------------------------------------- */
  165. /* ---------------------------------------------------------------- */
  166. /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
  167. /* ---------------------------------------------------------------- */
  168. /* Before accessing MDREFR we need a valid DRI field, so we set */
  169. /* this to power on defaults + DRI field, set SDRAM clocks free running */
  170. ldr r3, =CFG_MDREFR_VAL
  171. ldr r2, =0xFFF
  172. and r3, r3, r2
  173. ldr r0, [r1, #MDREFR_OFFSET]
  174. bic r0, r0, r2
  175. bic r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
  176. orr r0, r0, r3
  177. str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
  178. /* ---------------------------------------------------------------- */
  179. /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
  180. /* ---------------------------------------------------------------- */
  181. /* Initialize SXCNFG register. Assert the enable bits */
  182. /* Write SXMRS to cause an MRS command to all enabled banks of */
  183. /* synchronous static memory. Note that SXLCR need not be written */
  184. /* at this time. */
  185. /* FIXME: we use async mode for now */
  186. /* ---------------------------------------------------------------- */
  187. /* Step 4: Initialize SDRAM */
  188. /* ---------------------------------------------------------------- */
  189. /* set MDREFR according to user define with exception of a few bits */
  190. ldr r4, =CFG_MDREFR_VAL
  191. ldr r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
  192. MDREFR_K2RUN |MDREFR_K2DB2)
  193. and r4, r4, r2
  194. bic r0, r0, r2
  195. orr r0, r0, r4
  196. str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
  197. ldr r0, [r1, #MDREFR_OFFSET]
  198. /* Step 4b: de-assert MDREFR:SLFRSH. */
  199. bic r0, r0, #(MDREFR_SLFRSH)
  200. str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
  201. ldr r0, [r1, #MDREFR_OFFSET]
  202. /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE */
  203. ldr r4, =CFG_MDREFR_VAL
  204. ldr r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
  205. MDREFR_K1FREE | MDREFR_K2FREE)
  206. and r4, r4, r2
  207. orr r0, r0, r4
  208. str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
  209. ldr r0, [r1, #MDREFR_OFFSET]
  210. /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
  211. /* configure but not enable each SDRAM partition pair. */
  212. ldr r4, =CFG_MDCNFG_VAL
  213. bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
  214. bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
  215. str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
  216. ldr r4, [r1, #MDCNFG_OFFSET]
  217. /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
  218. /* 100..200 µsec. */
  219. ldr r3, =OSCR /* reset the OS Timer Count to zero */
  220. mov r2, #0
  221. str r2, [r3]
  222. ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
  223. /* so 0x300 should be plenty */
  224. 1:
  225. ldr r2, [r3]
  226. cmp r4, r2
  227. bgt 1b
  228. /* Step 4f: Trigger a number (usually 8) refresh cycles by */
  229. /* attempting non-burst read or write accesses to disabled */
  230. /* SDRAM, as commonly specified in the power up sequence */
  231. /* documented in SDRAM data sheets. The address(es) used */
  232. /* for this purpose must not be cacheable. */
  233. ldr r3, =CFG_DRAM_BASE
  234. .rept 8
  235. str r2, [r3]
  236. .endr
  237. /* Step 4g: Write MDCNFG with enable bits asserted */
  238. /* (MDCNFG:DEx set to 1). */
  239. ldr r3, [r1, #MDCNFG_OFFSET]
  240. orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
  241. str r3, [r1, #MDCNFG_OFFSET]
  242. /* Step 4h: Write MDMRS. */
  243. ldr r2, =CFG_MDMRS_VAL
  244. str r2, [r1, #MDMRS_OFFSET]
  245. /* We are finished with Intel's memory controller initialisation */
  246. /* ---------------------------------------------------------------- */
  247. /* Disable (mask) all interrupts at interrupt controller */
  248. /* ---------------------------------------------------------------- */
  249. initirqs:
  250. mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
  251. ldr r2, =ICLR
  252. str r1, [r2]
  253. ldr r2, =ICMR /* mask all interrupts at the controller */
  254. str r1, [r2]
  255. /* ---------------------------------------------------------------- */
  256. /* Clock initialisation */
  257. /* ---------------------------------------------------------------- */
  258. initclks:
  259. /* Disable the peripheral clocks, and set the core clock frequency */
  260. /* Turn Off ALL on-chip peripheral clocks for re-configuration */
  261. /* Note: See label 'ENABLECLKS' for the re-enabling */
  262. ldr r1, =CKEN
  263. mov r2, #0
  264. str r2, [r1]
  265. /* default value in case no valid rotary switch setting is found */
  266. ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
  267. /* ... and write the core clock config register */
  268. ldr r1, =CCCR
  269. str r2, [r1]
  270. #ifdef RTC
  271. /* enable the 32Khz oscillator for RTC and PowerManager */
  272. ldr r1, =OSCC
  273. mov r2, #OSCC_OON
  274. str r2, [r1]
  275. /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
  276. /* has settled. */
  277. 60:
  278. ldr r2, [r1]
  279. ands r2, r2, #1
  280. beq 60b
  281. #endif
  282. /* ---------------------------------------------------------------- */
  283. /* */
  284. /* ---------------------------------------------------------------- */
  285. /* Save SDRAM size */
  286. ldr r1, =DRAM_SIZE
  287. str r8, [r1]
  288. /* Interrupt init: Mask all interrupts */
  289. ldr r0, =ICMR /* enable no sources */
  290. mov r1, #0
  291. str r1, [r0]
  292. /* FIXME */
  293. #define NODEBUG
  294. #ifdef NODEBUG
  295. /*Disable software and data breakpoints */
  296. mov r0,#0
  297. mcr p15,0,r0,c14,c8,0 /* ibcr0 */
  298. mcr p15,0,r0,c14,c9,0 /* ibcr1 */
  299. mcr p15,0,r0,c14,c4,0 /* dbcon */
  300. /*Enable all debug functionality */
  301. mov r0,#0x80000000
  302. mcr p14,0,r0,c10,c0,0 /* dcsr */
  303. #endif
  304. /* ---------------------------------------------------------------- */
  305. /* End lowlevel_init */
  306. /* ---------------------------------------------------------------- */
  307. endlowlevel_init:
  308. mov pc, lr