assabet.c 2.6 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4. * Marius Groeger <mgroeger@sysgo.de>
  5. *
  6. * 2004 (c) MontaVista Software, Inc.
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #include <common.h>
  27. #include <SA-1100.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. /* ------------------------------------------------------------------------- */
  30. /*
  31. * Board dependent initialisation
  32. */
  33. #define ECOR 0x8000
  34. #define ECOR_RESET 0x80
  35. #define ECOR_LEVEL_IRQ 0x40
  36. #define ECOR_WR_ATTRIB 0x04
  37. #define ECOR_ENABLE 0x01
  38. #define ECSR 0x8002
  39. #define ECSR_IOIS8 0x20
  40. #define ECSR_PWRDWN 0x04
  41. #define ECSR_INT 0x02
  42. #define SMC_IO_SHIFT 2
  43. #define NCR_0 (*((volatile u_char *)(0x100000a0)))
  44. #define NCR_ENET_OSC_EN (1<<3)
  45. static inline u8
  46. readb(volatile u8 * p)
  47. {
  48. return *p;
  49. }
  50. static inline void
  51. writeb(u8 v, volatile u8 * p)
  52. {
  53. *p = v;
  54. }
  55. static void
  56. smc_init(void)
  57. {
  58. u8 ecor;
  59. u8 ecsr;
  60. volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25));
  61. NCR_0 |= NCR_ENET_OSC_EN;
  62. udelay(100);
  63. ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
  64. writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
  65. udelay(100);
  66. /*
  67. * The device will ignore all writes to the enable bit while
  68. * reset is asserted, even if the reset bit is cleared in the
  69. * same write. Must clear reset first, then enable the device.
  70. */
  71. writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
  72. writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
  73. /*
  74. * Set the appropriate byte/word mode.
  75. */
  76. ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
  77. ecsr |= ECSR_IOIS8;
  78. writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
  79. udelay(100);
  80. }
  81. static void
  82. neponset_init(void)
  83. {
  84. smc_init();
  85. }
  86. int
  87. board_init(void)
  88. {
  89. gd->bd->bi_arch_number = MACH_TYPE_ASSABET;
  90. gd->bd->bi_boot_params = 0xc0000100;
  91. neponset_init();
  92. return 0;
  93. }
  94. int
  95. dram_init(void)
  96. {
  97. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  98. gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  99. return (0);
  100. }