bamboo.c 69 KB

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  1. /*
  2. * (C) Copyright 2005-2007
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <asm/processor.h>
  25. #include <asm/gpio.h>
  26. #include <spd_sdram.h>
  27. #include <ppc440.h>
  28. #include "bamboo.h"
  29. void ext_bus_cntlr_init(void);
  30. void configure_ppc440ep_pins(void);
  31. int is_nand_selected(void);
  32. #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
  33. /*************************************************************************
  34. *
  35. * Bamboo has one bank onboard sdram (plus DIMM)
  36. *
  37. * Fixed memory is composed of :
  38. * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
  39. * 13 row add bits, 10 column add bits (but 12 row used only).
  40. * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
  41. * 12 row add bits, 10 column add bits.
  42. * Prepare a subset (only the used ones) of SPD data
  43. *
  44. * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
  45. * the corresponding bank is divided by 2 due to number of Row addresses
  46. * 12 in the ECC module
  47. *
  48. * Assumes: 64 MB, ECC, non-registered
  49. * PLB @ 133 MHz
  50. *
  51. ************************************************************************/
  52. const unsigned char cfg_simulate_spd_eeprom[128] = {
  53. 0x80, /* number of SPD bytes used: 128 */
  54. 0x08, /* total number bytes in SPD device = 256 */
  55. 0x07, /* DDR ram */
  56. #ifdef CONFIG_DDR_ECC
  57. 0x0C, /* num Row Addr: 12 */
  58. #else
  59. 0x0D, /* num Row Addr: 13 */
  60. #endif
  61. 0x09, /* numColAddr: 9 */
  62. 0x01, /* numBanks: 1 */
  63. 0x20, /* Module data width: 32 bits */
  64. 0x00, /* Module data width continued: +0 */
  65. 0x04, /* 2.5 Volt */
  66. 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
  67. 0x00, /* SDRAM Access from clock */
  68. #ifdef CONFIG_DDR_ECC
  69. 0x02, /* ECC ON : 02 OFF : 00 */
  70. #else
  71. 0x00, /* ECC ON : 02 OFF : 00 */
  72. #endif
  73. 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */
  74. 0,
  75. 0,
  76. 0x01, /* wcsbc = 1 */
  77. 0,
  78. 0,
  79. 0x0C, /* casBit (2,2.5) */
  80. 0,
  81. 0,
  82. 0x00, /* not registered: 0 registered : 0x02*/
  83. 0,
  84. 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */
  85. 0,
  86. 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */
  87. 0,
  88. 0x50, /* tRpNs = 20 ns */
  89. 0,
  90. 0x50, /* tRcdNs = 20 ns */
  91. 45, /* tRasNs */
  92. #ifdef CONFIG_DDR_ECC
  93. 0x08, /* bankSizeID: 32MB */
  94. #else
  95. 0x10, /* bankSizeID: 64MB */
  96. #endif
  97. 0,
  98. 0,
  99. 0,
  100. 0,
  101. 0,
  102. 0,
  103. 0,
  104. 0,
  105. 0,
  106. 0,
  107. 0,
  108. 0,
  109. 0,
  110. 0,
  111. 0,
  112. 0,
  113. 0,
  114. 0,
  115. 0,
  116. 0,
  117. 0,
  118. 0,
  119. 0,
  120. 0,
  121. 0,
  122. 0,
  123. 0,
  124. 0,
  125. 0,
  126. 0,
  127. 0,
  128. 0,
  129. 0,
  130. 0,
  131. 0,
  132. 0,
  133. 0,
  134. 0,
  135. 0,
  136. 0,
  137. 0,
  138. 0,
  139. 0,
  140. 0,
  141. 0,
  142. 0,
  143. 0,
  144. 0,
  145. 0,
  146. 0,
  147. 0,
  148. 0,
  149. 0,
  150. 0,
  151. 0,
  152. 0,
  153. 0,
  154. 0,
  155. 0,
  156. 0,
  157. 0,
  158. 0,
  159. 0,
  160. 0,
  161. 0,
  162. 0,
  163. 0,
  164. 0,
  165. 0,
  166. 0,
  167. 0,
  168. 0,
  169. 0,
  170. 0,
  171. 0,
  172. 0,
  173. 0,
  174. 0,
  175. 0,
  176. 0,
  177. 0,
  178. 0,
  179. 0,
  180. 0,
  181. 0,
  182. 0,
  183. 0,
  184. 0,
  185. 0,
  186. 0,
  187. 0,
  188. 0,
  189. 0,
  190. 0,
  191. 0,
  192. 0
  193. };
  194. #endif
  195. #if 0
  196. { /* GPIO Alternate1 Alternate2 Alternate3 */
  197. {
  198. /* GPIO Core 0 */
  199. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
  200. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
  201. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
  202. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
  203. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
  204. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
  205. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
  206. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
  207. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
  208. { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
  209. { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
  210. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
  211. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
  212. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
  213. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
  214. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
  215. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
  216. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
  217. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
  218. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
  219. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
  220. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
  221. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
  222. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
  223. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
  224. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
  225. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
  226. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
  227. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
  228. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
  229. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
  230. { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
  231. },
  232. {
  233. /* GPIO Core 1 */
  234. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
  235. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
  236. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
  237. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
  238. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
  239. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
  240. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
  241. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
  242. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
  243. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
  244. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
  245. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
  246. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
  247. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
  248. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
  249. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
  250. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
  251. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
  252. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
  253. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
  254. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
  255. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
  256. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
  257. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
  258. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
  259. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
  260. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
  261. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
  262. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
  263. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
  264. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
  265. { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
  266. }
  267. };
  268. #endif
  269. /*----------------------------------------------------------------------------+
  270. | EBC Devices Characteristics
  271. | Peripheral Bank Access Parameters - EBC0_BnAP
  272. | Peripheral Bank Configuration Register - EBC0_BnCR
  273. +----------------------------------------------------------------------------*/
  274. /* Small Flash */
  275. #define EBC0_BNAP_SMALL_FLASH \
  276. EBC0_BNAP_BME_DISABLED | \
  277. EBC0_BNAP_TWT_ENCODE(6) | \
  278. EBC0_BNAP_CSN_ENCODE(0) | \
  279. EBC0_BNAP_OEN_ENCODE(1) | \
  280. EBC0_BNAP_WBN_ENCODE(1) | \
  281. EBC0_BNAP_WBF_ENCODE(3) | \
  282. EBC0_BNAP_TH_ENCODE(1) | \
  283. EBC0_BNAP_RE_ENABLED | \
  284. EBC0_BNAP_SOR_DELAYED | \
  285. EBC0_BNAP_BEM_WRITEONLY | \
  286. EBC0_BNAP_PEN_DISABLED
  287. #define EBC0_BNCR_SMALL_FLASH_CS0 \
  288. EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
  289. EBC0_BNCR_BS_1MB | \
  290. EBC0_BNCR_BU_RW | \
  291. EBC0_BNCR_BW_8BIT
  292. #define EBC0_BNCR_SMALL_FLASH_CS4 \
  293. EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
  294. EBC0_BNCR_BS_1MB | \
  295. EBC0_BNCR_BU_RW | \
  296. EBC0_BNCR_BW_8BIT
  297. /* Large Flash or SRAM */
  298. #define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
  299. EBC0_BNAP_BME_DISABLED | \
  300. EBC0_BNAP_TWT_ENCODE(8) | \
  301. EBC0_BNAP_CSN_ENCODE(0) | \
  302. EBC0_BNAP_OEN_ENCODE(1) | \
  303. EBC0_BNAP_WBN_ENCODE(1) | \
  304. EBC0_BNAP_WBF_ENCODE(1) | \
  305. EBC0_BNAP_TH_ENCODE(2) | \
  306. EBC0_BNAP_SOR_DELAYED | \
  307. EBC0_BNAP_BEM_RW | \
  308. EBC0_BNAP_PEN_DISABLED
  309. #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
  310. EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
  311. EBC0_BNCR_BS_8MB | \
  312. EBC0_BNCR_BU_RW | \
  313. EBC0_BNCR_BW_16BIT
  314. #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
  315. EBC0_BNCR_BAS_ENCODE(0x87800000) | \
  316. EBC0_BNCR_BS_8MB | \
  317. EBC0_BNCR_BU_RW | \
  318. EBC0_BNCR_BW_16BIT
  319. /* NVRAM - FPGA */
  320. #define EBC0_BNAP_NVRAM_FPGA \
  321. EBC0_BNAP_BME_DISABLED | \
  322. EBC0_BNAP_TWT_ENCODE(9) | \
  323. EBC0_BNAP_CSN_ENCODE(0) | \
  324. EBC0_BNAP_OEN_ENCODE(1) | \
  325. EBC0_BNAP_WBN_ENCODE(1) | \
  326. EBC0_BNAP_WBF_ENCODE(0) | \
  327. EBC0_BNAP_TH_ENCODE(2) | \
  328. EBC0_BNAP_RE_ENABLED | \
  329. EBC0_BNAP_SOR_DELAYED | \
  330. EBC0_BNAP_BEM_WRITEONLY | \
  331. EBC0_BNAP_PEN_DISABLED
  332. #define EBC0_BNCR_NVRAM_FPGA_CS5 \
  333. EBC0_BNCR_BAS_ENCODE(0x80000000) | \
  334. EBC0_BNCR_BS_1MB | \
  335. EBC0_BNCR_BU_RW | \
  336. EBC0_BNCR_BW_8BIT
  337. /* Nand Flash */
  338. #define EBC0_BNAP_NAND_FLASH \
  339. EBC0_BNAP_BME_DISABLED | \
  340. EBC0_BNAP_TWT_ENCODE(3) | \
  341. EBC0_BNAP_CSN_ENCODE(0) | \
  342. EBC0_BNAP_OEN_ENCODE(0) | \
  343. EBC0_BNAP_WBN_ENCODE(0) | \
  344. EBC0_BNAP_WBF_ENCODE(0) | \
  345. EBC0_BNAP_TH_ENCODE(1) | \
  346. EBC0_BNAP_RE_ENABLED | \
  347. EBC0_BNAP_SOR_NOT_DELAYED | \
  348. EBC0_BNAP_BEM_RW | \
  349. EBC0_BNAP_PEN_DISABLED
  350. #define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
  351. /* NAND0 */
  352. #define EBC0_BNCR_NAND_FLASH_CS1 \
  353. EBC0_BNCR_BAS_ENCODE(0x90000000) | \
  354. EBC0_BNCR_BS_1MB | \
  355. EBC0_BNCR_BU_RW | \
  356. EBC0_BNCR_BW_32BIT
  357. /* NAND1 - Bank2 */
  358. #define EBC0_BNCR_NAND_FLASH_CS2 \
  359. EBC0_BNCR_BAS_ENCODE(0x94000000) | \
  360. EBC0_BNCR_BS_1MB | \
  361. EBC0_BNCR_BU_RW | \
  362. EBC0_BNCR_BW_32BIT
  363. /* NAND1 - Bank3 */
  364. #define EBC0_BNCR_NAND_FLASH_CS3 \
  365. EBC0_BNCR_BAS_ENCODE(0x94000000) | \
  366. EBC0_BNCR_BS_1MB | \
  367. EBC0_BNCR_BU_RW | \
  368. EBC0_BNCR_BW_32BIT
  369. int board_early_init_f(void)
  370. {
  371. ext_bus_cntlr_init();
  372. /*--------------------------------------------------------------------
  373. * Setup the interrupt controller polarities, triggers, etc.
  374. *-------------------------------------------------------------------*/
  375. mtdcr(uic0sr, 0xffffffff); /* clear all */
  376. mtdcr(uic0er, 0x00000000); /* disable all */
  377. mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
  378. mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
  379. mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
  380. mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
  381. mtdcr(uic0sr, 0xffffffff); /* clear all */
  382. mtdcr(uic1sr, 0xffffffff); /* clear all */
  383. mtdcr(uic1er, 0x00000000); /* disable all */
  384. mtdcr(uic1cr, 0x00000000); /* all non-critical */
  385. mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
  386. mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
  387. mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
  388. mtdcr(uic1sr, 0xffffffff); /* clear all */
  389. /*--------------------------------------------------------------------
  390. * Setup the GPIO pins
  391. *-------------------------------------------------------------------*/
  392. out32(GPIO0_OSRL, 0x00000400);
  393. out32(GPIO0_OSRH, 0x00000000);
  394. out32(GPIO0_TSRL, 0x00000400);
  395. out32(GPIO0_TSRH, 0x00000000);
  396. out32(GPIO0_ISR1L, 0x00000000);
  397. out32(GPIO0_ISR1H, 0x00000000);
  398. out32(GPIO0_ISR2L, 0x00000000);
  399. out32(GPIO0_ISR2H, 0x00000000);
  400. out32(GPIO0_ISR3L, 0x00000000);
  401. out32(GPIO0_ISR3H, 0x00000000);
  402. out32(GPIO1_OSRL, 0x0C380000);
  403. out32(GPIO1_OSRH, 0x00000000);
  404. out32(GPIO1_TSRL, 0x0C380000);
  405. out32(GPIO1_TSRH, 0x00000000);
  406. out32(GPIO1_ISR1L, 0x0FC30000);
  407. out32(GPIO1_ISR1H, 0x00000000);
  408. out32(GPIO1_ISR2L, 0x0C010000);
  409. out32(GPIO1_ISR2H, 0x00000000);
  410. out32(GPIO1_ISR3L, 0x01400000);
  411. out32(GPIO1_ISR3H, 0x00000000);
  412. configure_ppc440ep_pins();
  413. return 0;
  414. }
  415. int checkboard(void)
  416. {
  417. char *s = getenv("serial#");
  418. printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
  419. if (s != NULL) {
  420. puts(", serial# ");
  421. puts(s);
  422. }
  423. putc('\n');
  424. return (0);
  425. }
  426. long int initdram (int board_type)
  427. {
  428. #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
  429. long dram_size;
  430. dram_size = spd_sdram();
  431. return dram_size;
  432. #else
  433. return CFG_MBYTES_SDRAM << 20;
  434. #endif
  435. }
  436. #if defined(CFG_DRAM_TEST)
  437. int testdram(void)
  438. {
  439. unsigned long *mem = (unsigned long *)0;
  440. const unsigned long kend = (1024 / sizeof(unsigned long));
  441. unsigned long k, n, *p32, ctr;
  442. const unsigned long bend = CFG_MBYTES_SDRAM * 1024 * 1024;
  443. mtmsr(0);
  444. for (k = 0; k < CFG_MBYTES_SDRAM*1024;
  445. ++k, mem += (1024 / sizeof(unsigned long))) {
  446. if ((k & 1023) == 0) {
  447. printf("%3d MB\r", k / 1024);
  448. }
  449. memset(mem, 0xaaaaaaaa, 1024);
  450. for (n = 0; n < kend; ++n) {
  451. if (mem[n] != 0xaaaaaaaa) {
  452. printf("SDRAM test fails at: %08x\n",
  453. (uint) & mem[n]);
  454. return 1;
  455. }
  456. }
  457. memset(mem, 0x55555555, 1024);
  458. for (n = 0; n < kend; ++n) {
  459. if (mem[n] != 0x55555555) {
  460. printf("SDRAM test fails at: %08x\n",
  461. (uint) & mem[n]);
  462. return 1;
  463. }
  464. }
  465. }
  466. /*
  467. * Perform a sequence test to ensure that all
  468. * memory locations are uniquely addressable
  469. */
  470. ctr = 0;
  471. p32 = 0;
  472. while ((unsigned long)p32 != bend) {
  473. if (0 == ((unsigned long)p32 & ((1<<20)-1)))
  474. printf("Writing %3d MB\r", (unsigned long)p32 >> 20);
  475. *p32++ = ctr++;
  476. }
  477. ctr = 0;
  478. p32 = 0;
  479. while ((unsigned long)p32 != bend) {
  480. if (0 == ((unsigned long)p32 & ((1<<20)-1)))
  481. printf("Verifying %3d MB\r", (unsigned long)p32 >> 20);
  482. if (*p32 != ctr) {
  483. printf("SDRAM test fails at: %08x\n", p32);
  484. return 1;
  485. }
  486. ctr++;
  487. p32++;
  488. }
  489. printf("SDRAM test passes\n");
  490. return 0;
  491. }
  492. #endif
  493. /*************************************************************************
  494. * pci_pre_init
  495. *
  496. * This routine is called just prior to registering the hose and gives
  497. * the board the opportunity to check things. Returning a value of zero
  498. * indicates that things are bad & PCI initialization should be aborted.
  499. *
  500. * Different boards may wish to customize the pci controller structure
  501. * (add regions, override default access routines, etc) or perform
  502. * certain pre-initialization actions.
  503. *
  504. ************************************************************************/
  505. #if defined(CONFIG_PCI)
  506. int pci_pre_init(struct pci_controller *hose)
  507. {
  508. unsigned long addr;
  509. /*-------------------------------------------------------------------------+
  510. | Set priority for all PLB3 devices to 0.
  511. | Set PLB3 arbiter to fair mode.
  512. +-------------------------------------------------------------------------*/
  513. mfsdr(sdr_amp1, addr);
  514. mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
  515. addr = mfdcr(plb3_acr);
  516. mtdcr(plb3_acr, addr | 0x80000000);
  517. /*-------------------------------------------------------------------------+
  518. | Set priority for all PLB4 devices to 0.
  519. +-------------------------------------------------------------------------*/
  520. mfsdr(sdr_amp0, addr);
  521. mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
  522. addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
  523. mtdcr(plb4_acr, addr);
  524. /*-------------------------------------------------------------------------+
  525. | Set Nebula PLB4 arbiter to fair mode.
  526. +-------------------------------------------------------------------------*/
  527. /* Segment0 */
  528. addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
  529. addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
  530. addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
  531. addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
  532. mtdcr(plb0_acr, addr);
  533. /* Segment1 */
  534. addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
  535. addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
  536. addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
  537. addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
  538. mtdcr(plb1_acr, addr);
  539. return 1;
  540. }
  541. #endif /* defined(CONFIG_PCI) */
  542. /*************************************************************************
  543. * pci_target_init
  544. *
  545. * The bootstrap configuration provides default settings for the pci
  546. * inbound map (PIM). But the bootstrap config choices are limited and
  547. * may not be sufficient for a given board.
  548. *
  549. ************************************************************************/
  550. #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
  551. void pci_target_init(struct pci_controller *hose)
  552. {
  553. /*--------------------------------------------------------------------------+
  554. * Set up Direct MMIO registers
  555. *--------------------------------------------------------------------------*/
  556. /*--------------------------------------------------------------------------+
  557. | PowerPC440 EP PCI Master configuration.
  558. | Map one 1Gig range of PLB/processor addresses to PCI memory space.
  559. | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
  560. | Use byte reversed out routines to handle endianess.
  561. | Make this region non-prefetchable.
  562. +--------------------------------------------------------------------------*/
  563. out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
  564. out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
  565. out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
  566. out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
  567. out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
  568. out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
  569. out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
  570. out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
  571. out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
  572. out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
  573. out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
  574. out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
  575. out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
  576. out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
  577. /*--------------------------------------------------------------------------+
  578. * Set up Configuration registers
  579. *--------------------------------------------------------------------------*/
  580. /* Program the board's subsystem id/vendor id */
  581. pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
  582. CFG_PCI_SUBSYS_VENDORID);
  583. pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
  584. /* Configure command register as bus master */
  585. pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
  586. /* 240nS PCI clock */
  587. pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
  588. /* No error reporting */
  589. pci_write_config_word(0, PCI_ERREN, 0);
  590. pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
  591. }
  592. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
  593. /*************************************************************************
  594. * pci_master_init
  595. *
  596. ************************************************************************/
  597. #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
  598. void pci_master_init(struct pci_controller *hose)
  599. {
  600. unsigned short temp_short;
  601. /*--------------------------------------------------------------------------+
  602. | Write the PowerPC440 EP PCI Configuration regs.
  603. | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
  604. | Enable PowerPC440 EP to act as a PCI memory target (PTM).
  605. +--------------------------------------------------------------------------*/
  606. pci_read_config_word(0, PCI_COMMAND, &temp_short);
  607. pci_write_config_word(0, PCI_COMMAND,
  608. temp_short | PCI_COMMAND_MASTER |
  609. PCI_COMMAND_MEMORY);
  610. }
  611. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
  612. /*************************************************************************
  613. * is_pci_host
  614. *
  615. * This routine is called to determine if a pci scan should be
  616. * performed. With various hardware environments (especially cPCI and
  617. * PPMC) it's insufficient to depend on the state of the arbiter enable
  618. * bit in the strap register, or generic host/adapter assumptions.
  619. *
  620. * Rather than hard-code a bad assumption in the general 440 code, the
  621. * 440 pci code requires the board to decide at runtime.
  622. *
  623. * Return 0 for adapter mode, non-zero for host (monarch) mode.
  624. *
  625. *
  626. ************************************************************************/
  627. #if defined(CONFIG_PCI)
  628. int is_pci_host(struct pci_controller *hose)
  629. {
  630. /* Bamboo is always configured as host. */
  631. return (1);
  632. }
  633. #endif /* defined(CONFIG_PCI) */
  634. /*----------------------------------------------------------------------------+
  635. | is_powerpc440ep_pass1.
  636. +----------------------------------------------------------------------------*/
  637. int is_powerpc440ep_pass1(void)
  638. {
  639. unsigned long pvr;
  640. pvr = get_pvr();
  641. if (pvr == PVR_POWERPC_440EP_PASS1)
  642. return TRUE;
  643. else if (pvr == PVR_POWERPC_440EP_PASS2)
  644. return FALSE;
  645. else {
  646. printf("brdutil error 3\n");
  647. for (;;)
  648. ;
  649. }
  650. return(FALSE);
  651. }
  652. /*----------------------------------------------------------------------------+
  653. | is_nand_selected.
  654. +----------------------------------------------------------------------------*/
  655. int is_nand_selected(void)
  656. {
  657. #ifdef CONFIG_BAMBOO_NAND
  658. return TRUE;
  659. #else
  660. return FALSE;
  661. #endif
  662. }
  663. /*----------------------------------------------------------------------------+
  664. | config_on_ebc_cs4_is_small_flash => from EPLD
  665. +----------------------------------------------------------------------------*/
  666. unsigned char config_on_ebc_cs4_is_small_flash(void)
  667. {
  668. /* Not implemented yet => returns constant value */
  669. return TRUE;
  670. }
  671. /*----------------------------------------------------------------------------+
  672. | Ext_bus_cntlr_init.
  673. | Initialize the external bus controller
  674. +----------------------------------------------------------------------------*/
  675. void ext_bus_cntlr_init(void)
  676. {
  677. unsigned long sdr0_pstrp0, sdr0_sdstp1;
  678. unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
  679. int computed_boot_device = BOOT_DEVICE_UNKNOWN;
  680. unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
  681. unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
  682. unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
  683. unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
  684. unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
  685. /*-------------------------------------------------------------------------+
  686. |
  687. | PART 1 : Initialize EBC Bank 5
  688. | ==============================
  689. | Bank5 is always associated to the NVRAM/EPLD.
  690. | It has to be initialized prior to other banks settings computation since
  691. | some board registers values may be needed
  692. |
  693. +-------------------------------------------------------------------------*/
  694. /* NVRAM - FPGA */
  695. mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
  696. mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
  697. /*-------------------------------------------------------------------------+
  698. |
  699. | PART 2 : Determine which boot device was selected
  700. | =========================================
  701. |
  702. | Read Pin Strap Register in PPC440EP
  703. | In case of boot from IIC, read Serial Device Strap Register1
  704. |
  705. | Result can either be :
  706. | - Boot from EBC 8bits => SMALL FLASH
  707. | - Boot from EBC 16bits => Large Flash or SRAM
  708. | - Boot from NAND Flash
  709. | - Boot from PCI
  710. |
  711. +-------------------------------------------------------------------------*/
  712. /* Read Pin Strap Register in PPC440EP */
  713. mfsdr(sdr_pstrp0, sdr0_pstrp0);
  714. bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
  715. /*-------------------------------------------------------------------------+
  716. | PPC440EP Pass1
  717. +-------------------------------------------------------------------------*/
  718. if (is_powerpc440ep_pass1() == TRUE) {
  719. switch(bootstrap_settings) {
  720. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
  721. /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
  722. /* Boot from Small Flash */
  723. computed_boot_device = BOOT_FROM_SMALL_FLASH;
  724. break;
  725. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
  726. /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
  727. /* Boot from PCI */
  728. computed_boot_device = BOOT_FROM_PCI;
  729. break;
  730. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
  731. /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
  732. /* Boot from Nand Flash */
  733. computed_boot_device = BOOT_FROM_NAND_FLASH0;
  734. break;
  735. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
  736. /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
  737. /* Boot from Small Flash */
  738. computed_boot_device = BOOT_FROM_SMALL_FLASH;
  739. break;
  740. case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
  741. case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
  742. /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
  743. /* Read Serial Device Strap Register1 in PPC440EP */
  744. mfsdr(sdr_sdstp1, sdr0_sdstp1);
  745. boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
  746. ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
  747. switch(boot_selection) {
  748. case SDR0_SDSTP1_BOOT_SEL_EBC:
  749. switch(ebc_boot_size) {
  750. case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
  751. computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
  752. break;
  753. case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
  754. computed_boot_device = BOOT_FROM_SMALL_FLASH;
  755. break;
  756. }
  757. break;
  758. case SDR0_SDSTP1_BOOT_SEL_PCI:
  759. computed_boot_device = BOOT_FROM_PCI;
  760. break;
  761. case SDR0_SDSTP1_BOOT_SEL_NDFC:
  762. computed_boot_device = BOOT_FROM_NAND_FLASH0;
  763. break;
  764. }
  765. break;
  766. }
  767. }
  768. /*-------------------------------------------------------------------------+
  769. | PPC440EP Pass2
  770. +-------------------------------------------------------------------------*/
  771. else {
  772. switch(bootstrap_settings) {
  773. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
  774. /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
  775. /* Boot from Small Flash */
  776. computed_boot_device = BOOT_FROM_SMALL_FLASH;
  777. break;
  778. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
  779. /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
  780. /* Boot from PCI */
  781. computed_boot_device = BOOT_FROM_PCI;
  782. break;
  783. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
  784. /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
  785. /* Boot from Nand Flash */
  786. computed_boot_device = BOOT_FROM_NAND_FLASH0;
  787. break;
  788. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
  789. /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
  790. /* Boot from Large Flash or SRAM */
  791. computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
  792. break;
  793. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
  794. /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
  795. /* Boot from Large Flash or SRAM */
  796. computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
  797. break;
  798. case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
  799. /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
  800. /* Boot from PCI */
  801. computed_boot_device = BOOT_FROM_PCI;
  802. break;
  803. case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
  804. case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
  805. /* Default Strap Settings 5-7 */
  806. /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
  807. /* Read Serial Device Strap Register1 in PPC440EP */
  808. mfsdr(sdr_sdstp1, sdr0_sdstp1);
  809. boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
  810. ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
  811. switch(boot_selection) {
  812. case SDR0_SDSTP1_BOOT_SEL_EBC:
  813. switch(ebc_boot_size) {
  814. case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
  815. computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
  816. break;
  817. case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
  818. computed_boot_device = BOOT_FROM_SMALL_FLASH;
  819. break;
  820. }
  821. break;
  822. case SDR0_SDSTP1_BOOT_SEL_PCI:
  823. computed_boot_device = BOOT_FROM_PCI;
  824. break;
  825. case SDR0_SDSTP1_BOOT_SEL_NDFC:
  826. computed_boot_device = BOOT_FROM_NAND_FLASH0;
  827. break;
  828. }
  829. break;
  830. }
  831. }
  832. /*-------------------------------------------------------------------------+
  833. |
  834. | PART 3 : Compute EBC settings depending on selected boot device
  835. | ====== ======================================================
  836. |
  837. | Resulting EBC init will be among following configurations :
  838. |
  839. | - Boot from EBC 8bits => boot from SMALL FLASH selected
  840. | EBC-CS0 = Small Flash
  841. | EBC-CS1,2,3 = NAND Flash or
  842. | Exp.Slot depending on Soft Config
  843. | EBC-CS4 = SRAM/Large Flash or
  844. | Large Flash/SRAM depending on jumpers
  845. | EBC-CS5 = NVRAM / EPLD
  846. |
  847. | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
  848. | EBC-CS0 = SRAM/Large Flash or
  849. | Large Flash/SRAM depending on jumpers
  850. | EBC-CS1,2,3 = NAND Flash or
  851. | Exp.Slot depending on Software Configuration
  852. | EBC-CS4 = Small Flash
  853. | EBC-CS5 = NVRAM / EPLD
  854. |
  855. | - Boot from NAND Flash
  856. | EBC-CS0 = NAND Flash0
  857. | EBC-CS1,2,3 = NAND Flash1
  858. | EBC-CS4 = SRAM/Large Flash or
  859. | Large Flash/SRAM depending on jumpers
  860. | EBC-CS5 = NVRAM / EPLD
  861. |
  862. | - Boot from PCI
  863. | EBC-CS0 = ...
  864. | EBC-CS1,2,3 = NAND Flash or
  865. | Exp.Slot depending on Software Configuration
  866. | EBC-CS4 = SRAM/Large Flash or
  867. | Large Flash/SRAM or
  868. | Small Flash depending on jumpers
  869. | EBC-CS5 = NVRAM / EPLD
  870. |
  871. +-------------------------------------------------------------------------*/
  872. switch(computed_boot_device) {
  873. /*------------------------------------------------------------------------- */
  874. case BOOT_FROM_SMALL_FLASH:
  875. /*------------------------------------------------------------------------- */
  876. ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
  877. ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
  878. if ((is_nand_selected()) == TRUE) {
  879. /* NAND Flash */
  880. ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
  881. ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
  882. ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
  883. ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
  884. ebc0_cs3_bnap_value = 0;
  885. ebc0_cs3_bncr_value = 0;
  886. } else {
  887. /* Expansion Slot */
  888. ebc0_cs1_bnap_value = 0;
  889. ebc0_cs1_bncr_value = 0;
  890. ebc0_cs2_bnap_value = 0;
  891. ebc0_cs2_bncr_value = 0;
  892. ebc0_cs3_bnap_value = 0;
  893. ebc0_cs3_bncr_value = 0;
  894. }
  895. ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
  896. ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
  897. break;
  898. /*------------------------------------------------------------------------- */
  899. case BOOT_FROM_LARGE_FLASH_OR_SRAM:
  900. /*------------------------------------------------------------------------- */
  901. ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
  902. ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
  903. if ((is_nand_selected()) == TRUE) {
  904. /* NAND Flash */
  905. ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
  906. ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
  907. ebc0_cs2_bnap_value = 0;
  908. ebc0_cs2_bncr_value = 0;
  909. ebc0_cs3_bnap_value = 0;
  910. ebc0_cs3_bncr_value = 0;
  911. } else {
  912. /* Expansion Slot */
  913. ebc0_cs1_bnap_value = 0;
  914. ebc0_cs1_bncr_value = 0;
  915. ebc0_cs2_bnap_value = 0;
  916. ebc0_cs2_bncr_value = 0;
  917. ebc0_cs3_bnap_value = 0;
  918. ebc0_cs3_bncr_value = 0;
  919. }
  920. ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
  921. ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
  922. break;
  923. /*------------------------------------------------------------------------- */
  924. case BOOT_FROM_NAND_FLASH0:
  925. /*------------------------------------------------------------------------- */
  926. ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
  927. ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
  928. ebc0_cs1_bnap_value = 0;
  929. ebc0_cs1_bncr_value = 0;
  930. ebc0_cs2_bnap_value = 0;
  931. ebc0_cs2_bncr_value = 0;
  932. ebc0_cs3_bnap_value = 0;
  933. ebc0_cs3_bncr_value = 0;
  934. /* Large Flash or SRAM */
  935. ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
  936. ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
  937. break;
  938. /*------------------------------------------------------------------------- */
  939. case BOOT_FROM_PCI:
  940. /*------------------------------------------------------------------------- */
  941. ebc0_cs0_bnap_value = 0;
  942. ebc0_cs0_bncr_value = 0;
  943. if ((is_nand_selected()) == TRUE) {
  944. /* NAND Flash */
  945. ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
  946. ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
  947. ebc0_cs2_bnap_value = 0;
  948. ebc0_cs2_bncr_value = 0;
  949. ebc0_cs3_bnap_value = 0;
  950. ebc0_cs3_bncr_value = 0;
  951. } else {
  952. /* Expansion Slot */
  953. ebc0_cs1_bnap_value = 0;
  954. ebc0_cs1_bncr_value = 0;
  955. ebc0_cs2_bnap_value = 0;
  956. ebc0_cs2_bncr_value = 0;
  957. ebc0_cs3_bnap_value = 0;
  958. ebc0_cs3_bncr_value = 0;
  959. }
  960. if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
  961. /* Small Flash */
  962. ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
  963. ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
  964. } else {
  965. /* Large Flash or SRAM */
  966. ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
  967. ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
  968. }
  969. break;
  970. /*------------------------------------------------------------------------- */
  971. case BOOT_DEVICE_UNKNOWN:
  972. /*------------------------------------------------------------------------- */
  973. /* Error */
  974. break;
  975. }
  976. /*-------------------------------------------------------------------------+
  977. | Initialize EBC CONFIG
  978. +-------------------------------------------------------------------------*/
  979. mtdcr(ebccfga, xbcfg);
  980. mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN |
  981. EBC0_CFG_PTD_ENABLED |
  982. EBC0_CFG_RTC_2048PERCLK |
  983. EBC0_CFG_EMPL_LOW |
  984. EBC0_CFG_EMPH_LOW |
  985. EBC0_CFG_CSTC_DRIVEN |
  986. EBC0_CFG_BPF_ONEDW |
  987. EBC0_CFG_EMS_8BIT |
  988. EBC0_CFG_PME_DISABLED |
  989. EBC0_CFG_PMT_ENCODE(0) );
  990. /*-------------------------------------------------------------------------+
  991. | Initialize EBC Bank 0-4
  992. +-------------------------------------------------------------------------*/
  993. /* EBC Bank0 */
  994. mtebc(pb0ap, ebc0_cs0_bnap_value);
  995. mtebc(pb0cr, ebc0_cs0_bncr_value);
  996. /* EBC Bank1 */
  997. mtebc(pb1ap, ebc0_cs1_bnap_value);
  998. mtebc(pb1cr, ebc0_cs1_bncr_value);
  999. /* EBC Bank2 */
  1000. mtebc(pb2ap, ebc0_cs2_bnap_value);
  1001. mtebc(pb2cr, ebc0_cs2_bncr_value);
  1002. /* EBC Bank3 */
  1003. mtebc(pb3ap, ebc0_cs3_bnap_value);
  1004. mtebc(pb3cr, ebc0_cs3_bncr_value);
  1005. /* EBC Bank4 */
  1006. mtebc(pb4ap, ebc0_cs4_bnap_value);
  1007. mtebc(pb4cr, ebc0_cs4_bncr_value);
  1008. return;
  1009. }
  1010. /*----------------------------------------------------------------------------+
  1011. | get_uart_configuration.
  1012. +----------------------------------------------------------------------------*/
  1013. uart_config_nb_t get_uart_configuration(void)
  1014. {
  1015. return (L4);
  1016. }
  1017. /*----------------------------------------------------------------------------+
  1018. | set_phy_configuration_through_fpga => to EPLD
  1019. +----------------------------------------------------------------------------*/
  1020. void set_phy_configuration_through_fpga(zmii_config_t config)
  1021. {
  1022. unsigned long fpga_selection_reg;
  1023. fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
  1024. switch(config)
  1025. {
  1026. case ZMII_CONFIGURATION_IS_MII:
  1027. fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
  1028. break;
  1029. case ZMII_CONFIGURATION_IS_RMII:
  1030. fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
  1031. break;
  1032. case ZMII_CONFIGURATION_IS_SMII:
  1033. fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
  1034. break;
  1035. case ZMII_CONFIGURATION_UNKNOWN:
  1036. default:
  1037. break;
  1038. }
  1039. out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
  1040. }
  1041. /*----------------------------------------------------------------------------+
  1042. | scp_selection_in_fpga.
  1043. +----------------------------------------------------------------------------*/
  1044. void scp_selection_in_fpga(void)
  1045. {
  1046. unsigned long fpga_selection_2_reg;
  1047. fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
  1048. fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
  1049. out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
  1050. }
  1051. /*----------------------------------------------------------------------------+
  1052. | iic1_selection_in_fpga.
  1053. +----------------------------------------------------------------------------*/
  1054. void iic1_selection_in_fpga(void)
  1055. {
  1056. unsigned long fpga_selection_2_reg;
  1057. fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
  1058. fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
  1059. out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
  1060. }
  1061. /*----------------------------------------------------------------------------+
  1062. | dma_a_b_selection_in_fpga.
  1063. +----------------------------------------------------------------------------*/
  1064. void dma_a_b_selection_in_fpga(void)
  1065. {
  1066. unsigned long fpga_selection_2_reg;
  1067. fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
  1068. out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
  1069. }
  1070. /*----------------------------------------------------------------------------+
  1071. | dma_a_b_unselect_in_fpga.
  1072. +----------------------------------------------------------------------------*/
  1073. void dma_a_b_unselect_in_fpga(void)
  1074. {
  1075. unsigned long fpga_selection_2_reg;
  1076. fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
  1077. out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
  1078. }
  1079. /*----------------------------------------------------------------------------+
  1080. | dma_c_d_selection_in_fpga.
  1081. +----------------------------------------------------------------------------*/
  1082. void dma_c_d_selection_in_fpga(void)
  1083. {
  1084. unsigned long fpga_selection_2_reg;
  1085. fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
  1086. out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
  1087. }
  1088. /*----------------------------------------------------------------------------+
  1089. | dma_c_d_unselect_in_fpga.
  1090. +----------------------------------------------------------------------------*/
  1091. void dma_c_d_unselect_in_fpga(void)
  1092. {
  1093. unsigned long fpga_selection_2_reg;
  1094. fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
  1095. out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
  1096. }
  1097. /*----------------------------------------------------------------------------+
  1098. | usb2_device_selection_in_fpga.
  1099. +----------------------------------------------------------------------------*/
  1100. void usb2_device_selection_in_fpga(void)
  1101. {
  1102. unsigned long fpga_selection_1_reg;
  1103. fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
  1104. out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
  1105. }
  1106. /*----------------------------------------------------------------------------+
  1107. | usb2_device_reset_through_fpga.
  1108. +----------------------------------------------------------------------------*/
  1109. void usb2_device_reset_through_fpga(void)
  1110. {
  1111. /* Perform soft Reset pulse */
  1112. unsigned long fpga_reset_reg;
  1113. int i;
  1114. fpga_reset_reg = in8(FPGA_RESET_REG);
  1115. out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
  1116. for (i=0; i<500; i++)
  1117. udelay(1000);
  1118. out8(FPGA_RESET_REG,fpga_reset_reg);
  1119. }
  1120. /*----------------------------------------------------------------------------+
  1121. | usb2_host_selection_in_fpga.
  1122. +----------------------------------------------------------------------------*/
  1123. void usb2_host_selection_in_fpga(void)
  1124. {
  1125. unsigned long fpga_selection_1_reg;
  1126. fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
  1127. out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
  1128. }
  1129. /*----------------------------------------------------------------------------+
  1130. | ndfc_selection_in_fpga.
  1131. +----------------------------------------------------------------------------*/
  1132. void ndfc_selection_in_fpga(void)
  1133. {
  1134. unsigned long fpga_selection_1_reg;
  1135. fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
  1136. fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
  1137. fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
  1138. out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
  1139. }
  1140. /*----------------------------------------------------------------------------+
  1141. | uart_selection_in_fpga.
  1142. +----------------------------------------------------------------------------*/
  1143. void uart_selection_in_fpga(uart_config_nb_t uart_config)
  1144. {
  1145. /* FPGA register */
  1146. unsigned char fpga_selection_3_reg;
  1147. /* Read FPGA Reagister */
  1148. fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
  1149. switch (uart_config)
  1150. {
  1151. case L1:
  1152. /* ----------------------------------------------------------------------- */
  1153. /* L1 configuration: UART0 = 8 pins */
  1154. /* ----------------------------------------------------------------------- */
  1155. /* Configure FPGA */
  1156. fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
  1157. fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
  1158. out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
  1159. break;
  1160. case L2:
  1161. /* ----------------------------------------------------------------------- */
  1162. /* L2 configuration: UART0 = 4 pins */
  1163. /* UART1 = 4 pins */
  1164. /* ----------------------------------------------------------------------- */
  1165. /* Configure FPGA */
  1166. fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
  1167. fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
  1168. out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
  1169. break;
  1170. case L3:
  1171. /* ----------------------------------------------------------------------- */
  1172. /* L3 configuration: UART0 = 4 pins */
  1173. /* UART1 = 2 pins */
  1174. /* UART2 = 2 pins */
  1175. /* ----------------------------------------------------------------------- */
  1176. /* Configure FPGA */
  1177. fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
  1178. fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
  1179. out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
  1180. break;
  1181. case L4:
  1182. /* Configure FPGA */
  1183. fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
  1184. fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
  1185. out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
  1186. break;
  1187. default:
  1188. /* Unsupported UART configuration number */
  1189. for (;;)
  1190. ;
  1191. break;
  1192. }
  1193. }
  1194. /*----------------------------------------------------------------------------+
  1195. | init_default_gpio
  1196. +----------------------------------------------------------------------------*/
  1197. void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1198. {
  1199. int i;
  1200. /* Init GPIO0 */
  1201. for(i=0; i<GPIO_MAX; i++)
  1202. {
  1203. gpio_tab[GPIO0][i].add = GPIO0_BASE;
  1204. gpio_tab[GPIO0][i].in_out = GPIO_DIS;
  1205. gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
  1206. }
  1207. /* Init GPIO1 */
  1208. for(i=0; i<GPIO_MAX; i++)
  1209. {
  1210. gpio_tab[GPIO1][i].add = GPIO1_BASE;
  1211. gpio_tab[GPIO1][i].in_out = GPIO_DIS;
  1212. gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
  1213. }
  1214. /* EBC_CS_N(5) - GPIO0_10 */
  1215. gpio_tab[GPIO0][10].in_out = GPIO_OUT;
  1216. gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
  1217. /* EBC_CS_N(4) - GPIO0_9 */
  1218. gpio_tab[GPIO0][9].in_out = GPIO_OUT;
  1219. gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
  1220. }
  1221. /*----------------------------------------------------------------------------+
  1222. | update_uart_ios
  1223. +------------------------------------------------------------------------------
  1224. |
  1225. | Set UART Configuration in PowerPC440EP
  1226. |
  1227. | +---------------------------------------------------------------------+
  1228. | | Configuartion | Connector | Nb of pins | Pins | Associated |
  1229. | | Number | Port Name | available | naming | CORE |
  1230. | +-----------------+---------------+------------+--------+-------------+
  1231. | | L1 | Port_A | 8 | UART | UART core 0 |
  1232. | +-----------------+---------------+------------+--------+-------------+
  1233. | | L2 | Port_A | 4 | UART1 | UART core 0 |
  1234. | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
  1235. | +-----------------+---------------+------------+--------+-------------+
  1236. | | L3 | Port_A | 4 | UART1 | UART core 0 |
  1237. | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
  1238. | | | Port_C | 2 | UART3 | UART core 2 |
  1239. | +-----------------+---------------+------------+--------+-------------+
  1240. | | | Port_A | 2 | UART1 | UART core 0 |
  1241. | | L4 | Port_B | 2 | UART2 | UART core 1 |
  1242. | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
  1243. | | | Port_D | 2 | UART4 | UART core 3 |
  1244. | +-----------------+---------------+------------+--------+-------------+
  1245. |
  1246. | Involved GPIOs
  1247. |
  1248. | +------------------------------------------------------------------------------+
  1249. | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
  1250. | +---------+------------------+-----+-----------------+-----+-------------+-----+
  1251. | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
  1252. | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
  1253. | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
  1254. | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
  1255. | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
  1256. | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
  1257. | +------------------------------------------------------------------------------+
  1258. |
  1259. |
  1260. +----------------------------------------------------------------------------*/
  1261. void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
  1262. {
  1263. switch (uart_config)
  1264. {
  1265. case L1:
  1266. /* ----------------------------------------------------------------------- */
  1267. /* L1 configuration: UART0 = 8 pins */
  1268. /* ----------------------------------------------------------------------- */
  1269. /* Update GPIO Configuration Table */
  1270. gpio_tab[GPIO1][2].in_out = GPIO_IN;
  1271. gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
  1272. gpio_tab[GPIO1][3].in_out = GPIO_IN;
  1273. gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
  1274. gpio_tab[GPIO1][4].in_out = GPIO_IN;
  1275. gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
  1276. gpio_tab[GPIO1][5].in_out = GPIO_OUT;
  1277. gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
  1278. gpio_tab[GPIO1][6].in_out = GPIO_OUT;
  1279. gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
  1280. gpio_tab[GPIO1][7].in_out = GPIO_IN;
  1281. gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
  1282. break;
  1283. case L2:
  1284. /* ----------------------------------------------------------------------- */
  1285. /* L2 configuration: UART0 = 4 pins */
  1286. /* UART1 = 4 pins */
  1287. /* ----------------------------------------------------------------------- */
  1288. /* Update GPIO Configuration Table */
  1289. gpio_tab[GPIO1][2].in_out = GPIO_IN;
  1290. gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
  1291. gpio_tab[GPIO1][3].in_out = GPIO_OUT;
  1292. gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
  1293. gpio_tab[GPIO1][4].in_out = GPIO_IN;
  1294. gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
  1295. gpio_tab[GPIO1][5].in_out = GPIO_OUT;
  1296. gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
  1297. gpio_tab[GPIO1][6].in_out = GPIO_OUT;
  1298. gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
  1299. gpio_tab[GPIO1][7].in_out = GPIO_IN;
  1300. gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
  1301. break;
  1302. case L3:
  1303. /* ----------------------------------------------------------------------- */
  1304. /* L3 configuration: UART0 = 4 pins */
  1305. /* UART1 = 2 pins */
  1306. /* UART2 = 2 pins */
  1307. /* ----------------------------------------------------------------------- */
  1308. /* Update GPIO Configuration Table */
  1309. gpio_tab[GPIO1][2].in_out = GPIO_OUT;
  1310. gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
  1311. gpio_tab[GPIO1][3].in_out = GPIO_IN;
  1312. gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
  1313. gpio_tab[GPIO1][4].in_out = GPIO_IN;
  1314. gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
  1315. gpio_tab[GPIO1][5].in_out = GPIO_OUT;
  1316. gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
  1317. gpio_tab[GPIO1][6].in_out = GPIO_OUT;
  1318. gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
  1319. gpio_tab[GPIO1][7].in_out = GPIO_IN;
  1320. gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
  1321. break;
  1322. case L4:
  1323. /* ----------------------------------------------------------------------- */
  1324. /* L4 configuration: UART0 = 2 pins */
  1325. /* UART1 = 2 pins */
  1326. /* UART2 = 2 pins */
  1327. /* UART3 = 2 pins */
  1328. /* ----------------------------------------------------------------------- */
  1329. /* Update GPIO Configuration Table */
  1330. gpio_tab[GPIO1][2].in_out = GPIO_OUT;
  1331. gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
  1332. gpio_tab[GPIO1][3].in_out = GPIO_IN;
  1333. gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
  1334. gpio_tab[GPIO1][4].in_out = GPIO_IN;
  1335. gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
  1336. gpio_tab[GPIO1][5].in_out = GPIO_OUT;
  1337. gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
  1338. gpio_tab[GPIO1][6].in_out = GPIO_OUT;
  1339. gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
  1340. gpio_tab[GPIO1][7].in_out = GPIO_IN;
  1341. gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
  1342. break;
  1343. default:
  1344. /* Unsupported UART configuration number */
  1345. printf("ERROR - Unsupported UART configuration number.\n\n");
  1346. for (;;)
  1347. ;
  1348. break;
  1349. }
  1350. /* Set input Selection Register on Alt_Receive for UART Input Core */
  1351. out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
  1352. out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
  1353. out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
  1354. }
  1355. /*----------------------------------------------------------------------------+
  1356. | update_ndfc_ios(void).
  1357. +----------------------------------------------------------------------------*/
  1358. void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1359. {
  1360. /* Update GPIO Configuration Table */
  1361. gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
  1362. gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
  1363. gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
  1364. gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
  1365. #if 0
  1366. gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
  1367. gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
  1368. #endif
  1369. }
  1370. /*----------------------------------------------------------------------------+
  1371. | update_zii_ios(void).
  1372. +----------------------------------------------------------------------------*/
  1373. void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1374. {
  1375. /* Update GPIO Configuration Table */
  1376. gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
  1377. gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
  1378. gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
  1379. gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
  1380. gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
  1381. gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
  1382. gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
  1383. gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
  1384. gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
  1385. gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
  1386. gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
  1387. gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
  1388. gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
  1389. gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
  1390. gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
  1391. gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
  1392. gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
  1393. gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
  1394. gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
  1395. gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
  1396. gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
  1397. gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
  1398. gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
  1399. gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
  1400. gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
  1401. gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
  1402. gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
  1403. gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
  1404. }
  1405. /*----------------------------------------------------------------------------+
  1406. | update_uic_0_3_irq_ios().
  1407. +----------------------------------------------------------------------------*/
  1408. void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1409. {
  1410. gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
  1411. gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
  1412. gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
  1413. gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
  1414. gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
  1415. gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
  1416. gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
  1417. gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
  1418. }
  1419. /*----------------------------------------------------------------------------+
  1420. | update_uic_4_9_irq_ios().
  1421. +----------------------------------------------------------------------------*/
  1422. void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1423. {
  1424. gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
  1425. gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
  1426. gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
  1427. gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
  1428. gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
  1429. gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
  1430. gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
  1431. gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
  1432. gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
  1433. gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
  1434. }
  1435. /*----------------------------------------------------------------------------+
  1436. | update_dma_a_b_ios().
  1437. +----------------------------------------------------------------------------*/
  1438. void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1439. {
  1440. gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
  1441. gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
  1442. gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
  1443. gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
  1444. gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
  1445. gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
  1446. gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
  1447. gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
  1448. gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
  1449. gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
  1450. }
  1451. /*----------------------------------------------------------------------------+
  1452. | update_dma_c_d_ios().
  1453. +----------------------------------------------------------------------------*/
  1454. void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1455. {
  1456. gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
  1457. gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
  1458. gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
  1459. gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
  1460. gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
  1461. gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
  1462. gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
  1463. gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
  1464. gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
  1465. gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
  1466. gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
  1467. gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
  1468. }
  1469. /*----------------------------------------------------------------------------+
  1470. | update_ebc_master_ios().
  1471. +----------------------------------------------------------------------------*/
  1472. void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1473. {
  1474. gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
  1475. gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
  1476. gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
  1477. gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
  1478. gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
  1479. gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
  1480. gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
  1481. gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
  1482. }
  1483. /*----------------------------------------------------------------------------+
  1484. | update_usb2_device_ios().
  1485. +----------------------------------------------------------------------------*/
  1486. void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1487. {
  1488. gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
  1489. gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
  1490. gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
  1491. gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
  1492. gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
  1493. gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
  1494. gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
  1495. gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
  1496. gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
  1497. gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
  1498. gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
  1499. gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
  1500. gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
  1501. gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
  1502. gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
  1503. gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
  1504. }
  1505. /*----------------------------------------------------------------------------+
  1506. | update_pci_patch_ios().
  1507. +----------------------------------------------------------------------------*/
  1508. void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
  1509. {
  1510. gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
  1511. gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
  1512. }
  1513. /*----------------------------------------------------------------------------+
  1514. | set_chip_gpio_configuration(unsigned char gpio_core,
  1515. | gpio_param_s (*gpio_tab)[GPIO_MAX])
  1516. | Put the core impacted by clock modification and sharing in reset.
  1517. | Config the select registers to resolve the sharing depending of the config.
  1518. | Configure the GPIO registers.
  1519. |
  1520. +----------------------------------------------------------------------------*/
  1521. void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
  1522. {
  1523. unsigned char i=0, j=0, reg_offset = 0;
  1524. unsigned long gpio_reg, gpio_core_add;
  1525. /* GPIO config of the GPIOs 0 to 31 */
  1526. for (i=0; i<GPIO_MAX; i++, j++)
  1527. {
  1528. if (i == GPIO_MAX/2)
  1529. {
  1530. reg_offset = 4;
  1531. j = i-16;
  1532. }
  1533. gpio_core_add = gpio_tab[gpio_core][i].add;
  1534. if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
  1535. (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
  1536. {
  1537. switch (gpio_tab[gpio_core][i].alt_nb)
  1538. {
  1539. case GPIO_SEL:
  1540. break;
  1541. case GPIO_ALT1:
  1542. gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1543. gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
  1544. out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
  1545. break;
  1546. case GPIO_ALT2:
  1547. gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1548. gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
  1549. out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
  1550. break;
  1551. case GPIO_ALT3:
  1552. gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1553. gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
  1554. out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
  1555. break;
  1556. }
  1557. }
  1558. if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
  1559. (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
  1560. {
  1561. switch (gpio_tab[gpio_core][i].alt_nb)
  1562. {
  1563. case GPIO_SEL:
  1564. break;
  1565. case GPIO_ALT1:
  1566. gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1567. gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
  1568. out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
  1569. gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1570. gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
  1571. out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
  1572. break;
  1573. case GPIO_ALT2:
  1574. gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1575. gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
  1576. out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
  1577. gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1578. gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
  1579. out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
  1580. break;
  1581. case GPIO_ALT3:
  1582. gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1583. gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
  1584. out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
  1585. gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
  1586. gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
  1587. out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
  1588. break;
  1589. }
  1590. }
  1591. }
  1592. }
  1593. /*----------------------------------------------------------------------------+
  1594. | force_bup_core_selection.
  1595. +----------------------------------------------------------------------------*/
  1596. void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
  1597. {
  1598. /* Pointer invalid */
  1599. if (core_select_P == NULL)
  1600. {
  1601. printf("Configuration invalid pointer 1\n");
  1602. for (;;)
  1603. ;
  1604. }
  1605. /* L4 Selection */
  1606. *(core_select_P+UART_CORE0) = CORE_SELECTED;
  1607. *(core_select_P+UART_CORE1) = CORE_SELECTED;
  1608. *(core_select_P+UART_CORE2) = CORE_SELECTED;
  1609. *(core_select_P+UART_CORE3) = CORE_SELECTED;
  1610. /* RMII Selection */
  1611. *(core_select_P+RMII_SEL) = CORE_SELECTED;
  1612. /* External Interrupt 0-9 selection */
  1613. *(core_select_P+UIC_0_3) = CORE_SELECTED;
  1614. *(core_select_P+UIC_4_9) = CORE_SELECTED;
  1615. *(core_select_P+SCP_CORE) = CORE_SELECTED;
  1616. *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
  1617. *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
  1618. *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
  1619. if (is_nand_selected()) {
  1620. *(core_select_P+NAND_FLASH) = CORE_SELECTED;
  1621. }
  1622. *config_val_P = CONFIG_IS_VALID;
  1623. }
  1624. /*----------------------------------------------------------------------------+
  1625. | configure_ppc440ep_pins.
  1626. +----------------------------------------------------------------------------*/
  1627. void configure_ppc440ep_pins(void)
  1628. {
  1629. uart_config_nb_t uart_configuration;
  1630. config_validity_t config_val = CONFIG_IS_INVALID;
  1631. /* Create Core Selection Table */
  1632. core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
  1633. {
  1634. CORE_NOT_SELECTED, /* IIC_CORE, */
  1635. CORE_NOT_SELECTED, /* SPC_CORE, */
  1636. CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
  1637. CORE_NOT_SELECTED, /* UIC_4_9, */
  1638. CORE_NOT_SELECTED, /* USB2_HOST, */
  1639. CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
  1640. CORE_NOT_SELECTED, /* USB2_DEVICE, */
  1641. CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
  1642. CORE_NOT_SELECTED, /* USB1_DEVICE, */
  1643. CORE_NOT_SELECTED, /* EBC_MASTER, */
  1644. CORE_NOT_SELECTED, /* NAND_FLASH, */
  1645. CORE_NOT_SELECTED, /* UART_CORE0, */
  1646. CORE_NOT_SELECTED, /* UART_CORE1, */
  1647. CORE_NOT_SELECTED, /* UART_CORE2, */
  1648. CORE_NOT_SELECTED, /* UART_CORE3, */
  1649. CORE_NOT_SELECTED, /* MII_SEL, */
  1650. CORE_NOT_SELECTED, /* RMII_SEL, */
  1651. CORE_NOT_SELECTED, /* SMII_SEL, */
  1652. CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
  1653. CORE_NOT_SELECTED, /* UIC_0_3 */
  1654. CORE_NOT_SELECTED, /* USB1_HOST */
  1655. CORE_NOT_SELECTED /* PCI_PATCH */
  1656. };
  1657. gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
  1658. /* Table Default Initialisation + FPGA Access */
  1659. init_default_gpio(gpio_tab);
  1660. set_chip_gpio_configuration(GPIO0, gpio_tab);
  1661. set_chip_gpio_configuration(GPIO1, gpio_tab);
  1662. /* Update Table */
  1663. force_bup_core_selection(ppc440ep_core_selection, &config_val);
  1664. #if 0 /* test-only */
  1665. /* If we are running PIBS 1, force known configuration */
  1666. update_core_selection_table(ppc440ep_core_selection, &config_val);
  1667. #endif
  1668. /*----------------------------------------------------------------------------+
  1669. | SDR + ios table update + fpga initialization
  1670. +----------------------------------------------------------------------------*/
  1671. unsigned long sdr0_pfc1 = 0;
  1672. unsigned long sdr0_usb0 = 0;
  1673. unsigned long sdr0_mfr = 0;
  1674. /* PCI Always selected */
  1675. /* I2C Selection */
  1676. if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
  1677. {
  1678. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
  1679. iic1_selection_in_fpga();
  1680. }
  1681. /* SCP Selection */
  1682. if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
  1683. {
  1684. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
  1685. scp_selection_in_fpga();
  1686. }
  1687. /* UIC 0:3 Selection */
  1688. if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
  1689. {
  1690. update_uic_0_3_irq_ios(gpio_tab);
  1691. dma_a_b_unselect_in_fpga();
  1692. }
  1693. /* UIC 4:9 Selection */
  1694. if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
  1695. {
  1696. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
  1697. update_uic_4_9_irq_ios(gpio_tab);
  1698. }
  1699. /* DMA AB Selection */
  1700. if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
  1701. {
  1702. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
  1703. update_dma_a_b_ios(gpio_tab);
  1704. dma_a_b_selection_in_fpga();
  1705. }
  1706. /* DMA CD Selection */
  1707. if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
  1708. {
  1709. update_dma_c_d_ios(gpio_tab);
  1710. dma_c_d_selection_in_fpga();
  1711. }
  1712. /* EBC Master Selection */
  1713. if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
  1714. {
  1715. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
  1716. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
  1717. update_ebc_master_ios(gpio_tab);
  1718. }
  1719. /* PCI Patch Enable */
  1720. if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
  1721. {
  1722. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
  1723. update_pci_patch_ios(gpio_tab);
  1724. }
  1725. /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
  1726. if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
  1727. {
  1728. /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
  1729. printf("Invalid configuration => USB2 Host selected\n");
  1730. for (;;)
  1731. ;
  1732. /*usb2_host_selection_in_fpga(); */
  1733. }
  1734. /* USB2.0 Device Selection */
  1735. if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
  1736. {
  1737. update_usb2_device_ios(gpio_tab);
  1738. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
  1739. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
  1740. mfsdr(sdr_usb0, sdr0_usb0);
  1741. sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
  1742. sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
  1743. mtsdr(sdr_usb0, sdr0_usb0);
  1744. usb2_device_selection_in_fpga();
  1745. }
  1746. /* USB1.1 Device Selection */
  1747. if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
  1748. {
  1749. mfsdr(sdr_usb0, sdr0_usb0);
  1750. sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
  1751. sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
  1752. mtsdr(sdr_usb0, sdr0_usb0);
  1753. }
  1754. /* USB1.1 Host Selection */
  1755. if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
  1756. {
  1757. mfsdr(sdr_usb0, sdr0_usb0);
  1758. sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
  1759. sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
  1760. mtsdr(sdr_usb0, sdr0_usb0);
  1761. }
  1762. /* NAND Flash Selection */
  1763. if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
  1764. {
  1765. update_ndfc_ios(gpio_tab);
  1766. #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
  1767. mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
  1768. SDR0_CUST0_NDFC_ENABLE |
  1769. SDR0_CUST0_NDFC_BW_8_BIT |
  1770. SDR0_CUST0_NDFC_ARE_MASK |
  1771. SDR0_CUST0_CHIPSELGAT_EN1 |
  1772. SDR0_CUST0_CHIPSELGAT_EN2);
  1773. #else
  1774. mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
  1775. SDR0_CUST0_NDFC_ENABLE |
  1776. SDR0_CUST0_NDFC_BW_8_BIT |
  1777. SDR0_CUST0_NDFC_ARE_MASK |
  1778. SDR0_CUST0_CHIPSELGAT_EN0 |
  1779. SDR0_CUST0_CHIPSELGAT_EN2);
  1780. #endif
  1781. ndfc_selection_in_fpga();
  1782. }
  1783. else
  1784. {
  1785. /* Set Mux on EMAC */
  1786. mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
  1787. }
  1788. /* MII Selection */
  1789. if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
  1790. {
  1791. update_zii_ios(gpio_tab);
  1792. mfsdr(sdr_mfr, sdr0_mfr);
  1793. sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
  1794. mtsdr(sdr_mfr, sdr0_mfr);
  1795. set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
  1796. }
  1797. /* RMII Selection */
  1798. if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
  1799. {
  1800. update_zii_ios(gpio_tab);
  1801. mfsdr(sdr_mfr, sdr0_mfr);
  1802. sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
  1803. mtsdr(sdr_mfr, sdr0_mfr);
  1804. set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
  1805. }
  1806. /* SMII Selection */
  1807. if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
  1808. {
  1809. update_zii_ios(gpio_tab);
  1810. mfsdr(sdr_mfr, sdr0_mfr);
  1811. sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
  1812. mtsdr(sdr_mfr, sdr0_mfr);
  1813. set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
  1814. }
  1815. /* UART Selection */
  1816. uart_configuration = get_uart_configuration();
  1817. switch (uart_configuration)
  1818. {
  1819. case L1: /* L1 Selection */
  1820. /* UART0 8 pins Only */
  1821. /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
  1822. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
  1823. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
  1824. break;
  1825. case L2: /* L2 Selection */
  1826. /* UART0 and UART1 4 pins */
  1827. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
  1828. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
  1829. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
  1830. break;
  1831. case L3: /* L3 Selection */
  1832. /* UART0 4 pins, UART1 and UART2 2 pins */
  1833. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
  1834. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
  1835. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
  1836. break;
  1837. case L4: /* L4 Selection */
  1838. /* UART0, UART1, UART2 and UART3 2 pins */
  1839. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
  1840. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
  1841. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
  1842. break;
  1843. }
  1844. update_uart_ios(uart_configuration, gpio_tab);
  1845. /* UART Selection in all cases */
  1846. uart_selection_in_fpga(uart_configuration);
  1847. /* Packet Reject Function Available */
  1848. if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
  1849. {
  1850. /* Set UPR Bit in SDR0_PFC1 Register */
  1851. sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
  1852. }
  1853. /* Packet Reject Function Enable */
  1854. if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
  1855. {
  1856. mfsdr(sdr_mfr, sdr0_mfr);
  1857. sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
  1858. mtsdr(sdr_mfr, sdr0_mfr);
  1859. }
  1860. /* Perform effective access to hardware */
  1861. mtsdr(sdr_pfc1, sdr0_pfc1);
  1862. set_chip_gpio_configuration(GPIO0, gpio_tab);
  1863. set_chip_gpio_configuration(GPIO1, gpio_tab);
  1864. /* USB2.0 Device Reset must be done after GPIO setting */
  1865. if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
  1866. usb2_device_reset_through_fpga();
  1867. }