yucca.c 36 KB

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  1. /*
  2. * (C) Copyright 2006
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. * Port to AMCC-440SPE Evaluation Board SOP - April 2005
  24. *
  25. * PCIe supporting routines derived from Linux 440SPe PCIe driver.
  26. */
  27. #include <common.h>
  28. #include <ppc4xx.h>
  29. #include <i2c.h>
  30. #include <asm/processor.h>
  31. #include <asm/io.h>
  32. #include <asm/4xx_pcie.h>
  33. #include "yucca.h"
  34. DECLARE_GLOBAL_DATA_PTR;
  35. void fpga_init (void);
  36. #define DEBUG_ENV
  37. #ifdef DEBUG_ENV
  38. #define DEBUGF(fmt,args...) printf(fmt ,##args)
  39. #else
  40. #define DEBUGF(fmt,args...)
  41. #endif
  42. #define FALSE 0
  43. #define TRUE 1
  44. int board_early_init_f (void)
  45. {
  46. /*----------------------------------------------------------------------------+
  47. | Define Boot devices
  48. +----------------------------------------------------------------------------*/
  49. #define BOOT_FROM_SMALL_FLASH 0x00
  50. #define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
  51. #define BOOT_FROM_PCI 0x02
  52. #define BOOT_DEVICE_UNKNOWN 0x03
  53. /*----------------------------------------------------------------------------+
  54. | EBC Devices Characteristics
  55. | Peripheral Bank Access Parameters - EBC_BxAP
  56. | Peripheral Bank Configuration Register - EBC_BxCR
  57. +----------------------------------------------------------------------------*/
  58. /*
  59. * Small Flash and FRAM
  60. * BU Value
  61. * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
  62. * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000
  63. * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000
  64. */
  65. #define EBC_BXAP_SMALL_FLASH EBC_BXAP_BME_DISABLED | \
  66. EBC_BXAP_TWT_ENCODE(7) | \
  67. EBC_BXAP_BCE_DISABLE | \
  68. EBC_BXAP_BCT_2TRANS | \
  69. EBC_BXAP_CSN_ENCODE(0) | \
  70. EBC_BXAP_OEN_ENCODE(0) | \
  71. EBC_BXAP_WBN_ENCODE(0) | \
  72. EBC_BXAP_WBF_ENCODE(0) | \
  73. EBC_BXAP_TH_ENCODE(0) | \
  74. EBC_BXAP_RE_DISABLED | \
  75. EBC_BXAP_SOR_DELAYED | \
  76. EBC_BXAP_BEM_WRITEONLY | \
  77. EBC_BXAP_PEN_DISABLED
  78. #define EBC_BXCR_SMALL_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \
  79. EBC_BXCR_BS_16MB | \
  80. EBC_BXCR_BU_RW | \
  81. EBC_BXCR_BW_8BIT
  82. #define EBC_BXCR_SMALL_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xe7000000) | \
  83. EBC_BXCR_BS_16MB | \
  84. EBC_BXCR_BU_RW | \
  85. EBC_BXCR_BW_8BIT
  86. /*
  87. * Large Flash and SRAM
  88. * BU Value
  89. * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
  90. * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
  91. * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
  92. */
  93. #define EBC_BXAP_LARGE_FLASH EBC_BXAP_BME_DISABLED | \
  94. EBC_BXAP_TWT_ENCODE(7) | \
  95. EBC_BXAP_BCE_DISABLE | \
  96. EBC_BXAP_BCT_2TRANS | \
  97. EBC_BXAP_CSN_ENCODE(0) | \
  98. EBC_BXAP_OEN_ENCODE(0) | \
  99. EBC_BXAP_WBN_ENCODE(0) | \
  100. EBC_BXAP_WBF_ENCODE(0) | \
  101. EBC_BXAP_TH_ENCODE(0) | \
  102. EBC_BXAP_RE_DISABLED | \
  103. EBC_BXAP_SOR_DELAYED | \
  104. EBC_BXAP_BEM_WRITEONLY | \
  105. EBC_BXAP_PEN_DISABLED
  106. #define EBC_BXCR_LARGE_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \
  107. EBC_BXCR_BS_16MB | \
  108. EBC_BXCR_BU_RW | \
  109. EBC_BXCR_BW_16BIT
  110. #define EBC_BXCR_LARGE_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xE7000000) | \
  111. EBC_BXCR_BS_16MB | \
  112. EBC_BXCR_BU_RW | \
  113. EBC_BXCR_BW_16BIT
  114. /*
  115. * FPGA
  116. * BU value :
  117. * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
  118. * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000
  119. */
  120. #define EBC_BXAP_FPGA EBC_BXAP_BME_DISABLED | \
  121. EBC_BXAP_TWT_ENCODE(11) | \
  122. EBC_BXAP_BCE_DISABLE | \
  123. EBC_BXAP_BCT_2TRANS | \
  124. EBC_BXAP_CSN_ENCODE(10) | \
  125. EBC_BXAP_OEN_ENCODE(1) | \
  126. EBC_BXAP_WBN_ENCODE(1) | \
  127. EBC_BXAP_WBF_ENCODE(1) | \
  128. EBC_BXAP_TH_ENCODE(1) | \
  129. EBC_BXAP_RE_DISABLED | \
  130. EBC_BXAP_SOR_DELAYED | \
  131. EBC_BXAP_BEM_RW | \
  132. EBC_BXAP_PEN_DISABLED
  133. #define EBC_BXCR_FPGA_CS1 EBC_BXCR_BAS_ENCODE(0xe2000000) | \
  134. EBC_BXCR_BS_1MB | \
  135. EBC_BXCR_BU_RW | \
  136. EBC_BXCR_BW_16BIT
  137. unsigned long mfr;
  138. /*
  139. * Define Variables for EBC initialization depending on BOOTSTRAP option
  140. */
  141. unsigned long sdr0_pinstp, sdr0_sdstp1 ;
  142. unsigned long bootstrap_settings, ebc_data_width, boot_selection;
  143. int computed_boot_device = BOOT_DEVICE_UNKNOWN;
  144. /*-------------------------------------------------------------------+
  145. | Initialize EBC CONFIG -
  146. | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
  147. | default value :
  148. | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
  149. |
  150. +-------------------------------------------------------------------*/
  151. mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
  152. EBC_CFG_PTD_ENABLE |
  153. EBC_CFG_RTC_16PERCLK |
  154. EBC_CFG_ATC_PREVIOUS |
  155. EBC_CFG_DTC_PREVIOUS |
  156. EBC_CFG_CTC_PREVIOUS |
  157. EBC_CFG_OEO_PREVIOUS |
  158. EBC_CFG_EMC_DEFAULT |
  159. EBC_CFG_PME_DISABLE |
  160. EBC_CFG_PR_16);
  161. /*-------------------------------------------------------------------+
  162. |
  163. | PART 1 : Initialize EBC Bank 1
  164. | ==============================
  165. | Bank1 is always associated to the EPLD.
  166. | It has to be initialized prior to other banks settings computation
  167. | since some board registers values may be needed to determine the
  168. | boot type
  169. |
  170. +-------------------------------------------------------------------*/
  171. mtebc(pb1ap, EBC_BXAP_FPGA);
  172. mtebc(pb1cr, EBC_BXCR_FPGA_CS1);
  173. /*-------------------------------------------------------------------+
  174. |
  175. | PART 2 : Determine which boot device was selected
  176. | =================================================
  177. |
  178. | Read Pin Strap Register in PPC440SPe
  179. | Result can either be :
  180. | - Boot strap = boot from EBC 8bits => Small Flash
  181. | - Boot strap = boot from PCI
  182. | - Boot strap = IIC
  183. | In case of boot from IIC, read Serial Device Strap Register1
  184. |
  185. | Result can either be :
  186. | - Boot from EBC - EBC Bus Width = 8bits => Small Flash
  187. | - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM
  188. | - Boot from PCI
  189. |
  190. +-------------------------------------------------------------------*/
  191. /* Read Pin Strap Register in PPC440SP */
  192. mfsdr(SDR0_PINSTP, sdr0_pinstp);
  193. bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
  194. switch (bootstrap_settings) {
  195. case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
  196. /*
  197. * Strapping Option A
  198. * Boot from EBC - 8 bits , Small Flash
  199. */
  200. computed_boot_device = BOOT_FROM_SMALL_FLASH;
  201. break;
  202. case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
  203. /*
  204. * Strappping Option B
  205. * Boot from PCI
  206. */
  207. computed_boot_device = BOOT_FROM_PCI;
  208. break;
  209. case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
  210. case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
  211. /*
  212. * Strapping Option C or D
  213. * Boot Settings in IIC EEprom address 0x50 or 0x54
  214. * Read Serial Device Strap Register1 in PPC440SPe
  215. */
  216. mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
  217. boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
  218. ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
  219. switch (boot_selection) {
  220. case SDR0_SDSTP1_ERPN_EBC:
  221. switch (ebc_data_width) {
  222. case SDR0_SDSTP1_EBCW_16_BITS:
  223. computed_boot_device =
  224. BOOT_FROM_LARGE_FLASH_OR_SRAM;
  225. break;
  226. case SDR0_SDSTP1_EBCW_8_BITS :
  227. computed_boot_device = BOOT_FROM_SMALL_FLASH;
  228. break;
  229. }
  230. break;
  231. case SDR0_SDSTP1_ERPN_PCI:
  232. computed_boot_device = BOOT_FROM_PCI;
  233. break;
  234. default:
  235. /* should not occure */
  236. computed_boot_device = BOOT_DEVICE_UNKNOWN;
  237. }
  238. break;
  239. default:
  240. /* should not be */
  241. computed_boot_device = BOOT_DEVICE_UNKNOWN;
  242. break;
  243. }
  244. /*-------------------------------------------------------------------+
  245. |
  246. | PART 3 : Compute EBC settings depending on selected boot device
  247. | ====== ======================================================
  248. |
  249. | Resulting EBC init will be among following configurations :
  250. |
  251. | - Boot from EBC 8bits => boot from Small Flash selected
  252. | EBC-CS0 = Small Flash
  253. | EBC-CS2 = Large Flash and SRAM
  254. |
  255. | - Boot from EBC 16bits => boot from Large Flash or SRAM
  256. | EBC-CS0 = Large Flash or SRAM
  257. | EBC-CS2 = Small Flash
  258. |
  259. | - Boot from PCI
  260. | EBC-CS0 = not initialized to avoid address contention
  261. | EBC-CS2 = same as boot from Small Flash selected
  262. |
  263. +-------------------------------------------------------------------*/
  264. unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
  265. unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
  266. switch (computed_boot_device) {
  267. /*-------------------------------------------------------------------*/
  268. case BOOT_FROM_PCI:
  269. /*-------------------------------------------------------------------*/
  270. /*
  271. * By Default CS2 is affected to LARGE Flash
  272. * do not initialize SMALL FLASH to avoid address contention
  273. * Large Flash
  274. */
  275. ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
  276. ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
  277. break;
  278. /*-------------------------------------------------------------------*/
  279. case BOOT_FROM_SMALL_FLASH:
  280. /*-------------------------------------------------------------------*/
  281. ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
  282. ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
  283. /*
  284. * Large Flash or SRAM
  285. */
  286. /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
  287. ebc0_cs2_bxap_value = 0x048ff240;
  288. ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
  289. break;
  290. /*-------------------------------------------------------------------*/
  291. case BOOT_FROM_LARGE_FLASH_OR_SRAM:
  292. /*-------------------------------------------------------------------*/
  293. ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
  294. ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
  295. /* Small flash */
  296. ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
  297. ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
  298. break;
  299. /*-------------------------------------------------------------------*/
  300. default:
  301. /*-------------------------------------------------------------------*/
  302. /* BOOT_DEVICE_UNKNOWN */
  303. break;
  304. }
  305. mtebc(pb0ap, ebc0_cs0_bxap_value);
  306. mtebc(pb0cr, ebc0_cs0_bxcr_value);
  307. mtebc(pb2ap, ebc0_cs2_bxap_value);
  308. mtebc(pb2cr, ebc0_cs2_bxcr_value);
  309. /*--------------------------------------------------------------------+
  310. | Interrupt controller setup for the AMCC 440SPe Evaluation board.
  311. +--------------------------------------------------------------------+
  312. +---------------------------------------------------------------------+
  313. |Interrupt| Source | Pol. | Sensi.| Crit. |
  314. +---------+-----------------------------------+-------+-------+-------+
  315. | IRQ 00 | UART0 | High | Level | Non |
  316. | IRQ 01 | UART1 | High | Level | Non |
  317. | IRQ 02 | IIC0 | High | Level | Non |
  318. | IRQ 03 | IIC1 | High | Level | Non |
  319. | IRQ 04 | PCI0X0 MSG IN | High | Level | Non |
  320. | IRQ 05 | PCI0X0 CMD Write | High | Level | Non |
  321. | IRQ 06 | PCI0X0 Power Mgt | High | Level | Non |
  322. | IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non |
  323. | IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non |
  324. | IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |
  325. | IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |
  326. | IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |
  327. | IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non |
  328. | IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non |
  329. | IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non |
  330. | IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non |
  331. | IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |
  332. | IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |
  333. | IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |
  334. | IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non |
  335. | IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non |
  336. | IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non |
  337. | IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non |
  338. | IRQ 23 | I2O Inbound Doorbell | High | Level | Non |
  339. | IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non |
  340. | IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non |
  341. | IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non |
  342. | IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non |
  343. | IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non |
  344. | IRQ 29 | GPT Down Count Timer | Rising| Edge | Non |
  345. | IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |
  346. | IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |
  347. |----------------------------------------------------------------------
  348. | IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non |
  349. | IRQ 33 | MAL Serr | High | Level | Non |
  350. | IRQ 34 | MAL Txde | High | Level | Non |
  351. | IRQ 35 | MAL Rxde | High | Level | Non |
  352. | IRQ 36 | DMC CE or DMC UE | High | Level | Non |
  353. | IRQ 37 | EBC or UART2 | High |Lvl Edg| Non |
  354. | IRQ 38 | MAL TX EOB | High | Level | Non |
  355. | IRQ 39 | MAL RX EOB | High | Level | Non |
  356. | IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non |
  357. | IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non |
  358. | IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non |
  359. | IRQ 43 | L2 Cache | Risin | Edge | Non |
  360. | IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non |
  361. | IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non |
  362. | IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non |
  363. | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
  364. | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
  365. | IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non |
  366. | IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non |
  367. | IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non |
  368. | IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
  369. | IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non |
  370. | IRQ 54 | DMA Error | High | Level | Non |
  371. | IRQ 55 | DMA I2O Error | High | Level | Non |
  372. | IRQ 56 | Serial ROM | High | Level | Non |
  373. | IRQ 57 | PCIX0 Error | High | Edge | Non |
  374. | IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non |
  375. | IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non |
  376. | IRQ 60 | EMAC0 Interrupt | High | Level | Non |
  377. | IRQ 61 | EMAC0 Wake-up | High | Level | Non |
  378. | IRQ 62 | Reserved | High | Level | Non |
  379. | IRQ 63 | XOR | High | Level | Non |
  380. |----------------------------------------------------------------------
  381. | IRQ 64 | PE0 AL | High | Level | Non |
  382. | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
  383. | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
  384. | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
  385. | IRQ 68 | PE0 TCR | High | Level | Non |
  386. | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
  387. | IRQ 70 | PE0 DCR Error | High | Level | Non |
  388. | IRQ 71 | Reserved | N/A | N/A | Non |
  389. | IRQ 72 | PE1 AL | High | Level | Non |
  390. | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
  391. | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
  392. | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
  393. | IRQ 76 | PE1 TCR | High | Level | Non |
  394. | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
  395. | IRQ 78 | PE1 DCR Error | High | Level | Non |
  396. | IRQ 79 | Reserved | N/A | N/A | Non |
  397. | IRQ 80 | PE2 AL | High | Level | Non |
  398. | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
  399. | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
  400. | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
  401. | IRQ 84 | PE2 TCR | High | Level | Non |
  402. | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
  403. | IRQ 86 | PE2 DCR Error | High | Level | Non |
  404. | IRQ 87 | Reserved | N/A | N/A | Non |
  405. | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
  406. | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
  407. | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
  408. | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
  409. | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
  410. | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
  411. | IRQ 94 | Reserved | N/A | N/A | Non |
  412. | IRQ 95 | Reserved | N/A | N/A | Non |
  413. |---------------------------------------------------------------------
  414. | IRQ 96 | PE0 INTA | High | Level | Non |
  415. | IRQ 97 | PE0 INTB | High | Level | Non |
  416. | IRQ 98 | PE0 INTC | High | Level | Non |
  417. | IRQ 99 | PE0 INTD | High | Level | Non |
  418. | IRQ 100 | PE1 INTA | High | Level | Non |
  419. | IRQ 101 | PE1 INTB | High | Level | Non |
  420. | IRQ 102 | PE1 INTC | High | Level | Non |
  421. | IRQ 103 | PE1 INTD | High | Level | Non |
  422. | IRQ 104 | PE2 INTA | High | Level | Non |
  423. | IRQ 105 | PE2 INTB | High | Level | Non |
  424. | IRQ 106 | PE2 INTC | High | Level | Non |
  425. | IRQ 107 | PE2 INTD | Risin | Edge | Non |
  426. | IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non |
  427. | IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non |
  428. | IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non |
  429. | IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non |
  430. | IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non |
  431. | IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non |
  432. | IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non |
  433. | IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non |
  434. | IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non |
  435. | IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non |
  436. | IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non |
  437. | IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non |
  438. | IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non |
  439. | IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non |
  440. | IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non |
  441. | IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non |
  442. | IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non |
  443. | IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non |
  444. | IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non |
  445. | IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non |
  446. +---------+-----------------------------------+-------+-------+------*/
  447. /*--------------------------------------------------------------------+
  448. | Put UICs in PowerPC440SPemode.
  449. | Initialise UIC registers. Clear all interrupts. Disable all
  450. | interrupts.
  451. | Set critical interrupt values. Set interrupt polarities. Set
  452. | interrupt trigger levels. Make bit 0 High priority. Clear all
  453. | interrupts again.
  454. +-------------------------------------------------------------------*/
  455. mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
  456. mtdcr (uic3er, 0x00000000); /* disable all interrupts */
  457. mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical
  458. * interrupts */
  459. mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities */
  460. mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
  461. mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest
  462. * priority */
  463. mtdcr (uic3sr, 0x00000000); /* clear all interrupts */
  464. mtdcr (uic3sr, 0xffffffff); /* clear all interrupts */
  465. mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
  466. mtdcr (uic2er, 0x00000000); /* disable all interrupts */
  467. mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical
  468. * interrupts */
  469. mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities */
  470. mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
  471. mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest
  472. * priority */
  473. mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
  474. mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
  475. mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
  476. mtdcr (uic1er, 0x00000000); /* disable all interrupts */
  477. mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical
  478. * interrupts */
  479. mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
  480. mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels */
  481. mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest
  482. * priority */
  483. mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
  484. mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
  485. mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
  486. mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted
  487. * cascade to be checked */
  488. mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical
  489. * interrupts */
  490. mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities */
  491. mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
  492. mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest
  493. * priority */
  494. mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
  495. mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
  496. mfsdr(sdr_mfr, mfr);
  497. mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
  498. mtsdr(sdr_mfr, mfr);
  499. fpga_init();
  500. return 0;
  501. }
  502. int checkboard (void)
  503. {
  504. char *s = getenv("serial#");
  505. printf("Board: Yucca - AMCC 440SPe Evaluation Board");
  506. if (s != NULL) {
  507. puts(", serial# ");
  508. puts(s);
  509. }
  510. putc('\n');
  511. return 0;
  512. }
  513. /*
  514. * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
  515. * board specific values.
  516. */
  517. static int ppc440spe_rev_a(void)
  518. {
  519. if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
  520. return 1;
  521. else
  522. return 0;
  523. }
  524. u32 ddr_wrdtr(u32 default_val) {
  525. /*
  526. * Yucca boards with 440SPe rev. A need a slightly different setup
  527. * for the MCIF0_WRDTR register.
  528. */
  529. if (ppc440spe_rev_a())
  530. return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
  531. return default_val;
  532. }
  533. u32 ddr_clktr(u32 default_val) {
  534. /*
  535. * Yucca boards with 440SPe rev. A need a slightly different setup
  536. * for the MCIF0_CLKTR register.
  537. */
  538. if (ppc440spe_rev_a())
  539. return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
  540. return default_val;
  541. }
  542. #if defined(CFG_DRAM_TEST)
  543. int testdram (void)
  544. {
  545. uint *pstart = (uint *) 0x00000000;
  546. uint *pend = (uint *) 0x08000000;
  547. uint *p;
  548. for (p = pstart; p < pend; p++)
  549. *p = 0xaaaaaaaa;
  550. for (p = pstart; p < pend; p++) {
  551. if (*p != 0xaaaaaaaa) {
  552. printf ("SDRAM test fails at: %08x\n", (uint) p);
  553. return 1;
  554. }
  555. }
  556. for (p = pstart; p < pend; p++)
  557. *p = 0x55555555;
  558. for (p = pstart; p < pend; p++) {
  559. if (*p != 0x55555555) {
  560. printf ("SDRAM test fails at: %08x\n", (uint) p);
  561. return 1;
  562. }
  563. }
  564. return 0;
  565. }
  566. #endif
  567. /*************************************************************************
  568. * pci_pre_init
  569. *
  570. * This routine is called just prior to registering the hose and gives
  571. * the board the opportunity to check things. Returning a value of zero
  572. * indicates that things are bad & PCI initialization should be aborted.
  573. *
  574. * Different boards may wish to customize the pci controller structure
  575. * (add regions, override default access routines, etc) or perform
  576. * certain pre-initialization actions.
  577. *
  578. ************************************************************************/
  579. #if defined(CONFIG_PCI)
  580. int pci_pre_init(struct pci_controller * hose )
  581. {
  582. unsigned long strap;
  583. /*-------------------------------------------------------------------+
  584. * The yucca board is always configured as the host & requires the
  585. * PCI arbiter to be enabled.
  586. *-------------------------------------------------------------------*/
  587. mfsdr(sdr_sdstp1, strap);
  588. if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
  589. printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
  590. return 0;
  591. }
  592. return 1;
  593. }
  594. #endif /* defined(CONFIG_PCI) */
  595. /*************************************************************************
  596. * pci_target_init
  597. *
  598. * The bootstrap configuration provides default settings for the pci
  599. * inbound map (PIM). But the bootstrap config choices are limited and
  600. * may not be sufficient for a given board.
  601. *
  602. ************************************************************************/
  603. #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
  604. void pci_target_init(struct pci_controller * hose )
  605. {
  606. /*-------------------------------------------------------------------+
  607. * Disable everything
  608. *-------------------------------------------------------------------*/
  609. out32r( PCIX0_PIM0SA, 0 ); /* disable */
  610. out32r( PCIX0_PIM1SA, 0 ); /* disable */
  611. out32r( PCIX0_PIM2SA, 0 ); /* disable */
  612. out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
  613. /*-------------------------------------------------------------------+
  614. * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
  615. * strapping options to not support sizes such as 128/256 MB.
  616. *-------------------------------------------------------------------*/
  617. out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
  618. out32r( PCIX0_PIM0LAH, 0 );
  619. out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
  620. out32r( PCIX0_BAR0, 0 );
  621. /*-------------------------------------------------------------------+
  622. * Program the board's subsystem id/vendor id
  623. *-------------------------------------------------------------------*/
  624. out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
  625. out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
  626. out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
  627. }
  628. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
  629. #if defined(CONFIG_PCI)
  630. /*************************************************************************
  631. * is_pci_host
  632. *
  633. * This routine is called to determine if a pci scan should be
  634. * performed. With various hardware environments (especially cPCI and
  635. * PPMC) it's insufficient to depend on the state of the arbiter enable
  636. * bit in the strap register, or generic host/adapter assumptions.
  637. *
  638. * Rather than hard-code a bad assumption in the general 440 code, the
  639. * 440 pci code requires the board to decide at runtime.
  640. *
  641. * Return 0 for adapter mode, non-zero for host (monarch) mode.
  642. *
  643. *
  644. ************************************************************************/
  645. int is_pci_host(struct pci_controller *hose)
  646. {
  647. /* The yucca board is always configured as host. */
  648. return 1;
  649. }
  650. int yucca_pcie_card_present(int port)
  651. {
  652. u16 reg;
  653. reg = in_be16((u16 *)FPGA_REG1C);
  654. switch(port) {
  655. case 0:
  656. return !(reg & FPGA_REG1C_PE0_PRSNT);
  657. case 1:
  658. return !(reg & FPGA_REG1C_PE1_PRSNT);
  659. case 2:
  660. return !(reg & FPGA_REG1C_PE2_PRSNT);
  661. default:
  662. return 0;
  663. }
  664. }
  665. /*
  666. * For the given slot, set rootpoint mode, send power to the slot,
  667. * turn on the green LED and turn off the yellow LED, enable the clock
  668. * and turn off reset.
  669. */
  670. void yucca_setup_pcie_fpga_rootpoint(int port)
  671. {
  672. u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
  673. switch(port) {
  674. case 0:
  675. rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
  676. endpoint = 0;
  677. power = FPGA_REG1A_PE0_PWRON;
  678. green_led = FPGA_REG1A_PE0_GLED;
  679. clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
  680. yellow_led = FPGA_REG1A_PE0_YLED;
  681. reset_off = FPGA_REG1C_PE0_PERST;
  682. break;
  683. case 1:
  684. rootpoint = 0;
  685. endpoint = FPGA_REG1C_PE1_ENDPOINT;
  686. power = FPGA_REG1A_PE1_PWRON;
  687. green_led = FPGA_REG1A_PE1_GLED;
  688. clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
  689. yellow_led = FPGA_REG1A_PE1_YLED;
  690. reset_off = FPGA_REG1C_PE1_PERST;
  691. break;
  692. case 2:
  693. rootpoint = 0;
  694. endpoint = FPGA_REG1C_PE2_ENDPOINT;
  695. power = FPGA_REG1A_PE2_PWRON;
  696. green_led = FPGA_REG1A_PE2_GLED;
  697. clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
  698. yellow_led = FPGA_REG1A_PE2_YLED;
  699. reset_off = FPGA_REG1C_PE2_PERST;
  700. break;
  701. default:
  702. return;
  703. }
  704. out_be16((u16 *)FPGA_REG1A,
  705. ~(power | clock | green_led) &
  706. (yellow_led | in_be16((u16 *)FPGA_REG1A)));
  707. out_be16((u16 *)FPGA_REG1C,
  708. ~(endpoint | reset_off) &
  709. (rootpoint | in_be16((u16 *)FPGA_REG1C)));
  710. /*
  711. * Leave device in reset for a while after powering on the
  712. * slot to give it a chance to initialize.
  713. */
  714. udelay(250 * 1000);
  715. out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C));
  716. }
  717. /*
  718. * For the given slot, set endpoint mode, send power to the slot,
  719. * turn on the green LED and turn off the yellow LED, enable the clock
  720. * .In end point mode reset bit is read only.
  721. */
  722. void yucca_setup_pcie_fpga_endpoint(int port)
  723. {
  724. u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
  725. switch(port) {
  726. case 0:
  727. rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
  728. endpoint = 0;
  729. power = FPGA_REG1A_PE0_PWRON;
  730. green_led = FPGA_REG1A_PE0_GLED;
  731. clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
  732. yellow_led = FPGA_REG1A_PE0_YLED;
  733. reset_off = FPGA_REG1C_PE0_PERST;
  734. break;
  735. case 1:
  736. rootpoint = 0;
  737. endpoint = FPGA_REG1C_PE1_ENDPOINT;
  738. power = FPGA_REG1A_PE1_PWRON;
  739. green_led = FPGA_REG1A_PE1_GLED;
  740. clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
  741. yellow_led = FPGA_REG1A_PE1_YLED;
  742. reset_off = FPGA_REG1C_PE1_PERST;
  743. break;
  744. case 2:
  745. rootpoint = 0;
  746. endpoint = FPGA_REG1C_PE2_ENDPOINT;
  747. power = FPGA_REG1A_PE2_PWRON;
  748. green_led = FPGA_REG1A_PE2_GLED;
  749. clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
  750. yellow_led = FPGA_REG1A_PE2_YLED;
  751. reset_off = FPGA_REG1C_PE2_PERST;
  752. break;
  753. default:
  754. return;
  755. }
  756. out_be16((u16 *)FPGA_REG1A,
  757. ~(power | clock | green_led) &
  758. (yellow_led | in_be16((u16 *)FPGA_REG1A)));
  759. out_be16((u16 *)FPGA_REG1C,
  760. ~(rootpoint | reset_off) &
  761. (endpoint | in_be16((u16 *)FPGA_REG1C)));
  762. }
  763. static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
  764. void pcie_setup_hoses(int busno)
  765. {
  766. struct pci_controller *hose;
  767. int i, bus;
  768. int ret = 0;
  769. char *env;
  770. unsigned int delay;
  771. /*
  772. * assume we're called after the PCIX hose is initialized, which takes
  773. * bus ID 0 and therefore start numbering PCIe's from 1.
  774. */
  775. bus = busno;
  776. for (i = 0; i <= 2; i++) {
  777. /* Check for yucca card presence */
  778. if (!yucca_pcie_card_present(i))
  779. continue;
  780. if (is_end_point(i)) {
  781. yucca_setup_pcie_fpga_endpoint(i);
  782. ret = ppc4xx_init_pcie_endport(i);
  783. } else {
  784. yucca_setup_pcie_fpga_rootpoint(i);
  785. ret = ppc4xx_init_pcie_rootport(i);
  786. }
  787. if (ret) {
  788. printf("PCIE%d: initialization as %s failed\n", i,
  789. is_end_point(i) ? "endpoint" : "root-complex");
  790. continue;
  791. }
  792. hose = &pcie_hose[i];
  793. hose->first_busno = bus;
  794. hose->last_busno = bus;
  795. hose->current_busno = bus;
  796. /* setup mem resource */
  797. pci_set_region(hose->regions + 0,
  798. CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
  799. CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
  800. CFG_PCIE_MEMSIZE,
  801. PCI_REGION_MEM);
  802. hose->region_count = 1;
  803. pci_register_hose(hose);
  804. if (is_end_point(i)) {
  805. ppc4xx_setup_pcie_endpoint(hose, i);
  806. /*
  807. * Reson for no scanning is endpoint can not generate
  808. * upstream configuration accesses.
  809. */
  810. } else {
  811. ppc4xx_setup_pcie_rootpoint(hose, i);
  812. env = getenv("pciscandelay");
  813. if (env != NULL) {
  814. delay = simple_strtoul(env, NULL, 10);
  815. if (delay > 5)
  816. printf("Warning, expect noticable delay before "
  817. "PCIe scan due to 'pciscandelay' value!\n");
  818. mdelay(delay * 1000);
  819. }
  820. /*
  821. * Config access can only go down stream
  822. */
  823. hose->last_busno = pci_hose_scan(hose);
  824. bus = hose->last_busno + 1;
  825. }
  826. }
  827. }
  828. #endif /* defined(CONFIG_PCI) */
  829. int misc_init_f (void)
  830. {
  831. uint reg;
  832. #if defined(CONFIG_STRESS)
  833. uint i ;
  834. uint disp;
  835. #endif
  836. out16(FPGA_REG10, (in16(FPGA_REG10) &
  837. ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
  838. FPGA_REG10_10MHZ_ENABLE |
  839. FPGA_REG10_100MHZ_ENABLE |
  840. FPGA_REG10_GIGABIT_ENABLE |
  841. FPGA_REG10_FULL_DUPLEX );
  842. udelay(10000); /* wait 10ms */
  843. out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
  844. /* minimal init for PCIe */
  845. /* pci express 0 Endpoint Mode */
  846. mfsdr(SDR0_PE0DLPSET, reg);
  847. reg &= (~0x00400000);
  848. mtsdr(SDR0_PE0DLPSET, reg);
  849. /* pci express 1 Rootpoint Mode */
  850. mfsdr(SDR0_PE1DLPSET, reg);
  851. reg |= 0x00400000;
  852. mtsdr(SDR0_PE1DLPSET, reg);
  853. /* pci express 2 Rootpoint Mode */
  854. mfsdr(SDR0_PE2DLPSET, reg);
  855. reg |= 0x00400000;
  856. mtsdr(SDR0_PE2DLPSET, reg);
  857. out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
  858. ~FPGA_REG1C_PE0_ROOTPOINT &
  859. ~FPGA_REG1C_PE1_ENDPOINT &
  860. ~FPGA_REG1C_PE2_ENDPOINT));
  861. #if defined(CONFIG_STRESS)
  862. /*
  863. * all this setting done by linux only needed by stress an charac. test
  864. * procedure
  865. * PCIe 1 Rootpoint PCIe2 Endpoint
  866. * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
  867. * Power Level
  868. */
  869. for (i = 0, disp = 0; i < 8; i++, disp += 3) {
  870. mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
  871. reg |= 0x33000000;
  872. mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
  873. }
  874. /*
  875. * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
  876. * Power Level
  877. */
  878. for (i = 0, disp = 0; i < 4; i++, disp += 3) {
  879. mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
  880. reg |= 0x33000000;
  881. mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
  882. }
  883. /*
  884. * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
  885. * Power Level
  886. */
  887. for (i = 0, disp = 0; i < 4; i++, disp += 3) {
  888. mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
  889. reg |= 0x33000000;
  890. mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
  891. }
  892. reg = 0x21242222;
  893. mtsdr(SDR0_PE2UTLSET1, reg);
  894. reg = 0x11000000;
  895. mtsdr(SDR0_PE2UTLSET2, reg);
  896. /* pci express 1 Endpoint Mode */
  897. reg = 0x00004000;
  898. mtsdr(SDR0_PE2DLPSET, reg);
  899. mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
  900. #endif
  901. return 0;
  902. }
  903. void fpga_init(void)
  904. {
  905. /*
  906. * by default sdram access is disabled by fpga
  907. */
  908. out16(FPGA_REG10, (in16 (FPGA_REG10) |
  909. FPGA_REG10_SDRAM_ENABLE |
  910. FPGA_REG10_ENABLE_DISPLAY ));
  911. return;
  912. }
  913. #ifdef CONFIG_POST
  914. /*
  915. * Returns 1 if keys pressed to start the power-on long-running tests
  916. * Called from board_init_f().
  917. */
  918. int post_hotkeys_pressed(void)
  919. {
  920. return (ctrlc());
  921. }
  922. #endif
  923. /*---------------------------------------------------------------------------+
  924. | onboard_pci_arbiter_selected => from EPLD
  925. +---------------------------------------------------------------------------*/
  926. int onboard_pci_arbiter_selected(int core_pci)
  927. {
  928. #if 0
  929. unsigned long onboard_pci_arbiter_sel;
  930. onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
  931. if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
  932. return (BOARD_OPTION_SELECTED);
  933. else
  934. #endif
  935. return (BOARD_OPTION_NOT_SELECTED);
  936. }