Godzil 1d928e7091 Merge branch 'udev' into develop пре 10 година
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ipcore_dir f0a2e85c65 FPGA: updated project files пре 12 година
address.v e33b2b2bc7 FPGA: simple SNES address input filtering пре 12 година
cx4.v 60d7a08117 FPGA: Adjust Cx4 timing to new master clock rate пре 12 година
dac.v 1a52da6272 FPGA: Adjust DAC I²S signal timing пре 12 година
dcm.v e57c4aa450 FPGA/cx4: initial commit пре 12 година
main.ucf d47858083a FPGA/Cx4: update user constraints for changed system clock пре 12 година
main.v 1d928e7091 Merge branch 'udev' into develop пре 10 година
msu.v 9253cc45b0 FPGA: implement MSU1 "audio error" status bit пре 12 година
sd2snes_cx4.xise 2a1ef40796 FPGA/cx4: adjust Cx4 CPU timing пре 12 година
sd_dma.v effa2a6972 FPGA/SDDMA: fix clock glitch, adjust RAM write timings пре 12 година
spi.v 968c347986 FPGA/SPI: detect end of byte via MSB toggle instead of constant compare of async input пре 12 година