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@@ -9,95 +9,77 @@
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<!-- along with the project source files, is sufficient to open and -->
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<!-- implement in ISE Project Navigator. -->
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<!-- -->
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- <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
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+ <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
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</header>
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- <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
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+ <version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
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<files>
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<file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
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</file>
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<file xil_pn:name="clk_test.v" xil_pn:type="FILE_VERILOG">
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
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</file>
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<file xil_pn:name="dac.v" xil_pn:type="FILE_VERILOG">
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
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</file>
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<file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
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</file>
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<file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
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</file>
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<file xil_pn:name="mcu_cmd.v" xil_pn:type="FILE_VERILOG">
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
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</file>
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<file xil_pn:name="msu.v" xil_pn:type="FILE_VERILOG">
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
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</file>
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<file xil_pn:name="sd_dma.v" xil_pn:type="FILE_VERILOG">
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
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</file>
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<file xil_pn:name="spi.v" xil_pn:type="FILE_VERILOG">
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
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</file>
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- <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
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- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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- </file>
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<file xil_pn:name="ipcore_dir/dac_buf.xco" xil_pn:type="FILE_COREGEN">
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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</file>
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<file xil_pn:name="ipcore_dir/msu_databuf.xco" xil_pn:type="FILE_COREGEN">
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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</file>
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<file xil_pn:name="cx4.v" xil_pn:type="FILE_VERILOG">
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
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+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
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</file>
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<file xil_pn:name="ipcore_dir/cx4_datrom.xco" xil_pn:type="FILE_COREGEN">
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
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</file>
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<file xil_pn:name="ipcore_dir/cx4_datram.xco" xil_pn:type="FILE_COREGEN">
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
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+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
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</file>
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<file xil_pn:name="ipcore_dir/cx4_pgmrom.xco" xil_pn:type="FILE_COREGEN">
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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</file>
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<file xil_pn:name="ipcore_dir/cx4_mul.xco" xil_pn:type="FILE_COREGEN">
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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</file>
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- <file xil_pn:name="ipcore_dir/dac_buf.xise" xil_pn:type="FILE_COREGENISE">
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- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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- </file>
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- <file xil_pn:name="ipcore_dir/msu_databuf.xise" xil_pn:type="FILE_COREGENISE">
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- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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- </file>
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- <file xil_pn:name="ipcore_dir/cx4_datrom.xise" xil_pn:type="FILE_COREGENISE">
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- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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- </file>
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- <file xil_pn:name="ipcore_dir/cx4_datram.xise" xil_pn:type="FILE_COREGENISE">
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- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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- </file>
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- <file xil_pn:name="ipcore_dir/cx4_pgmrom.xise" xil_pn:type="FILE_COREGENISE">
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- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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- </file>
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- <file xil_pn:name="ipcore_dir/cx4_mul.xise" xil_pn:type="FILE_COREGENISE">
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+ <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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</files>
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@@ -282,7 +264,7 @@
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<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="default"/>
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<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
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- <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
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+ <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
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<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
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@@ -366,8 +348,8 @@
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<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
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- <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="6" xil_pn:valueState="non-default"/>
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- <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="6" xil_pn:valueState="non-default"/>
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+ <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="3" xil_pn:valueState="non-default"/>
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+ <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="3" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
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@@ -438,9 +420,7 @@
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<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
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</properties>
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- <bindings>
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- <binding xil_pn:location="/main" xil_pn:name="main.ucf"/>
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- </bindings>
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+ <bindings/>
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<libraries/>
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