Browse Source

Linux_SDK_V1.0.3

thead_admin 1 year ago
parent
commit
221913b496
41 changed files with 9949 additions and 509 deletions
  1. 3 0
      arch/riscv/Kconfig
  2. 2 0
      arch/riscv/boot/dts/thead/Makefile
  3. 871 0
      arch/riscv/boot/dts/thead/fire-crash.dts
  4. 98 0
      arch/riscv/boot/dts/thead/fire-emu-crash.dts
  5. 2192 0
      arch/riscv/boot/dts/thead/fire-emu.dts
  6. 2116 0
      arch/riscv/boot/dts/thead/fire.dtsi
  7. 8 8
      arch/riscv/boot/dts/thead/light-a-product.dts
  8. 32 29
      arch/riscv/boot/dts/thead/light-a-val.dts
  9. 29 29
      arch/riscv/boot/dts/thead/light-ant-discrete.dts
  10. 37 35
      arch/riscv/boot/dts/thead/light-ant-ref.dts
  11. 33 33
      arch/riscv/boot/dts/thead/light-b-product.dts
  12. 2359 0
      arch/riscv/boot/dts/thead/light-beagle-ref.dts
  13. 116 19
      arch/riscv/boot/dts/thead/light-beagle.dts
  14. 1 1
      arch/riscv/boot/dts/thead/light-crash.dts
  15. 2 2
      arch/riscv/boot/dts/thead/light-fm-emu.dts
  16. 54 54
      arch/riscv/boot/dts/thead/light-vi-devices.dtsi
  17. 41 48
      arch/riscv/boot/dts/thead/light.dtsi
  18. 310 0
      arch/riscv/configs/fire_defconfig
  19. 310 0
      arch/riscv/configs/fire_emu_defconfig
  20. 1 0
      arch/riscv/configs/light_defconfig
  21. 2 0
      arch/riscv/include/asm/Kbuild
  22. 0 5
      arch/riscv/include/asm/csr.h
  23. 62 105
      arch/riscv/include/asm/spinlock.h
  24. 12 20
      arch/riscv/include/asm/spinlock_types.h
  25. 3 19
      arch/riscv/include/asm/tlbflush.h
  26. 1 1
      arch/riscv/kernel/entry.S
  27. 30 10
      arch/riscv/kernel/stacktrace.c
  28. 3 1
      arch/riscv/mm/cacheflush.c
  29. 35 1
      arch/riscv/mm/context.c
  30. 0 68
      arch/riscv/mm/tlbflush.c
  31. 0 2
      drivers/clk/thead/clk-light-fm.c
  32. 2 2
      drivers/clk/thead/gate/visys-gate.c
  33. 3 3
      drivers/cpufreq/light-mpw-cpufreq.c
  34. 10 0
      drivers/gpu/drm/panel/Kconfig
  35. 1 0
      drivers/gpu/drm/panel/Makefile
  36. 909 0
      drivers/gpu/drm/panel/panel-ili9881d.c
  37. 128 0
      drivers/gpu/drm/panel/panel-ili9881d.h
  38. 1 0
      drivers/i2c/busses/i2c-designware-core.h
  39. 6 2
      drivers/i2c/busses/i2c-designware-master.c
  40. 126 0
      drivers/nvmem/light-efuse.c
  41. 0 12
      include/asm-generic/spinlock.h

+ 3 - 0
arch/riscv/Kconfig

@@ -34,6 +34,7 @@ config RISCV
 	select ARCH_HAS_DMA_MMAP_PGPROT
 	select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
 	select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT
+	select ARCH_USE_QUEUED_RWLOCKS
 	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
 	select ARCH_WANT_FRAME_POINTERS
 	select ARCH_WANT_HUGE_PMD_SHARE if 64BIT
@@ -360,6 +361,8 @@ config RISCV_ISA_C
 
 config NO_SFENCE_VMA
 	bool "Replace sfence.vma with CSR_SMCIR operation"
+	depends on !SMP
+	default y
 
 config RISCV_SWIOTLB
 	bool "Enable SWIOTLB"

+ 2 - 0
arch/riscv/boot/dts/thead/Makefile

@@ -33,3 +33,5 @@ dtb-$(CONFIG_SOC_THEAD) += light-a-val-crash.dtb light-b-product-crash.dtb light
 dtb-$(CONFIG_SOC_THEAD) += light-b-power.dtb
 
 dtb-$(CONFIG_SOC_THEAD) += light-a-val-android.dtb
+
+dtb-$(CONFIG_SOC_THEAD) += fire-emu.dtb fire-emu-crash.dtb

+ 871 - 0
arch/riscv/boot/dts/thead/fire-crash.dts

@@ -0,0 +1,871 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "fire.dtsi"
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "light-vi-devices.dtsi"
+/ {
+	model = "T-HEAD Fire emu board";
+	compatible = "thead,fire-emu", "thead,fire";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		status = "disabled";
+		led0 {
+			label = "SYS_STATUS";
+			gpios = <&gpio1_porta 15 0>;	/* GPIO_ACTIVE_HIGH: 0 */
+			default-state = "off";
+		};
+	};
+
+	display-subsystem {
+		status = "okay";
+	};
+
+	lcd0_backlight: pwm-backlight@0 {
+		status = "disabled";
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <7>;
+	};
+
+	light_iopmp: iopmp {
+		status = "disabled";
+		compatible = "thead,light-iopmp";
+
+		/* config#1: multiple valid regions */
+		iopmp_emmc: IOPMP_EMMC {
+			regions = <0x000000 0x100000>,
+				  <0x100000 0x200000>;
+			attr = <0xFFFFFFFF>;
+			dummy_slave= <0x800000>;
+		};
+
+		/* config#2: iopmp bypass */
+		iopmp_sdio0: IOPMP_SDIO0 {
+			bypass_en;
+		};
+
+		/* config#3: iopmp default region set */
+		iopmp_sdio1: IOPMP_SDIO1 {
+			attr = <0xFFFFFFFF>;
+			is_default_region;
+		};
+
+		iopmp_usb0: IOPMP_USB0 {
+			attr = <0xFFFFFFFF>;
+			is_default_region;
+		};
+
+		iopmp_ao: IOPMP_AO {
+			is_default_region;
+		};
+
+		iopmp_aud: IOPMP_AUD {
+			is_default_region;
+		};
+
+		iopmp_chip_dbg: IOPMP_CHIP_DBG {
+			is_default_region;
+		};
+
+		iopmp_eip120i: IOPMP_EIP120I {
+			is_default_region;
+		};
+
+		iopmp_eip120ii: IOPMP_EIP120II {
+			is_default_region;
+		};
+
+		iopmp_eip120iii: IOPMP_EIP120III {
+			is_default_region;
+		};
+
+		iopmp_isp0: IOPMP_ISP0 {
+			is_default_region;
+		};
+
+		iopmp_isp1: IOPMP_ISP1 {
+			is_default_region;
+		};
+
+		iopmp_dw200: IOPMP_DW200 {
+			is_default_region;
+		};
+
+		iopmp_vipre: IOPMP_VIPRE {
+			is_default_region;
+		};
+
+		iopmp_venc: IOPMP_VENC {
+			is_default_region;
+		};
+
+		iopmp_vdec: IOPMP_VDEC {
+			is_default_region;
+		};
+
+		iopmp_g2d: IOPMP_G2D {
+			is_default_region;
+		};
+
+		iopmp_fce: IOPMP_FCE {
+			is_default_region;
+		};
+
+		iopmp0_dpu: IOPMP0_DPU {
+			bypass_en;
+		};
+
+		iopmp1_dpu: IOPMP1_DPU {
+			bypass_en;
+		};
+
+		iopmp_gpu: IOPMP_GPU {
+			is_default_region;
+		};
+
+		iopmp_gmac1: IOPMP_GMAC1 {
+			is_default_region;
+		};
+
+		iopmp_gmac2: IOPMP_GMAC2 {
+			is_default_region;
+		};
+
+		iopmp_dmac: IOPMP_DMAC {
+			is_default_region;
+		};
+
+		iopmp_tee_dmac: IOPMP_TEE_DMAC {
+			is_default_region;
+		};
+
+		iopmp_dsp0: IOPMP_DSP0 {
+			is_default_region;
+		};
+
+		iopmp_dsp1: IOPMP_DSP1 {
+			is_default_region;
+		};
+	};
+
+	mbox_910t_client1: mbox_910t_client1 {
+		compatible = "thead,light-mbox-client";
+		mbox-names = "902";
+		mboxes = <&mbox_910t 1 0>;
+		status = "disabled";
+	};
+
+
+	mbox_910t_client2: mbox_910t_client2 {
+		compatible = "thead,light-mbox-client";
+		mbox-names = "906";
+		mboxes = <&mbox_910t 2 0>;
+		status = "disabled";
+	};
+
+	lightsound: lightsound@1 {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "Light-Sound-Card";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+	};
+
+	dummy_codec: dummy_codec {
+		#sound-dai-cells = <1>;
+		compatible = "linux,bt-sco";
+		status = "okay";
+	};
+
+	reg_vref_1v8: regulator-adc-verf {
+			compatible = "regulator-fixed";
+			regulator-name = "vref-1v8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+	status = "okay";
+	};
+
+        reg_tp_pwr_en: regulator-pwr-en {
+                compatible = "regulator-fixed";
+                regulator-name = "PWR_EN";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                gpio = <&gpio1_porta 12 1>;
+                enable-active-high;
+                regulator-always-on;
+        };
+
+	wcn_wifi: wireless-wlan {
+		compatible = "wlan-platdata";
+		clock-names = "clk_wifi";
+		ref-clock-frequency = <24000000>;
+		keep_wifi_power_on;
+		pinctrl-names = "default";
+		wifi_chip_type = "rtl8723ds";
+		WIFI,poweren_gpio = <&gpio2_porta 29 0>;
+		WIFI,reset_n = <&gpio2_porta 24 0>;
+		status = "okay";
+	};
+
+	wcn_bt: wireless-bluetooth {
+		compatible = "bluetooth-platdata";
+		pinctrl-names = "default", "rts_gpio";
+		BT,power_gpio    = <&gpio2_porta 25 0>;
+		status = "okay";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&pinctrl_volume>;
+		pinctrl-names = "default";
+		key-volumedown {
+			label = "Volume Down Key";
+			linux,code = <KEY_VOLUMEDOWN>;
+			debounce-interval = <1>;
+			gpios = <&ao_gpio_porta 11 0x1>;
+		};
+		key-volumeup {
+			label = "Volume Up Key";
+			linux,code = <KEY_VOLUMEUP>;
+			debounce-interval = <1>;
+			gpios = <&ao_gpio_porta 10 0x1>;
+		};
+	};
+
+	aon: light-aon {
+		compatible = "thead,light-aon";
+		mbox-names = "aon";
+		mboxes = <&mbox_910t 1 0>;
+		status = "okay";
+
+		pd: light-aon-pd {
+			compatible = "thead,light-aon-pd";
+			#power-domain-cells = <1>;
+		};
+
+		c910_cpufreq {
+			compatible = "thead,light-mpw-cpufreq";
+			status = "okay";
+		};
+
+		test: light-aon-test {
+			compatible = "thead,light-aon-test";
+		};
+	};
+};
+
+&resmem {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	ranges;
+
+	tee_mem: memory@1a000000 {
+		reg = <0x0 0x1a000000 0 0x4000000>;
+		no-map;
+	};
+
+	dsp0_mem: memory@20000000 {             /**0x2000_0000~0x2040_0000 4M**/
+		reg = <0x0 0x20000000 0x0 0x00280000   /* DSP FW code&data section 2.5M*/ 
+               0x0 0x20280000 0x0 0x00001000   /* DSP communication area 4K*/ 
+               0x0 0x20281000 0x0 0x00007000  /* Panic/log page 28K */
+               0x0 0x20288000 0x0 0x00178000>;  /* DSP shared memory 1.5M-32K*/
+		no-map;
+	};
+    dsp1_mem: memory@20400000 {             /**0x2040_0000~0x2080_0000 4M**/
+        reg = <0x0 0x20400000 0x0 0x00280000  /* DSP FW code&data section */ 
+               0x0 0x20680000 0x0 0x00001000 /* DSP communication area */
+               0x0 0x20681000 0x0 0x00007000    /* Panic/log page*/ 
+               0x0 0x20688000 0x0 0x00178000>;  /* DSP shared memory */
+        no-map;
+    };
+	vi_mem: framebuffer@10000000 {
+		reg = <0x0 0x10000000 0x0 0x02C00000	/* vi_mem_pool_region[0]  44 MB (default) */
+		       0x0 0x12C00000 0x0 0x01D00000	/* vi_mem_pool_region[1]  29 MB */
+		       0x0 0x14900000 0x0 0x01E00000>;	/* vi_mem_pool_region[2]  30 MB */
+		no-map;
+	};
+	facelib_mem: memory@17000000 {
+		reg = <0x0 0x17000000 0 0x02000000>;
+		no-map;
+	};
+};
+
+&adc {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <100000>;
+	status = "okay";
+
+       touch@5d {
+               #gpio-cells = <2>;
+               compatible = "goodix,gt911";
+               reg = <0x5d>;
+               interrupt-parent = <&gpio1_porta>;
+               interrupts = <8 0>;
+               irq-gpios = <&gpio1_porta 8 0>;
+               reset-gpios = <&gpio1_porta 7 0>;
+               AVDD28-supply = <&reg_tp_pwr_en>;
+               touchscreen-size-x = <720>;
+               touchscreen-size-y = <1280>;
+       };
+
+};
+
+&audio_i2c0 {
+        clock-frequency = <100000>;
+        status = "okay";
+
+       es8156_audio_codec: es8156@8 {
+               #sound-dai-cells = <0>;
+               compatible = "everest,es8156";
+               reg = <0x08>;
+       };
+
+        es7210_audio_codec: es7210@40 {
+                #sound-dai-cells = <0>;
+                compatible = "MicArray_0";
+                reg = <0x40>;
+        };
+
+	audio_aw87519_pa@58 {
+		compatible = "awinic,aw87519_pa";
+		reg = <0x58>;
+		reset-gpio = <&ao_gpio4_porta 9 0x1>;
+		status = "okay";
+	};
+};
+
+&i2c1 {
+        clock-frequency = <100000>;
+        status = "okay";
+};
+
+&spi0 {
+	num-cs = <1>;
+	cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
+	rx-sample-delay-ns = <10>;
+	status = "disabled";
+
+	spi_norflash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q64jwm", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		w25q,fast-read;
+	};
+
+	spidev@1 {
+		compatible = "spidev";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		reg = <0x1>;
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&uart0 {
+	clocks = <&dummy_clock_uart_sclk>;
+	clock-names = "baudclk";
+	clock-frequency = <100000000>;
+};
+
+&qspi0 {
+	num-cs = <1>;
+	cs-gpios = <&gpio2_porta 3 0>;
+	rx-sample-dly = <4>;
+	status = "disabled";
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		spi-max-frequency = <100000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		reg = <0>;
+
+		partition@0 {
+			label = "ubi1";
+			reg = <0x00000000 0x08000000>;
+		};
+	};
+};
+
+&qspi1 {
+	compatible = "snps,dw-apb-ssi";
+	num-cs = <1>;
+	cs-gpios = <&gpio0_porta 1 0>;
+	status = "disabled";
+
+	spidev@0 {
+		compatible = "spidev";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		reg = <0x0>;
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&gmac0 {
+	phy-mode = "rgmii-id";
+	rx-clk-delay = <0x00>; /* for RGMII */
+	tx-clk-delay = <0x00>; /* for RGMII */
+	phy-handle = <&phy_88E1111_0>;
+	status = "okay";
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+
+		phy_88E1111_0: ethernet-phy@0 {
+			reg = <0x1>;
+		};
+
+		phy_88E1111_1: ethernet-phy@1 {
+			reg = <0x2>;
+		};
+	};
+};
+
+&gmac1 {
+	phy-mode = "rgmii-id";
+	rx-clk-delay = <0x00>; /* for RGMII */
+	tx-clk-delay = <0x00>; /* for RGMII */
+	phy-handle = <&phy_88E1111_1>;
+	status = "okay";
+};
+
+&emmc {
+	max-frequency = <198000000>;
+	non-removable;
+	mmc-hs400-1_8v;
+	io_fixed_1v8;
+	is_emmc;
+	no-sdio;
+	no-sd;
+	pull_up;
+	bus-width = <8>;
+	status = "okay";
+};
+
+&sdhci0 {
+	max-frequency = <198000000>;
+	bus-width = <4>;
+	pull_up;
+	wprtn_ignore;
+	status = "okay";
+};
+
+&sdhci1 {
+	max-frequency = <100000000>;
+	bus-width = <4>;
+	pull_up;
+	no-sd;
+	no-mmc;
+	non-removable;
+	io_fixed_1v8;
+	post-power-on-delay-ms = <50>;
+	wprtn_ignore;
+	cap-sd-highspeed;
+	keep-power-in-suspend;
+	wakeup-source;
+	status = "okay";
+};
+
+&padctrl0_apsys { /* right-pinctrl */
+	light-evb-padctrl0 {
+			/*
+			 * Pin Configuration Node:
+			 * Format: <pin_id mux_node config>
+			 */
+			pinctrl_uart0: uart0grp {
+				thead,pins = <
+					FM_UART0_TXD	0x0	0x72
+					FM_UART0_RXD	0x0	0x72
+				>;
+			};
+
+			pinctrl_spi0: spi0grp {
+				thead,pins = <
+					FM_SPI_CSN	0x3	0x20a
+					FM_SPI_SCLK	0x0	0x20a
+					FM_SPI_MISO	0x0	0x23a
+					FM_SPI_MOSI	0x0	0x23a
+				>;
+			};
+
+			pinctrl_qspi0: qspi0grp {
+				thead,pins = <
+					FM_QSPI0_SCLK    0x0    0x20f
+					FM_QSPI0_CSN0    0x3    0x20f
+					FM_QSPI0_CSN1    0x0    0x20f
+					FM_QSPI0_D0_MOSI 0x0    0x23f
+					FM_QSPI0_D1_MISO 0x0    0x23f
+					FM_QSPI0_D2_WP   0x0    0x23f
+					FM_QSPI0_D3_HOLD 0x0    0x23f
+				>;
+			};
+
+			pinctrl_audio_i2s0: i2s0grp {
+				thead,pins = <
+					FM_QSPI0_SCLK    0x2    0x208
+					FM_QSPI0_CSN0    0x2    0x238
+					FM_QSPI0_CSN1    0x2    0x208
+					FM_QSPI0_D0_MOSI 0x2    0x238
+					FM_QSPI0_D1_MISO 0x2    0x238
+					FM_QSPI0_D2_WP   0x2    0x238
+					FM_QSPI0_D3_HOLD 0x2    0x238
+				>;
+			};
+
+			pinctrl_pwm: pwmgrp {
+				thead,pins = <
+					FM_GPIO3_2	0x1	0x208	/* pwm0 */
+				>;
+			};
+		};
+};
+
+&padctrl1_apsys { /* left-pinctrl */
+	light-evb-padctrl1 {
+			/*
+			 * Pin Configuration Node:
+			 * Format: <pin_id mux_node config>
+			 */
+			pinctrl_uart3: uart3grp {
+				thead,pins = <
+					FM_UART3_TXD	0x0	0x72
+					FM_UART3_RXD	0x0	0x72
+				>;
+			};
+
+			pinctrl_uart4: uart4grp {
+				thead,pins = <
+					FM_UART4_TXD	0x0	0x72
+					FM_UART4_RXD	0x0	0x72
+					FM_UART4_CTSN	0x0	0x72
+					FM_UART4_RTSN	0x0	0x72
+				>;
+			};
+
+			pinctrl_qspi1: qspi1grp {
+				thead,pins = <
+					FM_QSPI1_SCLK    0x0    0x20a
+					FM_QSPI1_CSN0    0x3    0x20a
+					FM_QSPI1_D0_MOSI 0x0    0x23a
+					FM_QSPI1_D1_MISO 0x0    0x23a
+					FM_QSPI1_D2_WP   0x0    0x23a
+					FM_QSPI1_D3_HOLD 0x0    0x23a
+				>;
+			};
+
+
+			pinctrl_iso7816: iso7816grp {
+				thead,pins = <
+					FM_QSPI1_SCLK		0x1	0x208
+					FM_QSPI1_D0_MOSI	0x1	0x238
+					FM_QSPI1_D1_MISO	0x1	0x238
+					FM_QSPI1_D2_WP		0x1	0x238
+					FM_QSPI1_D3_HOLD	0x1	0x238
+				>;
+			};
+
+		};
+};
+
+&padctrl_aosys {
+	light-aon-padctrl {
+			/*
+			 * Pin Configuration Node:
+			 * Format: <pin_id mux_node config>
+			 */
+
+			pinctrl_audiopa1: audiopa1_grp {
+				thead,pins = <
+					FM_AUDIO_PA1	0x3	0x72
+				>;
+			};
+
+			pinctrl_audiopa2: audiopa2_grp {
+				thead,pins = <
+					FM_AUDIO_PA2	0x0	0x72
+				>;
+			};
+
+			pinctrl_volume: volume_grp {
+				thead,pins = <
+					FM_AOGPIO_11  0x0     0x208
+					FM_AOGPIO_10  0x3     0x208
+				>;
+			};
+	};
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&isp0 {
+	status = "disabled";
+};
+
+&isp1 {
+	status = "disabled";
+};
+
+&isp_ry0 {
+	status = "disabled";
+};
+
+&dewarp {
+	status = "disabled";
+};
+
+&dec400_isp0 {
+	status = "disabled";
+};
+
+&dec400_isp1 {
+	status = "disabled";
+};
+
+&dec400_isp2 {
+	status = "disabled";
+};
+
+&bm_visys {
+	status = "disabled";
+};
+
+&bm_csi0 {
+	status = "disabled";
+};
+
+&bm_csi1 {
+	status = "disabled";
+};
+
+&bm_csi2 {
+	status = "disabled";
+};
+
+&vi_pre {
+	status = "disabled";
+};
+
+&xtensa_dsp {
+	status = "disabled";
+};
+
+&xtensa_dsp0 {
+	status = "disabled";
+};
+
+&xtensa_dsp1 {
+	status = "disabled";
+};
+
+&vvcam_flash_led0{
+       status = "disabled";
+};
+
+
+&vvcam_sensor0 {
+	status = "disabled";
+};
+
+&vvcam_sensor1 {
+	status = "disabled";
+};
+
+&vvcam_sensor2 {
+	status = "disabled";
+};
+
+&vvcam_sensor3 {
+	status = "disabled";
+};
+
+&vvcam_sensor4 {
+    status = "disabled";
+};
+
+&vvcam_sensor5 {
+    status = "disabled";
+};
+
+&video0{
+	status = "disabled";
+};
+
+
+&video1{
+	status = "disabled";
+};
+
+&video2{
+	status = "disabled";
+};
+
+&video3{
+	status = "disabled";
+};
+
+&video4{
+	status = "disabled";
+};
+
+&video5{
+	status = "disabled";
+};
+
+&video6{
+	status = "disabled";
+};
+
+&video7{
+	status = "disabled";
+};
+
+
+&video8{
+	status = "disabled";
+};
+
+&video9{
+	status = "disabled";
+};
+
+
+&video10{
+	status = "disabled";
+};
+
+&video11{
+	status = "disabled";
+};
+
+&video12{
+	status = "disabled";
+};
+
+&trng {
+	status = "disabled";
+};
+
+&eip_28 {
+	status = "disabled";
+};
+
+&vdec {
+	status = "disabled";
+};
+
+&venc {
+	status = "disabled";
+};
+
+&isp_venc_shake {
+	status = "disabled";
+};
+
+&vidmem {
+	status = "disabled";
+};
+
+&gpu {
+	status = "disabled";
+};
+
+&dpu_enc0 {
+	status = "disabled";
+};
+
+&dpu_enc1 {
+	status = "disabled";
+};
+
+&dpu {
+        status = "disabled";
+};
+
+&dsi0 {
+        status = "disabled";
+};
+
+&dhost_0 {
+	status = "disabled";
+};
+
+&disp1_out {
+	status = "disabled";
+};
+
+&hdmi_tx {
+	status = "disabled";
+};
+
+&lightsound {
+        status = "disabled";
+};
+
+&light_i2s {
+        status = "okay";
+};
+
+&i2s0 {
+        status = "okay";
+};
+
+&i2s1 {
+        status = "okay";
+};
+
+&i2s3 {
+        status = "okay";
+};
+
+&khvhost {
+	status = "disabled";
+};

+ 98 - 0
arch/riscv/boot/dts/thead/fire-emu-crash.dts

@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+#include "fire-crash.dts"
+
+&aon {
+	aon_reg_dialog: light-dialog-reg {
+		compatible = "thead,light-dialog-pmic";
+		status = "okay";
+
+		dvdd_cpu_reg: appcpu_dvdd {
+			regulator-name = "appcpu_dvdd";
+			regulator-min-microvolt = <600000>;
+			regulator-max-microvolt = <1500000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dvddm_cpu_reg: appcpu_dvddm {
+			regulator-name = "appcpu_dvddm";
+			regulator-min-microvolt = <600000>;
+			regulator-max-microvolt = <1500000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+	};
+};
+
+&cpus {
+	c910_0: cpu@0 {
+		operating-points = <
+			/* kHz    uV */
+			300000	600000
+			800000	700000
+			1500000	800000
+			1848000 1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000 1000000
+		>;
+	};
+	c910_1: cpu@1 {
+		operating-points = <
+			/* kHz    uV */
+			300000	600000
+			800000	700000
+			1500000	800000
+			1848000 1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000 1000000
+		>;
+	};
+	c910_2: cpu@2 {
+
+		operating-points = <
+			/* kHz    uV */
+			300000	600000
+			800000	700000
+			1500000	800000
+			1848000 1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000 1000000
+		>;
+	};
+	c910_3: cpu@3 {
+
+		operating-points = <
+			/* kHz    uV */
+			300000	600000
+			800000	700000
+			1500000	800000
+			1848000 1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000 1000000
+		>;
+	};
+};

+ 2192 - 0
arch/riscv/boot/dts/thead/fire-emu.dts

@@ -0,0 +1,2192 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021-2022 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "fire.dtsi"
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "light-vi-devices.dtsi"
+
+/ {
+	model = "T-HEAD fire fpga board";
+	compatible = "thead,fire-emu", "thead,fire";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000";
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0 {
+			label = "SYS_STATUS";
+			gpios = <&gpio1_porta 15 0>;	/* GPIO_ACTIVE_HIGH: 0 */
+			default-state = "off";
+		};
+	};
+
+	lcd0_backlight: pwm-backlight@0 {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <7>;
+	};
+
+	lcd1_backlight: pwm-backlight@1 {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 1 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <7>;
+	};
+
+	light_iopmp: iopmp {
+		compatible = "thead,light-iopmp";
+
+		/* config#1: multiple valid regions */
+		iopmp_emmc: IOPMP_EMMC {
+			regions = <0x000000 0x100000>,
+				  <0x100000 0x200000>;
+			attr = <0xFFFFFFFF>;
+			dummy_slave= <0x800000>;
+		};
+
+		/* config#2: iopmp bypass */
+		iopmp_sdio0: IOPMP_SDIO0 {
+			bypass_en;
+		};
+
+		/* config#3: iopmp default region set */
+		iopmp_sdio1: IOPMP_SDIO1 {
+			attr = <0xFFFFFFFF>;
+			is_default_region;
+		};
+
+		iopmp_usb0: IOPMP_USB0 {
+			attr = <0xFFFFFFFF>;
+			is_default_region;
+		};
+
+		iopmp_ao: IOPMP_AO {
+			is_default_region;
+		};
+
+		iopmp_aud: IOPMP_AUD {
+			is_default_region;
+		};
+
+		iopmp_chip_dbg: IOPMP_CHIP_DBG {
+			is_default_region;
+		};
+
+		iopmp_eip120i: IOPMP_EIP120I {
+			is_default_region;
+		};
+
+		iopmp_eip120ii: IOPMP_EIP120II {
+			is_default_region;
+		};
+
+		iopmp_eip120iii: IOPMP_EIP120III {
+			is_default_region;
+		};
+
+		iopmp_isp0: IOPMP_ISP0 {
+			is_default_region;
+		};
+
+		iopmp_isp1: IOPMP_ISP1 {
+			is_default_region;
+		};
+
+		iopmp_dw200: IOPMP_DW200 {
+			is_default_region;
+		};
+
+		iopmp_vipre: IOPMP_VIPRE {
+			is_default_region;
+		};
+
+		iopmp_venc: IOPMP_VENC {
+			is_default_region;
+		};
+
+		iopmp_vdec: IOPMP_VDEC {
+			is_default_region;
+		};
+
+		iopmp_g2d: IOPMP_G2D {
+			is_default_region;
+		};
+
+		iopmp0_dpu: IOPMP0_DPU {
+			bypass_en;
+		};
+
+		iopmp1_dpu: IOPMP1_DPU {
+			bypass_en;
+		};
+
+		iopmp_gpu: IOPMP_GPU {
+			is_default_region;
+		};
+
+		iopmp_gmac1: IOPMP_GMAC1 {
+			is_default_region;
+		};
+
+		iopmp_gmac2: IOPMP_GMAC2 {
+			is_default_region;
+		};
+
+		iopmp_dmac: IOPMP_DMAC {
+			is_default_region;
+		};
+
+		iopmp_tee_dmac: IOPMP_TEE_DMAC {
+			is_default_region;
+		};
+
+		iopmp_dsp0: IOPMP_DSP0 {
+			is_default_region;
+		};
+
+		iopmp_dsp1: IOPMP_DSP1 {
+			is_default_region;
+		};
+	};
+
+	mbox_910t_client1: mbox_910t_client1 {
+		compatible = "thead,light-mbox-client";
+		mbox-names = "902";
+		mboxes = <&mbox_910t 1 0>;
+		status = "disabled";
+	};
+
+
+	mbox_910t_client2: mbox_910t_client2 {
+		compatible = "thead,light-mbox-client";
+		mbox-names = "906";
+		mboxes = <&mbox_910t 2 0>;
+		status = "disabled";
+	};
+
+	lightsound: lightsound@1 {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "Light-Sound-Card";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+	};
+
+	dummy_codec: dummy_codec {
+		#sound-dai-cells = <1>;
+		compatible = "linux,bt-sco";
+		status = "okay";
+	};
+
+	reg_vref_1v8: regulator-adc-verf {
+			compatible = "regulator-fixed";
+			regulator-name = "vref-1v8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+	status = "okay";
+	};
+
+		reg_tp_pwr_en: regulator-pwr-en {
+                compatible = "regulator-fixed";
+                regulator-name = "PWR_EN";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                gpio = <&pcal6408ahk_a 3 1>;
+                enable-active-high;
+                regulator-always-on;
+        };
+
+        reg_tp1_pwr_en: regulator-tp1-pwr-en {
+                compatible = "regulator-fixed";
+                regulator-name = "PWR_EN";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                gpio = <&pcal6408ahk_a 6 1>;
+                enable-active-high;
+                regulator-always-on;
+        };
+
+	lcd0_1v8: regulator-lcd0-vdd18 {
+		compatible = "regulator-fixed";
+		regulator-name = "lcd0_en";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&pcal6408ahk_a 2 0>;
+		enable-active-high;
+	};
+
+	lcd0_5v7: regulator-lcd0-vspn57 {
+		compatible = "regulator-fixed";
+		regulator-name = "lcd0_bias_en";
+		regulator-min-microvolt = <5700000>;
+		regulator-max-microvolt = <5700000>;
+		gpio = <&pcal6408ahk_a 4 0>;
+		enable-active-high;
+	};
+
+	lcd1_1v8: regulator-lcd1-vdd18 {
+		compatible = "regulator-fixed";
+		regulator-name = "lcd1_en";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&pcal6408ahk_a 5 0>;
+		enable-active-high;
+	};
+
+	lcd1_5v7: regulator-lcd1-vspn57 {
+		compatible = "regulator-fixed";
+		regulator-name = "lcd1_bias_en";
+		regulator-min-microvolt = <5700000>;
+		regulator-max-microvolt = <5700000>;
+		gpio = <&pcal6408ahk_a 7 0>;
+		enable-active-high;
+	};
+
+	wcn_wifi: wireless-wlan {
+		compatible = "wlan-platdata";
+		clock-names = "clk_wifi";
+		ref-clock-frequency = <24000000>;
+		keep_wifi_power_on;
+		pinctrl-names = "default";
+		wifi_chip_type = "rtl8723ds";
+		WIFI,poweren_gpio = <&gpio2_porta 26 0>;
+		WIFI,reset_n = <&gpio2_porta 28 0>;
+		status = "disabled";
+	};
+
+	wcn_bt: wireless-bluetooth {
+		compatible = "bluetooth-platdata";
+		pinctrl-names = "default", "rts_gpio";
+		BT,power_gpio    = <&gpio2_porta 29 0>;
+		status = "disabled";
+	};
+
+	gpio_keys: gpio_keys{
+		compatible = "gpio-keys";
+		pinctrl-0 = <&pinctrl_volume>;
+		pinctrl-names = "default";
+		status = "disabled";
+		key-volumedown {
+			label = "Volume Down Key";
+			linux,code = <KEY_1>;
+			debounce-interval = <2>;
+			gpios = <&ao_gpio_porta 4 GPIO_ACTIVE_LOW>;
+		};
+		key-volumeup {
+			label = "Volume Up Key";
+			linux,code = <KEY_2>;
+			debounce-interval = <2>;
+			gpios = <&ao_gpio_porta 5 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	aon {
+		compatible = "thead,light-aon";
+		mbox-names = "aon";
+		mboxes = <&mbox_910t 1 0>;
+		status = "okay";
+
+		pd: light-aon-pd {
+			compatible = "thead,light-aon-pd";
+			#power-domain-cells = <1>;
+		};
+
+		aon_reg_dialog: light-dialog-reg {
+			compatible = "thead,light-dialog-pmic";
+			status = "disabled";
+
+			dvdd_cpu_reg: appcpu_dvdd {
+				regulator-name = "appcpu_dvdd";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1570000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			dvddm_cpu_reg: appcpu_dvddm {
+				regulator-name = "appcpu_dvddm";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1570000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dvdd18_aon_reg: soc_dvdd18_aon {
+				regulator-name = "soc_dvdd18_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
+				regulator-name = "soc_avdd33_usb3";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_aon_reg: soc_dvdd08_aon {
+				regulator-name = "soc_dvdd08_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
+				regulator-name = "soc_dvdd08_ddr";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
+				regulator-name = "soc_vdd_ddr_1v8";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
+				regulator-name = "soc_vdd_ddr_1v1";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
+				regulator-name = "soc_vdd_ddr_0v6";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_ap_reg: soc_dvdd18_ap {
+				regulator-name = "soc_dvdd18_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
+				regulator-name = "soc_avdd08_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
+				regulator-name = "soc_avdd18_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd33_emmc_reg: soc_vdd33_emmc {
+				regulator-name = "soc_vdd33_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd18_emmc_reg: soc_vdd18_emmc {
+				regulator-name = "soc_vdd18_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_scan_reg: soc_dovdd18_scan {
+				regulator-name = "soc_dovdd18_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+			soc_vext_2v8_reg: soc_vext_2v8 {
+				regulator-name = "soc_vext_2v8";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dvdd12_scan_reg: soc_dvdd12_scan {
+				regulator-name = "soc_dvdd12_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
+				regulator-name = "soc_avdd28_scan_en";
+			};
+			soc_avdd28_rgb_reg: soc_avdd28_rgb {
+				regulator-name = "soc_avdd28_rgb";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
+				regulator-name = "soc_dovdd18_rgb";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
+				regulator-name = "soc_dvdd12_rgb";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_avdd25_ir_reg: soc_avdd25_ir {
+				regulator-name = "soc_avdd25_ir";
+				regulator-min-microvolt = <2200000>;
+				regulator-max-microvolt = <3475000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dovdd18_ir_reg: soc_dovdd18_ir {
+				regulator-name = "soc_dovdd18_ir";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			soc_dvdd12_ir_reg: soc_dvdd12_ir {
+				regulator-name = "soc_dvdd12_ir";
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1675000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+		};
+
+		c910_cpufreq {
+			compatible = "thead,light-mpw-cpufreq";
+			status = "disabled";
+		};
+
+		test: light-aon-test {
+			compatible = "thead,light-aon-test";
+		};
+	};
+};
+
+&cmamem {
+	alloc-ranges = <0 0xe4000000 0 0x14000000>; // [0xE400_0000 ~ 0xF800_0000]
+};
+
+&resmem {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	ranges;
+
+	tee_mem: memory@1a000000 {
+		reg = <0x0 0x1a000000 0 0x4000000>;
+		no-map;
+	};
+	dsp0_mem: memory@20000000 {			/**0x2000_0000~0x2040_0000 4M**/
+		reg = <0x0 0x20000000 0x0 0x00280000	/* DSP FW code&data section 2.5M*/
+		       0x0 0x20280000 0x0 0x00001000	/* DSP communication area 4K*/
+		       0x0 0x20281000 0x0 0x00007000	/* Panic/log page 28K */
+		       0x0 0x20288000 0x0 0x00178000>;	/* DSP shared memory 1.5M-32K*/
+		no-map;
+	};
+	dsp1_mem: memory@20400000 {			/**0x2040_0000~0x2080_0000 4M**/
+		reg = <0x0 0x20400000 0x0 0x00280000	/* DSP FW code&data section */
+		       0x0 0x20680000 0x0 0x00001000	/* DSP communication area */
+		       0x0 0x20681000 0x0 0x00007000	/* Panic/log page*/
+		       0x0 0x20688000 0x0 0x00178000>;	/* DSP shared memory */
+		no-map;
+	};
+    vi_mem: framebuffer@0f800000 {
+		reg = <0x0 0x0F800000 0x0 0x05400000	/* vi_mem_pool_region[0]  84 MB (default) */
+		       0x0 0x14C00000 0x0 0x01D00000	/* vi_mem_pool_region[1]  29 MB */
+		       0x0 0x16900000 0x0 0x03200000>;	/* vi_mem_pool_region[2]  50 MB */
+		no-map;
+	};
+	facelib_mem: memory@22000000 {
+		reg = <0x0 0x22000000 0x0 0x10000000>;
+		no-map;
+	};
+
+};
+
+&clk {
+	status = "disabled";
+};
+
+&adc {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+
+	codec: wm8960@1a {
+		#sound-dai-cells = <0>;
+		compatible = "wlf,wm8960";
+		reg = <0x1a>;
+		wlf,shared-lrclk;
+		wlf,hp-cfg = <3 2 3>;
+		wlf,gpio-cfg = <1 3>;
+	};
+
+       touch@5d {
+               #gpio-cells = <2>;
+               compatible = "goodix,gt911";
+               reg = <0x5d>;
+               interrupt-parent = <&gpio1_porta>;
+               interrupts = <8 0>;
+               irq-gpios = <&gpio1_porta 8 0>;
+               reset-gpios = <&gpio1_porta 7 0>;
+               AVDD28-supply = <&reg_tp_pwr_en>;
+               touchscreen-size-x = <720>;
+               touchscreen-size-y = <1280>;
+       };
+};
+
+&audio_i2c0 {
+        clock-frequency = <100000>;
+        status = "okay";
+
+       es8156_audio_codec: es8156@8 {
+               #sound-dai-cells = <0>;
+               compatible = "everest,es8156";
+               reg = <0x08>;
+       };
+
+        es7210_audio_codec: es7210@40 {
+                #sound-dai-cells = <0>;
+                compatible = "MicArray_0";
+                reg = <0x40>;
+        };
+};
+
+&i2c1 {
+        clock-frequency = <400000>;
+        status = "okay";
+        touch1@5d {
+                #gpio-cells = <2>;
+                compatible = "goodix,gt911";
+                reg = <0x5d>;
+                interrupt-parent = <&gpio1_porta>;
+                interrupts = <12 0>;
+                irq-gpios = <&gpio1_porta 12 0>;
+                reset-gpios = <&gpio1_porta 11 0>;
+                AVDD28-supply = <&reg_tp1_pwr_en>;
+                touchscreen-size-x = <720>;
+                touchscreen-size-y = <1280>;
+        };
+};
+
+&spi0 {
+	num-cs = <1>;
+	cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
+	rx-sample-delay-ns = <10>;
+	status = "okay";
+
+	spi_norflash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q64jwm", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		w25q,fast-read;
+		status = "disabled";
+	};
+
+	spidev@1 {
+		compatible = "spidev";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		reg = <0x1>;
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&uart0 {
+	clock-frequency = <100000000>;
+};
+
+&qspi0 {
+	num-cs = <1>;
+	cs-gpios = <&gpio2_porta 3 0>;
+	rx-sample-dly = <4>;
+	status = "disabled";
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		spi-max-frequency = <100000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		reg = <0>;
+
+		partition@0 {
+			label = "ubi1";
+			reg = <0x00000000 0x08000000>;
+		};
+	};
+};
+
+&qspi1 {
+	num-cs = <1>;
+	cs-gpios = <&gpio0_porta 1 0>;
+	status = "disabled";
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		spi-max-frequency = <66000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		reg = <0>;
+
+		partition@0 {
+			label = "ubi2";
+			reg = <0x00000000 0x08000000>;
+		};
+	};
+};
+
+&gmac0 {
+	phy-mode = "rgmii-id";
+	rx-clk-delay = <0x00>; /* for RGMII */
+	tx-clk-delay = <0x00>; /* for RGMII */
+	phy-handle = <&phy_88E1111_0>;
+	status = "okay";
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+
+		phy_88E1111_0: ethernet-phy@0 {
+			reg = <0x1>;
+		};
+
+		phy_88E1111_1: ethernet-phy@1 {
+			reg = <0x2>;
+		};
+	};
+};
+
+&gmac1 {
+	phy-mode = "rgmii-id";
+	rx-clk-delay = <0x00>; /* for RGMII */
+	tx-clk-delay = <0x00>; /* for RGMII */
+	phy-handle = <&phy_88E1111_1>;
+	status = "okay";
+};
+
+&emmc {
+	max-frequency = <198000000>;
+	non-removable;
+	mmc-hs400-1_8v;
+	io_fixed_1v8;
+	is_emmc;
+	no-sdio;
+	no-sd;
+	pull_up;
+	bus-width = <8>;
+	status = "okay";
+};
+
+&sdhci0 {
+	max-frequency = <198000000>;
+	bus-width = <4>;
+	pull_up;
+	wprtn_ignore;
+	status = "okay";
+};
+
+&sdhci1 {
+	max-frequency = <100000000>;
+	bus-width = <4>;
+	pull_up;
+	no-sd;
+	no-mmc;
+	non-removable;
+	io_fixed_1v8;
+	post-power-on-delay-ms = <50>;
+	wprtn_ignore;
+	cap-sd-highspeed;
+	keep-power-in-suspend;
+	wakeup-source;
+	status = "disabled";
+};
+
+&padctrl0_apsys { /* right-pinctrl */
+	light-evb-padctrl0 {
+			/*
+			 * Pin Configuration Node:
+			 * Format: <pin_id mux_node config>
+			 */
+			pinctrl_uart0: uart0grp {
+				thead,pins = <
+					FM_UART0_TXD	0x0	0x72
+					FM_UART0_RXD	0x0	0x72
+				>;
+			};
+
+			pinctrl_spi0: spi0grp {
+				thead,pins = <
+					FM_SPI_CSN	0x3	0x20a
+					FM_SPI_SCLK	0x0	0x20a
+					FM_SPI_MISO	0x0	0x23a
+					FM_SPI_MOSI	0x0	0x23a
+				>;
+			};
+
+			pinctrl_qspi0: qspi0grp {
+				thead,pins = <
+					FM_QSPI0_SCLK    0x0    0x20f
+					FM_QSPI0_CSN0    0x3    0x20f
+					FM_QSPI0_CSN1    0x0    0x20f
+					FM_QSPI0_D0_MOSI 0x0    0x23f
+					FM_QSPI0_D1_MISO 0x0    0x23f
+					FM_QSPI0_D2_WP   0x0    0x23f
+					FM_QSPI0_D3_HOLD 0x0    0x23f
+				>;
+			};
+
+			pinctrl_audio_i2s0: i2s0grp {
+				thead,pins = <
+					FM_QSPI0_SCLK    0x2    0x208
+					FM_QSPI0_CSN0    0x2    0x238
+					FM_QSPI0_CSN1    0x2    0x208
+					FM_QSPI0_D0_MOSI 0x2    0x238
+					FM_QSPI0_D1_MISO 0x2    0x238
+					FM_QSPI0_D2_WP   0x2    0x238
+					FM_QSPI0_D3_HOLD 0x2    0x238
+				>;
+			};
+
+			pinctrl_pwm: pwmgrp {
+				thead,pins = <
+					FM_GPIO3_2	0x1	0x208	/* pwm0 */
+					FM_GPIO3_3	0x1	0x208	/* pwm1 */
+				>;
+			};
+		};
+};
+
+&padctrl1_apsys { /* left-pinctrl */
+	light-evb-padctrl1 {
+			/*
+			 * Pin Configuration Node:
+			 * Format: <pin_id mux_node config>
+			 */
+			pinctrl_uart3: uart3grp {
+				thead,pins = <
+					FM_UART3_TXD	0x0	0x72
+					FM_UART3_RXD	0x0	0x72
+				>;
+			};
+
+			pinctrl_uart4: uart4grp {
+				thead,pins = <
+					FM_UART4_TXD	0x0	0x72
+					FM_UART4_RXD	0x0	0x72
+					FM_UART4_CTSN	0x0	0x72
+					FM_UART4_RTSN	0x0	0x72
+				>;
+			};
+
+			pinctrl_qspi1: qspi1grp {
+				thead,pins = <
+					FM_QSPI1_SCLK    0x0    0x20a
+					FM_QSPI1_CSN0    0x3    0x20a
+					FM_QSPI1_D0_MOSI 0x0    0x23a
+					FM_QSPI1_D1_MISO 0x0    0x23a
+					FM_QSPI1_D2_WP   0x0    0x23a
+					FM_QSPI1_D3_HOLD 0x0    0x23a
+				>;
+			};
+
+
+			pinctrl_iso7816: iso7816grp {
+				thead,pins = <
+					FM_QSPI1_SCLK		0x1	0x208
+					FM_QSPI1_D0_MOSI	0x1	0x238
+					FM_QSPI1_D1_MISO	0x1	0x238
+					FM_QSPI1_D2_WP		0x1	0x238
+					FM_QSPI1_D3_HOLD	0x1	0x238
+				>;
+			};
+
+		};
+};
+
+&padctrl_aosys {
+	light-aon-padctrl {
+			/*
+			 * Pin Configuration Node:
+			 * Format: <pin_id mux_node config>
+			 */
+
+			pinctrl_audiopa1: audiopa1_grp {
+				thead,pins = <
+					FM_AUDIO_PA1	0x3	0x72
+				>;
+			};
+
+			pinctrl_audiopa2: audiopa2_grp {
+				thead,pins = <
+					FM_AUDIO_PA2	0x0	0x72
+				>;
+			};
+
+			pinctrl_volume: volume_grp {
+				thead,pins = <
+					FM_CPU_JTG_TDI  0x3     0x208
+					FM_CPU_JTG_TDO  0x3     0x208
+				>;
+			};
+	};
+};
+
+&i2c2 {
+    clock-frequency = <400000>;
+	status = "okay";
+	eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+};
+
+&i2c3 {
+    clock-frequency = <400000>;
+	status = "okay";
+	eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+};
+
+&i2c4 {
+    clock-frequency = <400000>;
+	status = "okay";
+	eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+
+	pcal6408ahk_a: gpio@20 {
+		compatible = "nxp,pcal9554b";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&isp0 {
+	status = "okay";
+};
+
+&isp1 {
+	status = "okay";
+};
+
+&isp_ry0 {
+	status = "okay";
+};
+
+&dewarp {
+	status = "okay";
+};
+
+&dec400_isp0 {
+	status = "okay";
+};
+
+&dec400_isp1 {
+	status = "okay";
+};
+
+&dec400_isp2 {
+	status = "okay";
+};
+
+&bm_visys {
+	status = "okay";
+};
+
+&bm_csi0 {
+	status = "okay";
+};
+
+&bm_csi1 {
+	status = "okay";
+};
+
+&bm_csi2 {
+	status = "okay";
+};
+
+&vi_pre {
+	//vi_pre_irq_en = <1>;
+	status = "okay";
+};
+
+&xtensa_dsp {
+	status = "okay";
+};
+
+&xtensa_dsp0 {
+	status = "okay";
+    memory-region = <&dsp0_mem>;
+};
+
+&xtensa_dsp1{
+    status = "okay";
+    memory-region = <&dsp1_mem>;
+};
+
+&vvcam_flash_led0{
+    flash_led_name = "aw36413_aw36515";
+	floodlight_i2c_bus = /bits/ 8 <2>;
+	floodlight_en_pin = <&gpio1_porta 25 0>;
+	//projection_i2c_bus = /bits/ 8 <2>;
+	flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin
+	status = "okay";
+};
+
+&vvcam_sensor0 {
+	sensor_name = "SC2310";
+	sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
+	sensor_regulator_voltage_uV = <1800000 1200000 2800000>;
+	sensor_regulator_timing_us = <70 50 20>;
+	sensor_rst = <&gpio1_porta 16 0>;
+	sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
+	DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
+	DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
+	AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
+    i2c_reg_width = /bits/ 8 <2>;
+    i2c_data_width = /bits/ 8 <1>;
+    i2c_addr = /bits/ 8 <0x30>;
+	i2c_bus = /bits/ 8 <3>;
+	status = "okay";
+};
+
+&vvcam_sensor1 {
+	sensor_name = "OV5693";
+	i2c_bus = /bits/ 8 <3>;
+	i2c_reg_width = /bits/ 8 <1>;
+	i2c_data_width = /bits/ 8 <1>;
+	status = "disabled";
+};
+
+&vvcam_sensor2 {
+	sensor_name = "GC5035";
+	sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
+	sensor_regulator_timing_us = <100 50 0>;
+	sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin
+	sensor_rst = <&gpio1_porta 29 0>;
+	sensor_pdn_delay_us = <60>; //powerdown pin / shutdown pin actived till I2C ready
+	DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>;
+	DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
+	AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
+	i2c_addr = /bits/ 8 <0x37>;
+	i2c_bus = /bits/ 8 <4>;
+	i2c_reg_width = /bits/ 8 <1>;
+	i2c_data_width = /bits/ 8 <1>;
+	status = "okay";
+};
+
+&vvcam_sensor3 {
+	sensor_name = "SC2310";
+	sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
+	sensor_regulator_timing_us = <70 50 20>;
+	sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin
+	sensor_rst = <&gpio1_porta 29 0>;
+	sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
+	DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>;
+	DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
+	AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
+	i2c_bus = /bits/ 8 <4>;
+	status = "okay";
+};
+
+&vvcam_sensor4 {
+    sensor_name = "SC132GS";
+    sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR";
+    sensor_regulator_timing_us = <70 1000 2000>;
+    i2c_addr = /bits/ 8 <0x31>;
+    sensor_rst = <&gpio1_porta 24 0>;
+	sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready
+    DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>;
+    DVDD12_IR-supply = <&soc_dvdd12_ir_reg>;
+    AVDD25_IR-supply = <&soc_avdd25_ir_reg>;
+    i2c_reg_width = /bits/ 8 <2>;
+    i2c_data_width = /bits/ 8 <1>;
+    i2c_bus = /bits/ 8 <2>;
+    status = "okay";
+};
+
+&vvcam_sensor5 {
+    sensor_name = "OV12870";
+    sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
+    sensor_regulator_voltage_uV = <1800000 1200000 2800000>;
+    sensor_regulator_timing_us = <100 50 0>;
+    sensor_rst = <&gpio1_porta 16 0>;
+    sensor_pdn_delay_us = <60>; //powerdown pin / shutdown pin actived till I2C ready
+    DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
+    DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
+    AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
+    i2c_addr = /bits/ 8 <0x10>;
+    i2c_reg_width = /bits/ 8 <2>;
+    i2c_data_width = /bits/ 8 <1>;
+    i2c_bus = /bits/ 8 <3>;
+    status = "okay";
+};
+
+&vvcam_sensor6 {
+	sensor_name = "GC02M1B";
+	sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
+	sensor_regulator_voltage_uV = <1800000 1675000 2800000>;
+	sensor_regulator_timing_us = <70 50 20>;
+	sensor_rst = <&gpio1_porta 16 0>;
+	sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
+	DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
+	DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
+	AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
+    i2c_reg_width = /bits/ 8 <1>;
+    i2c_data_width = /bits/ 8 <1>;
+    i2c_addr = /bits/ 8 <0x37>;
+	i2c_bus = /bits/ 8 <3>;
+	status = "okay";
+};
+
+&video0{
+	vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
+	channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : sc2310
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+	channel1 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : sc2310
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_SP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+	channel2 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : sc2310
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_SP2_BP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+};
+
+
+&video1{
+	vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
+	channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : sc2310
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE0";
+			dw_dst_depth = <2>;
+		};
+	};
+	channel1 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : sc2310
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE1";
+			dw_dst_depth = <2>;
+		};
+	};
+	channel2 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : sc2310
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE2";
+			dw_dst_depth = <2>;
+		};
+	};
+};
+
+&video2{
+    vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
+	channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //sc2310
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <6>; //gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <16>;
+				frame_count = <3>;
+			};
+		};
+	};
+	channel1 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //sc2310
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <6>; //gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_SP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <16>;
+				frame_count = <3>;
+			};
+		};
+	};
+	channel2 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //sc2310
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <6>; //gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_SP2_BP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <16>;
+				frame_count = <3>;
+			};
+		};
+	};
+};
+
+&video3{
+    vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
+	channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //sc2310
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <6>; //gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE0";
+			dw_dst_depth = <2>;
+		};
+	};
+	channel1 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //sc2310
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <6>; //gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE1";
+			dw_dst_depth = <2>;
+		};
+	};
+	channel2 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //sc2310
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <6>; //gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE2";
+			dw_dst_depth = <2>;
+		};
+	};
+};
+
+&video4{
+    vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
+	channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //sc2310
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <6>; //gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_PP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <0>;
+			path_type = "DSP_PATH_ISP_RY";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		ry {
+			subdev_name = "ry";
+			idx = <0>;
+			path_type = "ISP_RY_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+	channel1 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //sc2310
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <6>; //gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_PP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <0>;
+			path_type = "DSP_PATH_ISP_RY";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		ry {
+			subdev_name = "ry";
+			idx = <0>;
+			path_type = "ISP_RY_MI_PATH_SP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+	channel2 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //sc2310
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <6>; //gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_PP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <0>;
+			path_type = "DSP_PATH_ISP_RY";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		ry {
+			subdev_name = "ry";
+			idx = <0>;
+			path_type = "ISP_RY_MI_PATH_SP2_BP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+};
+
+&video5{
+	vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
+	channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //sc2310
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <6>; //gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_PP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <0>;
+			path_type = "DSP_PATH_ISP_RY";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		ry {
+			subdev_name = "ry";
+			idx = <0>;
+			path_type = "ISP_RY_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE0";
+			dw_dst_depth = <2>;
+		};
+	};
+	channel1 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //sc2310
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <6>; //gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_PP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <0>;
+			path_type = "DSP_PATH_ISP_RY";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		ry {
+			subdev_name = "ry";
+			idx = <0>;
+			path_type = "ISP_RY_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE1";
+			dw_dst_depth = <2>;
+		};
+	};
+	channel2 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //sc2310
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <6>; //gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_PP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <0>;
+			path_type = "DSP_PATH_ISP_RY";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		ry {
+			subdev_name = "ry";
+			idx = <0>;
+			path_type = "ISP_RY_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE2";
+			dw_dst_depth = <2>;
+		};
+	};
+};
+
+&video6{
+	vi_mem_pool_region = <1>;	// vi_mem: framebuffer, region[1]
+	channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <4>; //sc132gs
+			csi_idx = <2>; //<2>=CSI2X2_A
+			flash_led_idx = <0>;
+			mode_idx = <0>;
+			path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
+		};
+		dsp{
+			output {
+				max_width = <1080>;
+				max_height = <1280>;
+				bit_per_pixel = <16>;
+				frame_count = <3>;
+			};
+		};
+	};
+	channel1 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <4>; //sc132gs
+			csi_idx = <2>; //<2>=CSI2X2_A
+			flash_led_idx = <0>;
+			mode_idx = <0>;
+			path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
+		};
+		dsp{
+			output {
+				max_width = <1080>;
+				max_height = <1280>;
+				bit_per_pixel = <16>;
+				frame_count = <3>;
+			};
+		};
+	};
+};
+
+&video7{
+	channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : sc2310
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_PP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <1>;
+			path_type = "DSP_PATH_ISP_RY";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		ry {
+			subdev_name = "ry";
+			idx = <0>;
+			path_type = "ISP_RY_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE0";
+			dw_dst_depth = <2>;
+		};
+	};
+	channel1 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : sc2310
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_PP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <1>;
+			path_type = "DSP_PATH_ISP_RY";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		ry {
+			subdev_name = "ry";
+			idx = <0>;
+			path_type = "ISP_RY_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE1";
+			dw_dst_depth = <2>;
+		};
+	};
+	channel2 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : sc2310
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_PP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <1>;
+			path_type = "DSP_PATH_ISP_RY";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		ry {
+			subdev_name = "ry";
+			idx = <0>;
+			path_type = "ISP_RY_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE2";
+			dw_dst_depth = <2>;
+		};
+	};
+};
+
+
+&video8{
+    vi_mem_pool_region = <1>;	// vi_mem: framebuffer, region[1]
+	channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : sc2310
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <0>;
+			path_type = "DSP_PATH_VIPRE_DDR";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+};
+
+&video9{
+	channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <4>; //sc132gs
+			csi_idx = <2>; //<2>=CSI2X2_A
+			mode_idx = <0>;
+			path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
+		};
+		dsp{
+			output {
+				max_width = <1080>;
+				max_height = <1280>;
+				bit_per_pixel = <16>;
+				frame_count = <3>;
+			};
+		};
+	};
+};
+
+
+&video10{
+	channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
+			skip_init = <1>;
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : sc2310
+			csi_idx = <1>; //<1>=CSI2X2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+			skip_init = <1>;
+		};
+	};
+};
+
+&video11{
+	channel0 {
+		channel_id = <0>;
+		status = "okay";
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <4>; //sc132gs
+			csi_idx = <2>; //<2>=CSI2X2_A
+			flash_led_idx = <0>;
+			mode_idx = <0>;
+			path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+};
+
+&video12{ // TUNINGTOOL
+	channel0 { // CSI2
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //sc2310
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+			skip_init = <1>;
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <6>; //gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+			skip_init = <1>;
+		};
+	};
+};
+
+&trng {
+	status = "disabled";
+};
+
+&eip_28 {
+	status = "okay";
+};
+
+&vdec {
+	status = "okay";
+};
+
+&venc {
+	status = "okay";
+};
+
+&isp_venc_shake {
+	status = "okay";
+};
+
+&vidmem {
+	status = "okay";
+	memory-region = <&vi_mem>;
+};
+
+&gpu {
+	status = "okay";
+};
+
+&cpus {
+	c910_0: cpu@0 {
+		operating-points = <
+			/* kHz    uV */
+			300000	650000
+			800000	700000
+			1500000	800000
+			1848000	1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000	1000000
+		>;
+	};
+	c910_1: cpu@1 {
+		operating-points = <
+			/* kHz    uV */
+			300000	650000
+			800000	700000
+			1500000	800000
+			1848000	1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000	1000000
+		>;
+	};
+	c910_2: cpu@2 {
+
+		operating-points = <
+			/* kHz    uV */
+			300000	650000
+			800000	700000
+			1500000	800000
+			1848000	1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000	1000000
+		>;
+	};
+	c910_3: cpu@3 {
+
+		operating-points = <
+			/* kHz    uV */
+			300000	650000
+			800000	700000
+			1500000	800000
+			1848000	1000000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+			1848000	1000000
+		>;
+	};
+};

+ 2116 - 0
arch/riscv/boot/dts/thead/fire.dtsi

@@ -0,0 +1,2116 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+#include <dt-bindings/pinctrl/light-fm-left-pinctrl.h>
+#include <dt-bindings/pinctrl/light-fm-right-pinctrl.h>
+#include <dt-bindings/pinctrl/light-fm-aon-pinctrl.h>
+#include <dt-bindings/clock/light-fm-ap-clock.h>
+#include <dt-bindings/clock/light-vpsys.h>
+#include <dt-bindings/clock/light-vosys.h>
+#include <dt-bindings/clock/light-visys.h>
+#include <dt-bindings/clock/light-dspsys.h>
+#include <dt-bindings/firmware/thead/rsrc.h>
+#include <dt-bindings/soc/thead,light-iopmp.h>
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/reset/light-reset.h>
+
+/ {
+	compatible = "thead,fire";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+		gpio3 = &gpio3;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		audio_i2c0 = &audio_i2c0;
+		mmc0 = &emmc;
+		mmc1 = &sdhci0;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+		spi0 = &spi0;
+		spi1 = &qspi0;
+		spi2 = &qspi1;
+
+		flash_led0 = &vvcam_flash_led0;
+		vivcam0 = &vvcam_sensor0;
+		vivcam1 = &vvcam_sensor1;
+		vivcam2 = &vvcam_sensor2;
+		vivcam3 = &vvcam_sensor3;
+		vivcam4 = &vvcam_sensor4;
+		vivcam5 = &vvcam_sensor5;
+        vivcam6 = &vvcam_sensor6;
+
+        viv_video0 =  &video0;
+        viv_video1 =  &video1;
+		viv_video2 =  &video2;
+		viv_video3 =  &video3;
+		viv_video4 =  &video4;
+		viv_video5 =  &video5;
+		viv_video6 =  &video6;
+        viv_video7 =  &video7;
+        viv_video8 =  &video8;
+		viv_video9 =  &video9;
+		viv_video10 = &video10;
+		viv_video11 = &video11;
+		viv_video12 = &video12;
+        viv_video13 = &video13;
+		viv_video14 = &video14;
+		viv_video15 = &video15;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x200000 0x0 0xffe00000>;
+	};
+
+	resmem: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* global autoconfigured region for contiguous allocations */
+		cmamem: linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0 0x14000000>; // 320MB by default
+			alloc-ranges = <0 0x64000000 0 0x14000000>; // [0x6400_0000 ~ 0x7800_0000]
+			linux,cma-default;
+		};
+	};
+
+	thermal-zones {
+		cpu-thermal-zone {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			thermal-sensors = <&pvt 0>;
+			trips {
+				cpu_config0: trip0 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_config1: trip1 {
+					temperature = <110000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				cpu_cdev {
+					trip = <&cpu_config0>;
+					cooling-device =
+						<&c910_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&c910_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&c910_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&c910_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
+	cpus: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <3000000>;
+		c910_0: cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			cpu-freq = "1.848Ghz";
+			cpu-icache = "64KB";
+			cpu-dcache = "64KB";
+			cpu-l2cache = "1MB";
+			cpu-tlb = "1024 4-ways";
+			cpu-cacheline = "64Bytes";
+			cpu-vector = "0.7.1";
+			#cooling-cells = <2>;
+
+			operating-points = <
+				/* kHz    uV */
+				300000	600000
+				800000	700000
+				1500000	800000
+				1848000	1000000
+			>;
+			light,dvddm-operating-points = <
+				/* kHz   uV */
+				300000	750000
+				800000	800000
+				1500000	800000
+				1848000	1000000
+			>;
+			clock-latency = <61036>;
+			clocks = <&clk C910_CCLK>,
+				 <&clk C910_CCLK_I0>,
+				 <&clk CPU_PLL1_FOUTPOSTDIV>,
+				 <&clk CPU_PLL0_FOUTPOSTDIV>;
+			clock-names = "c910_cclk", "c910_cclk_i0",
+				      "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
+			dvdd-supply = <&dvdd_cpu_reg>;
+			dvddm-supply = <&dvddm_cpu_reg>;
+
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		c910_1: cpu@1 {
+			device_type = "cpu";
+			reg = <1>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			cpu-freq = "1.848Ghz";
+			cpu-icache = "64KB";
+			cpu-dcache = "64KB";
+			cpu-l2cache = "1MB";
+			cpu-tlb = "1024 4-ways";
+			cpu-cacheline = "64Bytes";
+			cpu-vector = "0.7.1";
+			#cooling-cells = <2>;
+
+			operating-points = <
+				/* kHz    uV */
+				300000	600000
+				800000	700000
+				1500000	800000
+				1848000	1000000
+			>;
+			light,dvddm-operating-points = <
+				/* kHz   uV */
+				300000	750000
+				800000	800000
+				1500000	800000
+				1848000	1000000
+			>;
+			clock-latency = <61036>;
+			clocks = <&clk C910_CCLK>,
+				 <&clk C910_CCLK_I0>,
+				 <&clk CPU_PLL1_FOUTPOSTDIV>,
+				 <&clk CPU_PLL0_FOUTPOSTDIV>;
+			clock-names = "c910_cclk", "c910_cclk_i0",
+				      "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
+			dvdd-supply = <&dvdd_cpu_reg>;
+			dvddm-supply = <&dvddm_cpu_reg>;
+
+			cpu1_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		c910_2: cpu@2 {
+			device_type = "cpu";
+			reg = <2>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			cpu-freq = "1.848Ghz";
+			cpu-icache = "64KB";
+			cpu-dcache = "64KB";
+			cpu-l2cache = "1MB";
+			cpu-tlb = "1024 4-ways";
+			cpu-cacheline = "64Bytes";
+			cpu-vector = "0.7.1";
+			#cooling-cells = <2>;
+
+			operating-points = <
+				/* kHz    uV */
+				300000	600000
+				800000	700000
+				1500000	800000
+				1848000	1000000
+			>;
+			light,dvddm-operating-points = <
+				/* kHz   uV */
+				300000	750000
+				800000	800000
+				1500000	800000
+				1848000	1000000
+			>;
+			clock-latency = <61036>;
+			clocks = <&clk C910_CCLK>,
+				 <&clk C910_CCLK_I0>,
+				 <&clk CPU_PLL1_FOUTPOSTDIV>,
+				 <&clk CPU_PLL0_FOUTPOSTDIV>;
+			clock-names = "c910_cclk", "c910_cclk_i0",
+				      "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
+			dvdd-supply = <&dvdd_cpu_reg>;
+			dvddm-supply = <&dvddm_cpu_reg>;
+
+			cpu2_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		c910_3: cpu@3 {
+			device_type = "cpu";
+			reg = <3>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcvsu";
+			mmu-type = "riscv,sv39";
+			cpu-freq = "1.848Ghz";
+			cpu-icache = "64KB";
+			cpu-dcache = "64KB";
+			cpu-l2cache = "1MB";
+			cpu-tlb = "1024 4-ways";
+			cpu-cacheline = "64Bytes";
+			cpu-vector = "0.7.1";
+			#cooling-cells = <2>;
+
+			operating-points = <
+				/* kHz    uV */
+				300000	600000
+				800000	700000
+				1500000	800000
+				1848000	1000000
+			>;
+			light,dvddm-operating-points = <
+				/* kHz   uV */
+				300000	750000
+				800000	800000
+				1500000	800000
+				1848000	1000000
+			>;
+			clock-latency = <61036>;
+			clocks = <&clk C910_CCLK>,
+				 <&clk C910_CCLK_I0>,
+				 <&clk CPU_PLL1_FOUTPOSTDIV>,
+				 <&clk CPU_PLL0_FOUTPOSTDIV>;
+			clock-names = "c910_cclk", "c910_cclk_i0",
+				      "cpu_pll1_foutpostdiv", "cpu_pll0_foutpostdiv";
+			dvdd-supply = <&dvdd_cpu_reg>;
+			dvddm-supply = <&dvddm_cpu_reg>;
+
+			cpu3_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+
+	display-subsystem {
+		compatible = "verisilicon,display-subsystem";
+		ports = <&dpu_disp0>, <&dpu_disp1>;
+		status = "disabled";
+	};
+
+	dpu-encoders {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dpu_enc0: dpu-encoder@0 {
+			/* default encoder is DSI */
+			compatible = "verisilicon,dsi-encoder";
+			reg = <0>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				/* input */
+				port@0 {
+					reg = <0>;
+
+					enc0_in: endpoint {
+						remote-endpoint = <&disp0_out>;
+					};
+				};
+			};
+		};
+
+		dpu_enc1: dpu-encoder@1 {
+			/* default encoder is DSI */
+			compatible = "verisilicon,dsi-encoder";
+			reg = <1>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				/* input */
+				port@0 {
+					reg = <0>;
+
+					enc1_in: endpoint {
+						remote-endpoint = <&disp1_out>;
+					};
+				};
+			};
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		reset: reset-sample {
+			compatible = "thead,reset-sample";
+			plic-delegate = <0xff 0xd81ffffc>;
+			entry-reg = <0xff 0xff019050>;
+			entry-cnt = <4>;
+			control-reg = <0xff 0xff015004>;
+			control-val = <0x1c>;
+			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+		};
+
+		clint0: clint@ffdc000000 {
+			compatible = "riscv,clint0";
+			interrupts-extended = <
+				&cpu0_intc  3 &cpu0_intc  7
+				&cpu1_intc  3 &cpu1_intc  7
+				&cpu2_intc  3 &cpu2_intc  7
+				&cpu3_intc  3 &cpu3_intc  7
+			>;
+			reg = <0xff 0xdc000000 0x0 0x04000000>;
+			clint,has-no-64bit-mmio;
+		};
+
+		intc: interrupt-controller@ffd8000000 {
+			#interrupt-cells = <1>;
+			compatible = "riscv,plic0";
+			interrupt-controller;
+			interrupts-extended = <
+				&cpu0_intc 0xffffffff &cpu0_intc 9
+				&cpu1_intc 0xffffffff &cpu1_intc 9
+				&cpu2_intc 0xffffffff &cpu2_intc 9
+				&cpu3_intc 0xffffffff &cpu3_intc 9
+			>;
+			reg = <0xff 0xd8000000 0x0 0x04000000>;
+			reg-names = "control";
+			riscv,max-priority = <7>;
+			riscv,ndev = <240>;
+		};
+
+		clocks {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			dummy_clock_apb: apb-clock@0 {
+				compatible = "fixed-clock";
+				reg = <0>;	/* Not address, just for index */
+				clock-frequency = <62500000>;
+				clock-output-names = "dummy_clock_apb";
+				#clock-cells = <0>;
+			};
+
+			dummy_clock_ref: ref-clock@1 {
+				compatible = "fixed-clock";
+				reg = <1>;	/* Not address, just for index */
+				clock-frequency = <50000000>;
+				clock-output-names = "dummy_clock_ref";
+				#clock-cells = <0>;
+			};
+
+			dummy_clock_suspend: suspend-clock@2 {
+				compatible = "fixed-clock";
+				reg = <2>;	/* Not address, just for index */
+				clock-frequency = <50000000>;
+				clock-output-names = "dummy_clock_suspend";
+				#clock-cells = <0>;
+			};
+
+			dummy_clock_rtc: rtc-clock@3 {
+				compatible = "fixed-clock";
+				reg = <3>;	/* Not address, just for index */
+				clock-frequency = <32768>;
+				clock-output-names = "dummy_clock_rtc";
+				#clock-cells = <0>;
+			};
+
+			dummy_clock_ahb: ahb-clock@4 {
+				compatible = "fixed-clock";
+				reg = <4>;	/* Not address, just for index */
+				clock-frequency = <50000000>;
+				clock-output-names = "dummy_clock_ahb";
+				#clock-cells = <0>;
+			};
+
+			dummy_clock_gpu: gpu-clock@6 {
+				compatible = "fixed-clock";
+				reg = <6>;  /* Not address, just for index */
+				clock-frequency = <18000000>;
+				clock-output-names = "dummy_clock_gpu";
+				#clock-cells = <0>;
+			};
+
+			dummy_clock_dphy_ref: dphy-ref-clock@7 {
+				compatible = "fixed-clock";
+				reg = <7>;      /* Not address, just for index */
+				clock-frequency = <24000000>;
+				clock-output-names = "dummy_clock_dphy_ref";
+				#clock-cells = <0>;
+			};
+
+			dummy_clock_dphy_cfg: dphy-cfg-clock@8 {
+				compatible = "fixed-clock";
+				reg = <8>;      /* Not address, just for index */
+				clock-frequency = <24000000>;
+				clock-output-names = "dummy_clock_dphy_cfg";
+				#clock-cells = <0>;
+			};
+
+			dummy_clock_dpu_pixel0: dpu-pixel-clock@9 {
+				compatible = "fixed-clock";
+				reg = <9>;
+				clock-frequency = <72000000>;
+				clock-output-names = "dummy_clock_dpu_pixel0";
+				#clock-cells = <0>;
+			};
+
+			dummy_clock_dpu_pixel1: dpu-pixel-clock@10 {
+				compatible = "fixed-clock";
+				reg = <10>;
+				clock-frequency = <74250000>;
+				clock-output-names = "dummy_clock_dpu_pixel1";
+				#clock-cells = <0>;
+			};
+
+			osc_32k: clock-osc-32k@11 {
+				compatible = "fixed-clock";
+				reg = <11>;
+				#clock-cells = <0>;
+				clock-frequency = <32768>;
+				clock-output-names = "osc_32k";
+			};
+
+			osc_24m: clock-osc-24m@12 {
+				compatible = "fixed-clock";
+				reg = <12>;
+				#clock-cells = <0>;
+				clock-frequency = <24000000>;
+				clock-output-names = "osc_24m";
+			};
+
+			rc_24m: clock-rc-24m@13 {
+				compatible = "fixed-clock";
+				reg = <13>;
+				#clock-cells = <0>;
+				clock-frequency = <24000000>;
+				clock-output-names = "rc_24m";
+			};
+
+			dummy_clock_eip: eip-clock@14 {
+				compatible = "fixed-clock";
+				reg = <14>;	/* Not address, just for index */
+				clock-frequency = <400000000>;
+				clock-output-names = "dummy_clock_eip";
+				#clock-cells = <0>;
+			};
+
+			dummy_clock_spi: spi-clock@15 {
+				compatible = "fixed-clock";
+				reg = <15>;	/* Not address, just for index */
+				clock-frequency = <396000000>;
+				clock-output-names = "dummy_clock_spi";
+				#clock-cells = <0>;
+			};
+
+			dummy_clock_qspi: spi-clock@16 {
+				compatible = "fixed-clock";
+				reg = <15>;	/* Not address, just for index */
+				clock-frequency = <792000000>;
+				clock-output-names = "dummy_clock_qspi";
+				#clock-cells = <0>;
+			};
+
+			dummy_gmac_ahb: gmac-ahb-clock@16 {
+				compatible = "fixed-clock";
+				reg = <16>;
+				clock-frequency = <250000000>;
+				clock-output-names = "dummy_gmac_ahb";
+				#clock-cells = <0>;
+			};
+
+			dummy_clock_gmac: gmac-clock@17 {
+				compatible = "fixed-clock";
+				reg = <17>;
+				clock-frequency = <500000000>;
+				clock-output-names = "dummy_clock_gmac";
+				#clock-cells = <0>;
+			};
+
+			dummy_clock_sdhci: sdhci-clock@18 {
+				compatible = "fixed-clock";
+				reg = <18>;	/* Not address, just for index */
+				clock-frequency = <198000000>;
+				clock-output-names = "dummy_clock_sdhci";
+				#clock-cells = <0>;
+			};
+
+			dummy_clock_aonsys_clk: aonsys-clk-clock@19 {
+				compatible = "fixed-clock";
+				reg = <19>;	/* Not address, just for index */
+				clock-frequency = <73728000>;
+				clock-output-names = "dummy_clock_aonsys_clk";
+				#clock-cells = <0>;
+			};
+
+			dummy_clock_uart_sclk: uart-sclk-clock@20 {
+				compatible = "fixed-clock";
+				reg = <20>;	/* Not address, just for index */
+				clock-frequency = <100000000>;
+				clock-output-names = "dummy_clock_uart_sclk";
+				#clock-cells = <0>;
+			};
+
+			dummy_clock_visys: visys-dummy-clock@21 {
+				compatible = "fixed-clock";
+				reg = <21>;
+				clock-frequency = <24000000>;
+				#clock-cells = <0>;
+			};
+		};
+
+		iso7816: iso7816-card@fff7f30000 {
+			compatible = "thead,light-iso7816-card";
+			reg = <0xff 0xf7f30000 0x0 0x4000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_iso7816>;
+			interrupts = <69>;
+			interrupt-parent = <&intc>;
+			status = "disabled";
+		};
+
+		teesys_syscon: teesys-reg@ffff200000 {
+			compatible = "syscon";
+			reg = <0xff 0xff200000 0x0 0x10000>;
+		};
+
+		visys_reg: visys-reg@ffe4040000 {
+			compatible = "thead,light-visys-reg", "syscon";
+			reg = <0xff 0xe4040000 0x0 0x1000>;
+			status = "disabled";
+		};
+
+		dspsys_reg: dspsys-reg@ffef040000 {
+			compatible = "thead,light-dspsys-reg", "syscon";
+			reg = <0xff 0xef040000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		audio_ioctrl: audio_ioctrl@ffcb01d000 {
+			compatible = "thead,light-audio-ioctrl-reg", "syscon";
+			reg = <0xff 0xcb01d000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		audio_cpr: audio_cpr@ffcb000000 {
+			compatible = "thead,light-audio-cpr-reg", "syscon";
+			reg = <0xff 0xcb000000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		nvmem_controller: efuse@ffff210000 {
+			compatible = "thead,light-fm-efuse", "syscon";
+			reg = <0xff 0xff210000 0x0 0x10000>;
+			thead,teesys = <&teesys_syscon>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			gmac0_mac_address: mac-address@176 {
+				reg = <0xb0 6>;
+			};
+
+			gmac1_mac_address: mac-address@184 {
+				reg = <0xb8 6>;
+			};
+		};
+
+		misc_sysreg: misc_sysreg@ffec02c000 {
+			compatible = "thead,light-misc-sysreg", "syscon";
+			reg = <0xff 0xec02c000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		usb3_drd: usb3_drd@ffec03f000 {
+			compatible = "thead,light-usb3-drd", "syscon";
+			reg = <0xff 0xec03f000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		gpio0: gpio@ffec005000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec005000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio0_porta: gpio0-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				nr-gpios-snps = <32>;
+				reg = <0>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupt-parent = <&intc>;
+				interrupts = <56>;
+			};
+		};
+
+		gpio1: gpio@ffec006000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xec006000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio1_porta: gpio1-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				nr-gpios-snps = <32>;
+				reg = <0>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupt-parent = <&intc>;
+				interrupts = <57>;
+			};
+		};
+
+		gpio2: gpio@ffe7f34000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f34000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio2_porta: gpio2-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				nr-gpios-snps = <32>;
+				reg = <0>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupt-parent = <&intc>;
+				interrupts = <58>;
+			};
+		};
+
+		gpio3: gpio@ffe7f38000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xe7f38000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio3_porta: gpio3-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				nr-gpios-snps = <32>;
+				reg = <0>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupt-parent = <&intc>;
+				interrupts = <59>;
+			};
+		};
+
+		ao_gpio: gpio@fffff41000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xfff41000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			ao_gpio_porta: ao_gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				nr-gpios-snps = <32>;
+				reg = <0>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupt-parent = <&intc>;
+				interrupts = <76>;
+			};
+		};
+
+		ao_gpio4: gpio@fffff52000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xff 0xfff52000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			ao_gpio4_porta: ao_gpio4-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				nr-gpios-snps = <32>;
+				reg = <0>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupt-parent = <&intc>;
+				interrupts = <55>;
+			};
+		};
+
+		padctrl1_apsys: pinctrl1-apsys@ffe7f3c000 {
+			compatible = "thead,light-fm-left-pinctrl";
+			reg = <0xff 0xe7f3c000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		padctrl0_apsys: padctrl0-apsys@ffec007000 {
+			compatible = "thead,light-fm-right-pinctrl";
+			reg = <0xff 0xec007000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		pwm: pwm@ffec01c000 {
+			compatible = "thead,pwm-light";
+			reg = <0xff 0xec01c000 0x0 0x4000>;
+			#pwm-cells = <2>;
+			clocks = <&clk CLKGEN_PWM_PCLK>,
+			         <&clk CLKGEN_PWM_CCLK>;
+			clock-names = "pclk", "cclk";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_pwm>;
+		};
+
+		timer0: timer@ffefc32000 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xefc32000 0x0 0x14>;
+			clocks = <&dummy_clock_apb>;
+			clock-names = "timer";
+			clock-frequency = <62500000>;
+			interrupts = <16>;
+			interrupt-parent = <&intc>;
+			status = "okay";
+		};
+
+		timer1: timer@ffefc32014 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xefc32014 0x0 0x14>;
+			clocks = <&dummy_clock_apb>;
+			clock-names = "timer";
+			clock-frequency = <62500000>;
+			interrupts = <17>;
+			interrupt-parent = <&intc>;
+			status = "okay";
+		};
+
+		timer2: timer@ffefc32028 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xefc32028 0x0 0x14>;
+			clocks = <&dummy_clock_apb>;
+			clock-names = "timer";
+			clock-frequency = <62500000>;
+			interrupts = <18>;
+			interrupt-parent = <&intc>;
+			status = "disabled";
+		};
+
+		timer3: timer@ffefc3203c {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xefc3203c 0x0 0x14>;
+			clocks = <&dummy_clock_apb>;
+			clock-names = "timer";
+			clock-frequency = <62500000>;
+			interrupts = <19>;
+			interrupt-parent = <&intc>;
+			status = "disabled";
+		};
+
+		padctrl_aosys: padctrl-aosys@fffff4a000 {
+			compatible = "thead,light-fm-aon-pinctrl";
+			reg = <0xff 0xfff4a000 0x0 0x2000>;
+			status = "okay";
+		};
+
+		timer4: timer@ffffc33000 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xffc33000 0x0 0x14>;
+			clocks = <&dummy_clock_apb>;
+			clock-names = "timer";
+			clock-frequency = <62500000>;
+			interrupts = <20>;
+			interrupt-parent = <&intc>;
+			status = "disabled";
+		};
+
+		timer5: timer@ffffc33014 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xffc33014 0x0 0x14>;
+			clocks = <&dummy_clock_apb>;
+			clock-names = "timer";
+			clock-frequency = <62500000>;
+			interrupts = <21>;
+			interrupt-parent = <&intc>;
+			status = "disabled";
+		};
+
+		timer6: timer@ffffc33028 {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xffc33028 0x0 0x14>;
+			clocks = <&dummy_clock_apb>;
+			clock-names = "timer";
+			clock-frequency = <62500000>;
+			interrupts = <22>;
+			interrupt-parent = <&intc>;
+			status = "disabled";
+		};
+
+		timer7: timer@ffffc3303c {
+			compatible = "snps,dw-apb-timer";
+			reg = <0xff 0xffc3303c 0x0 0x14>;
+			clocks = <&dummy_clock_apb>;
+			clock-names = "timer";
+			clock-frequency = <62500000>;
+			interrupts = <23>;
+			interrupt-parent = <&intc>;
+			status = "disabled";
+		};
+
+		uart0: serial@ffe7014000 { /* Normal serial, for C910 log */
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7014000 0x0 0x4000>;
+			interrupt-parent = <&intc>;
+			interrupts = <36>;
+			clocks = <&clk CLKGEN_UART0_SCLK>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			hw-flow-control = "unsupport";
+			status = "okay";
+		};
+
+		uart1: serial@ffe7f00000 { /* Normal serial, for C902 log */
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7f00000 0x0 0x4000>;
+			interrupt-parent = <&intc>;
+			interrupts = <37>;
+			clocks = <&clk CLKGEN_UART1_SCLK>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			hw-flow-control = "unsupport";
+			status = "okay";
+		};
+
+		uart2: serial@ffec010000 { /* IRDA supported serial, not in 85P bit */
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xec010000 0x0 0x4000>;
+			interrupt-parent = <&intc>;
+			interrupts = <38>;
+			clocks = <&clk CLKGEN_UART2_SCLK>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			hw-flow-control = "unsupport";
+			status = "disabled";
+		};
+
+		uart3: serial@ffe7f04000 { /* IRDA supported serial, not in 85P bit */
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xe7f04000 0x0 0x4000>;
+			interrupt-parent = <&intc>;
+			interrupts = <39>;
+			clocks = <&clk CLKGEN_UART3_SCLK>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			hw-flow-control = "unsupport";
+			status = "disabled";
+		};
+
+		uart4: serial@fff7f08000 { /* High Speed with Flow Ctrol serial */
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xf7f08000 0x0 0x4000>;
+			interrupt-parent = <&intc>;
+			interrupts = <40>;
+			clocks = <&clk CLKGEN_UART4_SCLK>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			hw-flow-control = "support";
+			status = "okay";
+		};
+
+		uart5: serial@fff7f0c000 { /* Normal serial, for external SE, not in 85P bit */
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff 0xf7f0c000 0x0 0x4000>;
+			interrupt-parent = <&intc>;
+			interrupts = <41>;
+			clocks = <&clk CLKGEN_UART5_SCLK>;
+			clock-names = "baudclk";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			hw-flow-control = "unsupport";
+			status = "disabled";
+		};
+
+		adc: adc@0xfffff51000 {
+			compatible = "thead,light-adc";
+			reg = <0xff 0xfff51000 0x0 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <61>;
+			clocks = <&dummy_clock_aonsys_clk>;
+			clock-names = "adc";
+			/* ADC pin is proprietary,no need to config pinctrl */
+			status = "disabled";
+		};
+
+		spi0: spi@ffe700c000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0xff 0xe700c000 0x0 0x1000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_spi0>;
+			interrupt-parent = <&intc>;
+			interrupts = <54>;
+			clocks = <&dummy_clock_spi>;
+			num-cs = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		qspi0: spi@ffea000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xea000000 0x0 0x1000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_qspi0>;
+			interrupt-parent = <&intc>;
+			interrupts = <52>;
+			clocks = <&dummy_clock_qspi>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		qspi1: spi@fff8000000 {
+			compatible = "snps,dw-apb-ssi-quad";
+			reg = <0xff 0xf8000000 0x0 0x1000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_qspi1>;
+			interrupt-parent = <&intc>;
+			interrupts = <53>;
+			clocks = <&dummy_clock_spi>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		g2d: gc620@ffecc80000 {
+			compatible = "thead,c910-gc620";
+			reg = <0xff 0xecc80000 0x0 0x40000>;
+			interrupt-parent = <&intc>;
+			interrupts = <101>;
+			interrupt-names = "irq_2d";
+			clocks = <&vpsys_clk_gate LIGHT_VPSYS_G2D_PCLK>,
+				 <&vpsys_clk_gate LIGHT_VPSYS_G2D_ACLK>,
+				 <&vpsys_clk_gate LIGHT_VPSYS_G2D_CCLK>;
+			clock-names = "pclk", "aclk", "cclk";
+			status = "okay";
+		};
+
+		dsi0: dw-mipi-dsi0@ffef500000 {
+			compatible = "thead,light-mipi-dsi", "simple-bus", "syscon";
+			reg = <0xff 0xef500000 0x0 0x10000>;
+			status = "disabled";
+
+			dphy_0: dsi0-dphy {
+				compatible = "thead,light-mipi-dphy";
+				regmap = <&dsi0>;
+				vosys-regmap = <&vosys_reg>;
+				clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_REFCLK>,
+					 <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_CFG_CLK>,
+					 <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PCLK>,
+					 <&clk OSC_24M>,
+					 <&clk OSC_24M>;
+				clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk";
+				#phy-cells = <0>;
+			};
+
+			dhost_0: dsi0-host {
+				compatible = "verisilicon,dw-mipi-dsi";
+				regmap = <&dsi0>;
+				interrupt-parent = <&intc>;
+				interrupts = <129>;
+				clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PCLK>,
+					 <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI0_PIXCLK>;
+				clock-names = "pclk", "pixclk";
+				phys = <&dphy_0>;
+				phy-names = "dphy";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		dsi1: dw-mipi-dsi1@ffef510000 {
+			compatible = "thead,light-mipi-dsi", "simple-bus", "syscon";
+			reg = <0xff 0xef510000 0x0 0x10000>;
+			status = "disabled";
+
+			dphy_1: dsi1-dphy {
+				compatible = "thead,light-mipi-dphy";
+				regmap = <&dsi1>;
+				vosys-regmap = <&vosys_reg>;
+				clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_REFCLK>,
+					 <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_CFG_CLK>,
+					 <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PCLK>,
+					 <&clk OSC_24M>,
+					 <&clk OSC_24M>;
+				clock-names = "refclk", "cfgclk", "pclk", "prefclk", "pcfgclk";
+				#phy-cells = <0>;
+			};
+
+			dhost_1: dsi1-host {
+				compatible = "verisilicon,dw-mipi-dsi";
+				regmap = <&dsi1>;
+				interrupt-parent = <&intc>;
+				interrupts = <129>;
+				clocks = <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PCLK>,
+					 <&vosys_clk_gate LIGHT_CLKGEN_MIPIDSI1_PIXCLK>;
+				clock-names = "pclk", "pixclk";
+				phys = <&dphy_1>;
+				phy-names = "dphy";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		vosys_reg: vosys@ffef528000 {
+			compatible = "thead,light-vo-subsys", "syscon";
+			reg = <0xff 0xef528000 0x0 0x1000>;
+			status = "okay";
+		};
+
+		hdmi_tx: dw-hdmi-tx@ffef540000 {
+			compatible = "thead,light-hdmi-tx";
+			reg = <0xff 0xef540000 0x0 0x40000>;
+			interrupt-parent = <&intc>;
+			interrupts = <111>;
+			clocks = <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PCLK>,
+				 <&vosys_clk_gate LIGHT_CLKGEN_HDMI_SFR_CLK>,
+				 <&vosys_clk_gate LIGHT_CLKGEN_HDMI_CEC_CLK>,
+				 <&vosys_clk_gate LIGHT_CLKGEN_HDMI_PIXCLK>,
+				 <&vosys_clk_gate LIGHT_CLKGEN_HDMI_I2S_CLK>;
+			clock-names = "iahb", "isfr", "cec", "pixclk", "i2s";
+			reg-io-width = <4>;
+			phy_version = <301>;
+			/* TODO: add phy property */
+			status = "disabled";
+		};
+
+		dpu: dc8200@ffef600000 {
+			compatible = "verisilicon,dc8200";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xff 0xef600000 0x0 0x100>,
+			      <0xff 0xef600800 0x0 0x2000>,
+			      <0xff 0xef630010 0x0 0x60>;
+			interrupt-parent = <&intc>;
+			interrupts = <93>;
+			clocks = <&vosys_clk_gate LIGHT_CLKGEN_DPU_CCLK>,
+				 <&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK0>,
+				 <&vosys_clk_gate LIGHT_CLKGEN_DPU_PIXCLK1>,
+				 <&vosys_clk_gate LIGHT_CLKGEN_DPU_ACLK>,
+				 <&vosys_clk_gate LIGHT_CLKGEN_DPU_HCLK>,
+				 <&clk DPU0_PLL_DIV_CLK>,
+				 <&clk DPU1_PLL_DIV_CLK>,
+				 <&clk DPU0_PLL_FOUTPOSTDIV>,
+				 <&clk DPU1_PLL_FOUTPOSTDIV>;
+			clock-names = "core_clk", "pix_clk0", "pix_clk1",
+				      "axi_clk", "cfg_clk", "pixclk0",
+				      "pixclk1", "dpu0_pll_foutpostdiv",
+				      "dpu1_pll_foutpostdiv";
+			status = "disabled";
+
+			dpu_disp0: port@0 {
+				reg = <0>;
+
+				disp0_out: endpoint {
+					remote-endpoint = <&enc0_in>;
+				};
+			};
+
+			dpu_disp1: port@1 {
+				reg = <1>;
+
+				disp1_out: endpoint {
+					remote-endpoint = <&enc1_in>;
+				};
+			};
+		};
+
+		watchdog0: watchdog@ffefc30000 {
+			compatible = "snps,dw-wdt";
+			reg = <0xff 0xefc30000 0x0 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <24>;
+			clocks = <&clk CLKGEN_WDT0_PCLK>;
+			clock-names = "tclk";
+			resets = <&rst LIGHT_RESET_WDT0>; 
+			status = "okay";
+		};
+
+		watchdog1: watchdog@ffefc31000 {
+			compatible = "snps,dw-wdt";
+			reg = <0xff 0xefc31000 0x0 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <25>;
+			clocks = <&clk CLKGEN_WDT1_PCLK>;
+			clock-names = "tclk";
+			resets = <&rst LIGHT_RESET_WDT1>; 
+			status = "okay";
+		};
+
+		rtc: rtc@fffff40000 {
+			compatible = "apm,xgene-rtc";
+			reg = <0xff 0xfff40000 0x0 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <74>;
+			clocks = <&dummy_clock_rtc>;
+			clock-names = "rtc";
+			status = "okay";
+		};
+
+		usb_1: usb@ffec03f000 {
+			compatible = "thead,dwc3";
+			usb3-misc-regmap = <&misc_sysreg>;
+			usb3-drd-regmap = <&usb3_drd>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			usb: dwc3@ffe7040000 {
+				compatible = "snps,dwc3";
+				reg = <0xff 0xe7040000 0x0 0x10000>;
+				interrupt-parent = <&intc>;
+				interrupts = <68>;
+				clocks = <&dummy_clock_ref>, <&dummy_clock_apb>, <&dummy_clock_suspend>;
+				clock-names = "ref", "bus_early", "suspend";
+				reg-shift = <2>;
+				reg-io-width = <4>;
+				maximum-speed = "super-speed";
+				dr_mode = "host";
+				dma-mask = <0xf 0xffffffff>;
+				snps,usb3_lpm_capable;
+				snps,usb_sofitpsync;
+				status = "okay";
+			};
+		};
+
+		pmu: pmu {
+			interrupt-parent = <&cpu0_intc>;
+			interrupts = <17>;
+			compatible = "riscv,c910_pmu";
+		};
+
+		clk: clock-controller@ffef010000 {
+			compatible = "thead,light-fm-ree-clk";
+			reg = <0xff 0xef010000 0x0 0x1000>;
+			#clock-cells = <1>;
+			clocks = <&osc_32k>, <&osc_24m>, <&rc_24m>;
+			clock-names = "osc_32k", "osc_24m", "rc_24m";
+			status = "okay";
+		};
+
+		rst: reset-controller@ffef014000 {
+			compatible = "thead,light-reset-src","syscon";
+			reg = <0xff 0xef014000 0x0 0x1000>;
+			#reset-cells = <1>;
+			status = "okay";
+		};
+
+		sys_reg: sys_reg@ffef010100 {
+			compatible = "thead,light_sys_reg";
+			reg = <0xff 0xef010100 0x0 0x100>;
+			status = "okay";
+		};
+
+		dmac0: dmac@ffefc00000 {
+			compatible = "snps,axi-dma-1.01a";
+			reg = <0xff 0xefc00000 0x0 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <27>;
+			clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
+			clock-names = "core-clk", "cfgr-clk";
+			#dma-cells = <1>;
+			dma-channels = <4>;
+			snps,block-size = <65536 65536 65536 65536>;
+			snps,priority = <0 1 2 3>;
+			snps,dma-masters = <1>;
+			snps,data-width = <4>;
+			snps,axi-max-burst-len = <16>;
+			status = "okay";
+		};
+
+		dmac1: tee_dmac@ffff340000 {
+			compatible = "snps,axi-dma-1.01a";
+			reg = <0xff 0xff340000 0x0 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <150>;
+			clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
+			clock-names = "core-clk", "cfgr-clk";
+			#dma-cells = <1>;
+			dma-channels = <4>;
+			snps,block-size = <65536 65536 65536 65536>;
+			snps,priority = <0 1 2 3>;
+			snps,dma-masters = <1>;
+			snps,data-width = <4>;
+			snps,axi-max-burst-len = <16>;
+			status = "disabled";
+		};
+
+                dmac2: audio_dmac@0xFFC8000000 {
+                        compatible = "snps,axi-dma-1.01a";
+                        reg = <0xff 0xc8000000 0x0 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <167>;
+                        clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
+                        clock-names = "core-clk", "cfgr-clk";
+                        #dma-cells = <1>;
+                        dma-channels = <16>;
+                        snps,block-size = <65536 65536 65536 65536
+                                          65536 65536 65536 65536
+                                          65536 65536 65536 65536
+                                          65536 65536 65536 65536>;
+                        snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+                        snps,dma-masters = <1>;
+                        snps,data-width = <4>;
+                        snps,axi-max-burst-len = <16>;
+                        status = "okay";
+                };
+
+		stmmac_axi_setup: stmmac-axi-config {
+			snps,wr_osr_lmt = <3>;
+			snps,rd_osr_lmt = <3>;
+			snps,blen = <16 8 4 0 0 0 0>;
+		};
+
+		gmac0: ethernet@ffe7070000 {
+			compatible = "thead,light-dwmac";
+			reg = <0xff 0xe7070000 0x0 0x2000
+			       0xff 0xec00301c 0x0 0x4
+			       0xff 0xec003020 0x0 0x4
+			       0xff 0xec003000 0x0 0x1c>;
+			reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg";
+			interrupt-parent = <&intc>;
+			interrupts = <66>;
+			interrupt-names = "macirq";
+			clocks = <&clk CLKGEN_GMAC0_CCLK>;
+			clock-names = "gmac_pll_clk";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+			snps,axi-config = <&stmmac_axi_setup>;
+			nvmem-cells = <&gmac0_mac_address>;
+			nvmem-cell-names = "mac-address";
+		};
+
+		gmac1: ethernet@ffe7060000 {
+			compatible = "thead,light-dwmac";
+			reg = <0xff 0xe7060000 0x0 0x2000
+			       0xff 0xec00401c 0x0 0x4
+			       0xff 0xec004020 0x0 0x4
+			       0xff 0xec004000 0x0 0x1c>;
+			reg-names = "gmac", "phy_if_reg", "txclk_dir_reg", "clk_mgr_reg";
+			interrupt-parent = <&intc>;
+			interrupts = <67>;
+			interrupt-names = "macirq";
+			clocks = <&clk CLKGEN_GMAC1_CCLK>;
+			clock-names = "gmac_pll_clk";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+			snps,axi-config = <&stmmac_axi_setup>;
+			nvmem-cells = <&gmac1_mac_address>;
+			nvmem-cell-names = "mac-address";
+		};
+
+		emmc: sdhci@ffe7080000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7080000 0x0 0x10000
+			       0xff 0xef014060 0x0 0x4>;
+			interrupt-parent = <&intc>;
+			interrupts = <62>;
+			interrupt-names = "sdhciirq";
+			clocks = <&dummy_clock_sdhci>;
+			clock-names = "core";
+		};
+
+		sdhci0: sd@ffe7090000 {
+			compatible = "snps,dwcmshc-sdhci";
+			reg = <0xff 0xe7090000 0x0 0x10000
+			       0xff 0xef014064 0x0 0x4>;
+			interrupt-parent = <&intc>;
+			interrupts = <64>;
+			interrupt-names = "sdhci0irq";
+			clocks = <&dummy_clock_sdhci>;
+			clock-names = "core";
+		};
+
+		sdhci1: sd@ffe70a0000 {
+		        compatible = "snps,dwcmshc-sdhci";
+		        reg = <0xff 0xe70a0000 0x0 0x10000
+		               0xff 0xef014064 0x0 0x4>;
+		        interrupt-parent = <&intc>;
+		        interrupts = <71>;
+		        interrupt-names = "sdhci1irq";
+		        clocks = <&dummy_clock_sdhci>;
+		        clock-names = "core";
+		};
+
+		hwspinlock: hwspinlock@ffefc10000 {
+			compatible = "light,hwspinlock";
+			reg = <0xff 0xefc10000 0x0 0x10000>;
+			status = "disabled";
+		};
+
+		gpu: gpu@ffef400000 {
+		    compatible = "img,gpu";
+		    reg = <0xff 0xef400000 0x0 0x100000>;
+		    interrupt-parent = <&intc>;
+		    interrupts = <102>;
+		    interrupt-names = "gpuirq";
+			vosys-regmap = <&vosys_reg>;
+			power-domains = <&pd LIGHT_AON_GPU_PD>;
+            clocks = <&vosys_clk_gate LIGHT_CLKGEN_GPU_CORE_CLK>,
+                     <&vosys_clk_gate LIGHT_CLKGEN_GPU_CFG_ACLK>;
+            clock-names = "cclk", "aclk";
+		    gpu_clk_rate = <18000000>;
+		    dma-mask = <0xf 0xffffffff>;
+		    status = "disabled";
+		};
+
+		vdec: vdec@ffecc00000 {
+			compatible = "thead,light-vc8000d";
+			reg = <0xff 0xecc00000 0x0 0x8000>;
+			interrupt-parent = <&intc>;
+			interrupts = <131>;
+			power-domains = <&pd LIGHT_AON_VDEC_PD>;
+			clocks = <&vpsys_clk_gate LIGHT_VPSYS_VDEC_ACLK>,
+				<&vpsys_clk_gate LIGHT_VPSYS_VDEC_CCLK>,
+				<&vpsys_clk_gate LIGHT_VPSYS_VDEC_PCLK>;
+			clock-names = "aclk", "cclk", "pclk";
+			status = "disabled";
+		};
+
+		venc: venc@ffecc10000 {
+			compatible = "thead,light-vc8000e";
+			reg = <0xff 0xecc10000 0x0 0x8000>;
+			interrupt-parent = <&intc>;
+			interrupts = <133>;
+			power-domains = <&pd LIGHT_AON_VENC_PD>;
+			clocks = <&vpsys_clk_gate LIGHT_VPSYS_VENC_ACLK>,
+				<&vpsys_clk_gate LIGHT_VPSYS_VENC_CCLK>,
+				<&vpsys_clk_gate LIGHT_VPSYS_VENC_PCLK>;
+			clock-names = "aclk", "cclk", "pclk";
+			status = "disabled";
+		};
+
+		isp_venc_shake: shake@ffe4078000 {
+			compatible = "thead,light-ivs";
+			reg = <0xff 0xe4078000 0x0 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <158>;
+			status = "disabled";
+		};
+
+		vidmem: vidmem@ffecc08000 {
+			compatible = "thead,light-vidmem";
+			reg = <0xff 0xecc08000 0x0 0x1000>;
+			status = "disabled";
+		};
+
+		light_i2s: light_i2s@ffe7034000 {
+			#sound-dai-cells = <1>;
+			compatible = "light,light-i2s";
+			reg = <0xff 0xe7034000 0x0 0x4000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_audio_i2s0>;
+			light,mode = "i2s-master";
+			light,sel = "ap_i2s";
+			interrupt-parent = <&intc>;
+			interrupts = <70>;
+			dmas = <&dmac0 35>, <&dmac0 40>;
+			dma-names = "tx", "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&dummy_clock_apb>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		i2s0: audio_i2s0@0xffcb014000 {
+			#sound-dai-cells = <1>;
+			compatible = "light,light-i2s";
+			reg = <0xff 0xcb014000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,sel = "i2s0";
+			interrupt-parent = <&intc>;
+			interrupts = <174>;
+			dmas = <&dmac2 9>, <&dmac2 16>;
+			dma-names = "tx", "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&dummy_clock_apb>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		i2s1: audio_i2s1@0xffcb015000 {
+			#sound-dai-cells = <1>;
+			compatible = "light,light-i2s";
+			reg = <0xff 0xcb015000 0x0 0x1000>;
+			audio-pin-regmap = <&audio_ioctrl>;
+			audio-cpr-regmap = <&audio_cpr>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,sel = "i2s1";
+			interrupt-parent = <&intc>;
+			interrupts = <175>;
+			dmas = <&dmac2 11>, <&dmac2 17>;
+			dma-names = "tx", "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&dummy_clock_apb>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		i2s3: audio_i2s3@0xffcb017000 {
+			#sound-dai-cells = <1>;
+			compatible = "light,light-i2s";
+			reg = <0xff 0xcb017000 0x0 0x1000>;
+			pinctrl-names = "default";
+			light,mode = "i2s-master";
+			light,sel = "i2s3";
+			interrupt-parent = <&intc>;
+			interrupts = <177>;
+			dmas = <&dmac2 14>, <&dmac2 16>;
+			dma-names = "tx", "rx";
+			light,dma_maxburst = <4>;
+			#dma-cells = <1>;
+			clocks = <&dummy_clock_apb>;
+			clock-names = "pclk";
+			status = "disabled";
+		};
+
+		pvt: pvt@fffff4e000 {
+		    compatible = "moortec,mr75203";
+		    reg = <0xff 0xfff4e000 0x0 0x80>,
+			  <0xff 0xfff4e080 0x0 0x100>,
+			  <0xff 0xfff4e180 0x0 0x680>,
+			  <0xff 0xfff4e800 0x0 0x600>;
+		    reg-names = "common", "ts", "pd", "vm";
+		    clocks = <&dummy_clock_aonsys_clk>;
+		    #thermal-sensor-cells = <1>;
+		    status = "okay";
+		};
+
+		i2c0: i2c@ffe7f20000 {
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f20000 0x0 0x4000>;
+			interrupt-parent = <&intc>;
+			interrupts = <44>;
+			clocks = <&dummy_clock_apb>;
+			clock-frequency = <100000>;
+			ss_hcnt = /bits/ 16 <0x104>;
+			ss_lcnt = /bits/ 16 <0xec>;
+			fs_hcnt = /bits/ 16 <0x37>;
+			fs_lcnt = /bits/ 16 <0x42>;
+			fp_hcnt = /bits/ 16 <0x14>;
+			fp_lcnt = /bits/ 16 <0x1a>;
+			hs_hcnt = /bits/ 16 <0x9>;
+			hs_lcnt = /bits/ 16 <0x11>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c@ffe7f24000 {
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f24000 0x0 0x4000>;
+			interrupt-parent = <&intc>;
+			interrupts = <45>;
+			clocks = <&dummy_clock_apb>;
+			clock-frequency = <100000>;
+			ss_hcnt = /bits/ 16 <0x104>;
+			ss_lcnt = /bits/ 16 <0xec>;
+			fs_hcnt = /bits/ 16 <0x37>;
+			fs_lcnt = /bits/ 16 <0x42>;
+			fp_hcnt = /bits/ 16 <0x14>;
+			fp_lcnt = /bits/ 16 <0x1a>;
+			hs_hcnt = /bits/ 16 <0x9>;
+			hs_lcnt = /bits/ 16 <0x11>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@ffec00c000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec00c000 0x0 0x4000>;
+			interrupt-parent = <&intc>;
+			interrupts = <46>;
+			clocks = <&dummy_clock_apb>;
+			clock-frequency = <100000>;
+			ss_hcnt = /bits/ 16 <0x104>;
+			ss_lcnt = /bits/ 16 <0xec>;
+			fs_hcnt = /bits/ 16 <0x37>;
+			fs_lcnt = /bits/ 16 <0x42>;
+			fp_hcnt = /bits/ 16 <0x14>;
+			fp_lcnt = /bits/ 16 <0x1a>;
+			hs_hcnt = /bits/ 16 <0x9>;
+			hs_lcnt = /bits/ 16 <0x11>;
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c3: i2c@ffec014000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xec014000 0x0 0x4000>;
+			interrupt-parent = <&intc>;
+			interrupts = <47>;
+			clocks = <&dummy_clock_apb>;
+			clock-frequency = <100000>;
+			ss_hcnt = /bits/ 16 <0x104>;
+			ss_lcnt = /bits/ 16 <0xec>;
+			fs_hcnt = /bits/ 16 <0x37>;
+			fs_lcnt = /bits/ 16 <0x42>;
+			fp_hcnt = /bits/ 16 <0x14>;
+			fp_lcnt = /bits/ 16 <0x1a>;
+			hs_hcnt = /bits/ 16 <0x9>;
+			hs_lcnt = /bits/ 16 <0x11>;
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c4: i2c@ffe7f28000{
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xe7f28000 0x0 0x4000>;
+			interrupt-parent = <&intc>;
+			interrupts = <48>;
+			clocks = <&dummy_clock_apb>;
+			clock-frequency = <100000>;
+			ss_hcnt = /bits/ 16 <0x104>;
+			ss_lcnt = /bits/ 16 <0xec>;
+			fs_hcnt = /bits/ 16 <0x37>;
+			fs_lcnt = /bits/ 16 <0x42>;
+			fp_hcnt = /bits/ 16 <0x14>;
+			fp_lcnt = /bits/ 16 <0x1a>;
+			hs_hcnt = /bits/ 16 <0x9>;
+			hs_lcnt = /bits/ 16 <0x11>;
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		audio_i2c0: i2c@0xffcb01a000 {
+			compatible = "snps,designware-i2c";
+			reg = <0xff 0xcb01a000 0x0 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <182>;
+			clocks = <&dummy_clock_apb>;
+			clock-frequency = <100000>;
+			ss_hcnt = /bits/ 16 <0x82>;
+			ss_lcnt = /bits/ 16 <0x78>;
+			fs_hcnt = /bits/ 16 <0x37>;
+			fs_lcnt = /bits/ 16 <0x42>;
+			fp_hcnt = /bits/ 16 <0x14>;
+			fp_lcnt = /bits/ 16 <0x1a>;
+			hs_hcnt = /bits/ 16 <0x5>;
+			hs_lcnt = /bits/ 16 <0x15>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		isp0: isp@ffe4100000 {
+			compatible = "thead,light-isp";
+			reg = <0xff 0xe4100000 0x0 0x10000>;
+			interrupt-parent = <&intc>;
+			interrupts = <117>,<118>;
+			clocks =  <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
+			          <&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
+				  <&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
+				  <&visys_clk_gate LIGHT_CLKGEN_ISP0_CLK>;
+			clock-names = "aclk", "hclk", "isp0_pclk", "cclk";
+			status = "disabled";
+		};
+
+		isp1: isp@ffe4110000 {
+			compatible = "thead,light-isp";
+			reg = <0xff 0xe4110000 0x0 0x10000>;
+			interrupt-parent = <&intc>;
+			interrupts = <120>,<121>;
+			clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP0_ACLK>,
+			         <&visys_clk_gate LIGHT_CLKGEN_ISP0_HCLK>,
+				 <&visys_clk_gate LIGHT_CLKGEN_ISP0_PIXELCLK>,
+				 <&visys_clk_gate LIGHT_CLKGEN_ISP1_CLK>,
+				 <&visys_clk_gate LIGHT_CLKGEN_ISP1_PIXELCLK>;
+			clock-names = "aclk", "hclk", "isp0_pclk", "cclk", "isp1_pclk";
+			status = "disabled";
+		};
+
+		isp_ry0: isp_ry@ffe4120000 {
+			compatible = "thead,light-isp_ry";
+			reg = <0xff 0xe4120000 0x0 0x10000>;
+			interrupt-parent = <&intc>;
+			interrupts = <123>,<124>;
+			clocks = <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_ACLK>,
+			         <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_HCLK>,
+				 <&visys_clk_gate LIGHT_CLKGEN_ISP_RY_CCLK>;
+			clock-names = "aclk", "hclk", "cclk";
+			status = "disabled";
+		};
+
+		dewarp: dewarp@ffe4130000 {
+			compatible = "thead,light-dewarp";
+			reg = <0xff 0xe4130000 0x0 0x10000>;
+			interrupt-parent = <&intc>;
+			interrupts = <98>,<99>;
+			clocks = <&visys_clk_gate LIGHT_CLKGEN_DW200_ACLK>,
+			         <&visys_clk_gate LIGHT_CLKGEN_DW200_HCLK>,
+				 <&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_VSE>,
+				 <&visys_clk_gate LIGHT_CLKGEN_DW200_CLK_DWE>;
+			clock-names = "aclk", "hclk", "vseclk", "dweclk";
+			status = "disabled";
+		};
+
+		dec400_isp0: dec400@ffe4060000 {
+			compatible = "thead,dec400";
+			reg = <0xff 0xe4060000 0x0 0x8000>;
+			status = "disabled";
+		};
+
+		dec400_isp1: dec400@ffe4068000 {
+			compatible = "thead,dec400";
+			reg = <0xff 0xe4068000 0x0 0x8000>;
+			status = "disabled";
+		};
+
+		dec400_isp2: dec400@ffe4070000 {
+			compatible = "thead,dec400";
+			reg = <0xff 0xe4070000 0x0 0x8000>;
+			status = "disabled";
+		};
+
+		bm_visys: bm_visys@ffe4040000 {
+			compatible = "thead,light-bm-visys";
+			reg = <0xff 0xe4040000 0x0 0x1000>;
+			status = "disabled";
+		};
+
+		bm_csi0: csi@ffe4000000{ //CSI2
+		    compatible = "thead,light-bm-csi";
+		    reg = < 0xff 0xe4000000 0x0 0x10000>;
+		    interrupt-parent = <&intc>;
+		    interrupts = <128>;
+		    dphyglueiftester = <0x180>;
+		    sysreg_mipi_csi_ctrl = <0x140>;
+		    clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PCLK>,
+		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PIXCLK>,
+		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>;
+		    clock-names = "pclk", "pixclk", "cfg_clk";
+		    phy_name = "CSI_4LANE";
+		    status = "disabled";
+		};
+
+		csia_reg: visys-reg@ffe4020000 {
+		    compatible = "thead,light-visys-reg", "syscon";
+		    reg = < 0xff 0xe4020000 0x0 0x10000>;
+		    status = "okay";
+		};
+
+		bm_csi1: csi@ffe4010000{ //CSI2X2_B
+		    compatible = "thead,light-bm-csi";
+		    reg = < 0xff 0xe4010000 0x0 0x10000>;
+		    interrupt-parent = <&intc>;
+		    interrupts = <126>; // 110 + 16 int_mipi_csi2x2_int0
+		    dphyglueiftester = <0x182>; // for FPGA PHY only. ASIC not needed.
+		    sysreg_mipi_csi_ctrl = <0x148>;
+		    visys-regmap = <&visys_reg>;
+		    csia-regmap = <&csia_reg>;
+		    clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PCLK>,
+		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PIXCLK>,
+		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>;
+		    clock-names = "pclk", "pixclk", "cfg_clk";
+		    phy_name = "CSI_B";
+		    status = "disabled";
+		};
+
+		bm_csi2: csi@ffe4020000{ //CSI2X2_A
+		    compatible = "thead,light-bm-csi";
+		    reg = < 0xff 0xe4020000 0x0 0x10000>;
+		    interrupt-parent = <&intc>;
+		    interrupts = <127>;
+		    dphyglueiftester = <0x184>;
+		    sysreg_mipi_csi_ctrl = <0x144>;
+		    clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PCLK>,
+		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PIXCLK>,
+		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
+		    clock-names = "pclk", "pixclk", "cfg_clk";
+		    phy_name = "CSI_A";
+		    status = "disabled";
+		};
+
+		bm_isp0: bm_isp@ffe4100000 {
+			compatible = "thead,light-bm-isp";
+			reg = <0xff 0xe4100000 0x0 0x10000>;
+			status = "disabled";
+		};
+
+		bm_isp1: bm_isp@ffe4110000 {
+			compatible = "thead,light-bm-isp";
+			reg = <0xff 0xe4110000 0x0 0x10000>;
+			status = "disabled";
+		};
+
+		//isp-ry
+		bm_isp2: bm_isp@ffe4120000 {
+			compatible = "thead,light-bm-isp";
+			reg = <0xff 0xe4120000 0x0 0x10000>;
+			status = "disabled";
+		};
+
+		vi_pre: vi_pre@ffe4030000 {
+			compatible = "thead,vi_pre";
+			reg = <0xff 0xe4030000 0x0 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <134>;
+			clocks = <&visys_clk_gate LIGHT_CLKGEN_VIPRE_ACLK>,
+			         <&visys_clk_gate LIGHT_CLKGEN_VIPRE_PCLK>,
+				 <&visys_clk_gate LIGHT_CLKGEN_VIPRE_PIXELCLK>;
+			clock-names ="aclk", "pclk", "pixclk";
+			status = "disabled";
+		};
+
+		video0: cam_dev@100 {
+			compatible = "thead,video";
+			status = "disabled";
+		};
+
+		video1: cam_dev@200 {
+			compatible = "thead,video";
+			status = "disabled";
+		};
+
+        video2: cam_dev@300 {
+			compatible = "thead,video";
+			status = "disabled";
+		};
+
+        video3: cam_dev@400 {
+			compatible = "thead,video";
+			status = "disabled";
+		};
+
+        video4: cam_dev@500 {
+			compatible = "thead,video";
+			status = "disabled";
+		};
+
+        video5: cam_dev@600 {
+			compatible = "thead,video";
+			status = "disabled";
+		};
+
+        video6: cam_dev@700 {
+			compatible = "thead,video";
+			status = "disabled";
+		};
+
+        video7: cam_dev@800 {
+			compatible = "thead,video";
+			status = "disabled";
+		};
+
+        video8: cam_dev@900 {
+			compatible = "thead,video";
+			status = "disabled";
+		};
+
+        video9: cam_dev@a00 {
+			compatible = "thead,video";
+			status = "disabled";
+		};
+
+        video10: cam_dev@b00 {
+			compatible = "thead,video";
+			status = "disabled";
+		};
+
+        video11: cam_dev@c00 {
+			compatible = "thead,video";
+			status = "disabled";
+		};
+        video12: cam_dev@d00 {
+			compatible = "thead,video";
+			status = "disabled";
+		};
+
+        video13: cam_dev@e00 {
+			compatible = "thead,video";
+			status = "disabled";
+		};
+
+		video14: cam_dev@f00 {
+			compatible = "thead,video";
+			status = "disabled";
+		};
+
+		video15: cam_dev@f01 {
+			compatible = "thead,video";
+			status = "disabled";
+		};
+
+        vvcam_flash_led0: vvcam_flash_led@0 {
+			compatible = "thead,light-vvcam-flash_led";
+			status = "disabled";
+		};
+
+		vvcam_sensor0: vvcam_sensor@0 {
+			compatible = "thead,light-vvcam-sensor";
+			status = "disabled";
+		};
+
+		vvcam_sensor1: vvcam_sensor@1 {
+			compatible = "thead,light-vvcam-sensor";
+			status = "disabled";
+		};
+
+		vvcam_sensor2: vvcam_sensor@2 {
+			compatible = "thead,light-vvcam-sensor";
+			status = "disabled";
+		};
+
+		vvcam_sensor3: vvcam_sensor@3 {
+			compatible = "thead,light-vvcam-sensor";
+			status = "disabled";
+		};
+
+		vvcam_sensor4: vvcam_sensor@4 {
+			compatible = "thead,light-vvcam-sensor";
+			status = "disabled";
+		};
+
+		vvcam_sensor5: vvcam_sensor@5 {
+			compatible = "thead,light-vvcam-sensor";
+			status = "disabled";
+		};
+
+        vvcam_sensor6: vvcam_sensor@6 {
+			compatible = "thead,light-vvcam-sensor";
+			status = "disabled";
+		};
+
+		xtensa_dsp: dsp@01{
+			compatible = "thead,dsp-hw-common";
+			reg = <0xff 0xef040000 0x0 0x001000 >;   /*DSP_SYSREG(0x0000-0xFFF) */
+			status = "disabled";
+		};
+
+		xtensa_dsp0: dsp@0 {
+			compatible = "cdns,xrp-hw-simple";
+			reg = <0xff 0xe4040190 0x0 0x000010   /* host irq DSP->CPU INT Register  */
+				   0xff 0xe40401e0 0x0 0x000010   /* device irq CPU->DSP INT Register  */
+				   0xff 0xef048000 0x0 0x008000>;  /* DSP shared memory */
+			dsp = <0>;
+			dspsys-rst-bit = <8>;           /*bit# in DSP_SYSREG*/
+			dspsys-bus-offset = <0x90>;   /*in DSP_SYSREG*/
+			device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */
+			device-irq-host-offset = <0x8>;  /*0xff 0xe40401e8 offset to trigger DSP IRQ*/
+			device-irq-mode = <1>; /*level trigger*/
+			host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */
+			host-irq-mode = <1>;   /*level trigger */
+			host-irq-offset = <0x8>;  /* 0xff 0xe4040198 offset to trigger ,device side*/
+			interrupt-parent = <&intc>;
+			interrupts = <156>;
+			firmware-name = "xrp0.elf";
+			clocks = <&dummy_clock_visys>,
+			<&dummy_clock_visys>;
+			clock-names = "pclk", "cclk";
+			status = "disabled";
+
+			#address-cells = <2>;
+			#size-cells = <1>;
+			ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
+                      0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
+					  0x00 0xfa000000 0xff 0xe0000000 0x00180000
+				      0x00 0xe0180000 0xff 0xe0180000 0x00040000
+					  0x00 0xffc00000 0xff 0xe4000000 0x00200000 >;  /* VISYS_R */
+			dsp@0 {
+				ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
+                          0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
+						  0x00 0xfa000000 0xff 0xe0000000 0x00180000
+						  0x00 0xe0180000 0xff 0xe0180000 0x00040000
+						  0x00 0xffc00000 0xff 0xe4000000 0x00200000 >;  /* VISYS_R */
+			};
+		};
+
+		xtensa_dsp1: dsp@1 {
+			compatible = "cdns,xrp-hw-simple";
+			reg = <0xff 0xe40401a0 0x0 0x000010   /* host irq DSP->CPU INT Register  */
+				   0xff 0xe40401d0 0x0 0x000010   /* device irq CPU->DSP INT Register  */
+				   0xff 0xef050000 0x0 0x008000>;  /* DSP shared memory */
+			dsp = <1>;
+			dspsys-rst-bit = <8>;           /*bit# in DSP_SYSREG*/
+			dspsys-bus-offset = <0x90>;   /*in DSP_SYSREG*/
+			device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */
+			device-irq-host-offset = <0x8>;  /*0xff 0xe40401e8 offset to trigger DSP IRQ*/
+			device-irq-mode = <1>; /*level trigger*/
+			host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */
+			host-irq-mode = <1>;   /*level trigger */
+			host-irq-offset = <0x8>;  /* 0xff 0xe4040198 offset to trigger ,device side*/
+			interrupt-parent = <&intc>;
+			interrupts = <157>;
+			firmware-name = "xrp1.elf";
+			clocks = <&dummy_clock_visys>,
+			<&dummy_clock_visys>;
+			clock-names = "pclk", "cclk";
+			status = "disabled";
+
+			#address-cells = <2>;
+			#size-cells = <1>;
+			ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
+                      0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
+					  0x00 0xfa000000 0xff 0xe0000000 0x00180000
+					  0x00 0xe0180000 0xff 0xe01C0000 0x00040000
+					  0x00 0xffc00000 0xff 0xe4000000 0x00200000 >;  /* VISYS_R */
+			dsp@0 {
+				ranges = <0x00 0x00000000 0x00 0x00000000 0xe0180000
+                          0x00 0xe01c0000 0x00 0xe01c0000 0x19E40000
+						  0x00 0xfa000000 0xff 0xe0000000 0x00180000
+						  0x00 0xe0180000 0xff 0xe01C0000 0x00040000
+						  0x00 0xffc00000 0xff 0xe4000000 0x00200000 >;  /* VISYS_R */
+			};
+		};
+
+		pmp: pmp@ffdc020000 {
+			compatible = "pmp";
+			reg = <0xff 0xdc020000 0x0 0x1000>;
+		};
+
+		mrvbr: mrvbr@ffff018050 {
+			compatible = "mrvbr";
+			reg = <0xff 0xff019050 0x0 0x1000>;
+		};
+
+		mrmr: mrmr@ffff014004 {
+			compatible = "mrmr";
+			reg = <0xff 0xff015004 0x0 0x1000>;
+		};
+
+		bmu: ddr-pmu@ffff008000 {
+			compatible = "thead,light-ddr-pmu";
+			reg = <0xff 0xff008000 0x0 0x800
+				0xff 0xff008800 0x0 0x800
+				0xff 0xff009000 0x0 0x800
+				0xff 0xff009800 0x0 0x800
+				0xff 0xff00a000 0x0 0x800>;
+			interrupt-parent = <&intc>;
+			interrupts = <87>;
+			status = "okay";
+		};
+
+		mbox_910t: mbox@ffffc38000 {
+		       compatible = "thead,light-mbox";
+		       reg = <0xff 0xffc38000 0x0 0x4000>,
+			     <0xff 0xffc44000 0x0 0x1000>,
+			     <0xff 0xffc4c000 0x0 0x1000>,
+			     <0xff 0xffc54000 0x0 0x1000>;
+		       reg-names = "local_base", "remote_icu0", "remote_icu1", "remote_icu2";
+		       interrupt-parent = <&intc>;
+		       interrupts = <28>;
+		       clocks = <&dummy_clock_apb>;
+		       clock-names = "ipg";
+		       icu_cpu_id = <0>;
+		       #mbox-cells = <2>;
+		};
+
+		trng: rng@ffff300000 {
+			compatible = "inside-secure,safexcel-eip76";
+			reg = <0xff 0xff300000 0x0 0x7d>;
+			interrupt-parent = <&intc>;
+			interrupts = <149>;
+			clocks = <&dummy_clock_eip>;
+			status = "disabled";
+		};
+
+
+		eip_28: eip-28@ffff300000 {
+			compatible = "xlnx,sunrise-fpga-1.0", "safexcel-eip-28";
+			reg = <0xff 0xff300000 0x0 0x40000>;
+			interrupt-parent = <&intc>;
+			interrupts = <144>,<145>,<146>,<147>;
+			clocks = <&dummy_clock_eip>;
+			status = "disabled";
+		};
+
+		khvhost: khvhost {
+			compatible = "thead,khv-host";
+			interrupt-parent = <&intc>;
+			interrupts = <215>; /* TEE INT SRC_7 */
+		};
+
+		visys_clk_gate: visys-clk-gate { /* VI_SYSREG_R */
+			compatible = "thead,visys-gate-controller";
+			visys-regmap = <&visys_reg>;
+			#clock-cells = <1>;
+			status = "okay";
+		};
+
+		vpsys_clk_gate: vpsys-clk-gate@ffecc30000 { /* VP_SYSREG_R */
+			compatible = "thead,vpsys-gate-controller";
+			reg = <0xff 0xecc30000 0x0 0x1000>;
+			#clock-cells = <1>;
+			status = "okay";
+		};
+
+		vosys_clk_gate: vosys-clk-gate@ffef528000 { /* VO_SYSREG_R */
+			compatible = "thead,vosys-gate-controller";
+			reg = <0xff 0xef528000 0x0 0x1000>;
+			#clock-cells = <1>;
+			status = "okay";
+		};
+
+		dspsys_clk_gate: dspsys-clk-gate {
+			compatible = "thead,dspsys-gate-controller";
+			dspsys-regmap = <&dspsys_reg>;
+			#clock-cells = <1>;
+			status = "okay";
+		};
+	};
+
+};
+

+ 8 - 8
arch/riscv/boot/dts/thead/light-a-product.dts

@@ -973,8 +973,8 @@ &vvcam_sensor1 {
 
 &video0{
 	status = "okay";
-    piplane0 {
-		pipline_id = <0>;
+    channel0 {
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -998,8 +998,8 @@ dsp {
 
 &video1{
 	status = "okay";
-	piplane0 { // VSE0
-		pipline_id = <0>;
+	channel0 { // VSE0
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -1023,8 +1023,8 @@ isp {
 
 &video2{
 	status = "okay";
-	piplane0 {
-		pipline_id = <0>;
+	channel0 {
+		channel_id = <0>;
 		status = "okay";
         sensor0 {
 			subdev_name = "vivcam";
@@ -1044,8 +1044,8 @@ dsp {
 			path_type = "DSP_PATH_VIPRE_ODD";
 		};
 	};
-    piplane1 {
-		pipline_id = <1>;
+    channel1 {
+		channel_id = <1>;
 		status = "okay";
         sensor0 {
 			subdev_name = "vivcam";

+ 32 - 29
arch/riscv/boot/dts/thead/light-a-val.dts

@@ -967,6 +967,7 @@ &vvcam_flash_led0{
 &vvcam_sensor0 {
 	sensor_name = "SC2310";
 	sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
+	sensor_regulator_voltage_uV = <1800000 1200000 2800000>;
 	sensor_regulator_timing_us = <70 50 20>;
 	sensor_rst = <&gpio1_porta 16 0>;
 	sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
@@ -1038,6 +1039,7 @@ &vvcam_sensor4 {
 &vvcam_sensor5 {
     sensor_name = "OV12870";
     sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
+    sensor_regulator_voltage_uV = <1800000 1200000 2800000>;
     sensor_regulator_timing_us = <100 50 0>;
     sensor_rst = <&gpio1_porta 16 0>;
     sensor_pdn_delay_us = <60>; //powerdown pin / shutdown pin actived till I2C ready
@@ -1054,6 +1056,7 @@ &vvcam_sensor5 {
 &vvcam_sensor6 {
 	sensor_name = "GC02M1B";
 	sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
+	sensor_regulator_voltage_uV = <1800000 1675000 2800000>;
 	sensor_regulator_timing_us = <70 50 20>;
 	sensor_rst = <&gpio1_porta 16 0>;
 	sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
@@ -1069,7 +1072,7 @@ &vvcam_sensor6 {
 
 &video0{
 	vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1096,7 +1099,7 @@ output {
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1123,7 +1126,7 @@ output {
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1155,7 +1158,7 @@ output {
 
 &video1{
 	vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1188,7 +1191,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1221,7 +1224,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1258,7 +1261,7 @@ dw {
 
 &video2{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1285,7 +1288,7 @@ output {
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1312,7 +1315,7 @@ output {
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1343,7 +1346,7 @@ output {
 
 &video3{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1376,7 +1379,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1409,7 +1412,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1446,7 +1449,7 @@ dw {
 
 &video4{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1495,7 +1498,7 @@ output {
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1544,7 +1547,7 @@ output {
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1597,7 +1600,7 @@ output {
 
 &video5{
 	vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1652,7 +1655,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1707,7 +1710,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1766,7 +1769,7 @@ dw {
 
 &video6{
 	vi_mem_pool_region = <1>;	// vi_mem: framebuffer, region[1]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; //sc132gs
@@ -1784,7 +1787,7 @@ output {
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; //sc132gs
@@ -1805,7 +1808,7 @@ output {
 };
 
 &video7{
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1860,7 +1863,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1915,7 +1918,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1975,7 +1978,7 @@ dw {
 
 &video8{
     vi_mem_pool_region = <1>;	// vi_mem: framebuffer, region[1]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -2005,7 +2008,7 @@ output {
 };
 
 &video9{
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; //sc132gs
@@ -2026,7 +2029,7 @@ output {
 
 
 &video10{
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -2047,8 +2050,8 @@ sensor1 {
 };
 
 &video11{
-	pipline0 {
-		pipline_id = <0>;
+	channel0 {
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -2073,7 +2076,7 @@ output {
 };
 
 &video12{ // TUNINGTOOL
-	pipline0 { // CSI2
+	channel0 { // CSI2
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310

+ 29 - 29
arch/riscv/boot/dts/thead/light-ant-discrete.dts

@@ -1034,7 +1034,7 @@ &vvcam_sensor3 {
 
 &video0{
     vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1061,7 +1061,7 @@ output {
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1088,7 +1088,7 @@ output {
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1120,7 +1120,7 @@ output {
 
 &video1{
     vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1153,7 +1153,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1186,7 +1186,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1223,7 +1223,7 @@ dw {
 
 &video2{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1243,7 +1243,7 @@ output {
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1263,7 +1263,7 @@ output {
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1287,7 +1287,7 @@ output {
 
 &video3{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1313,7 +1313,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1339,7 +1339,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1369,7 +1369,7 @@ dw {
 
 &video4{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1411,7 +1411,7 @@ output {
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1453,7 +1453,7 @@ output {
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1499,7 +1499,7 @@ output {
 
 &video5{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1547,7 +1547,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1595,7 +1595,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1647,7 +1647,7 @@ dw {
 
 &video6{
 	vi_mem_pool_region = <1>;	// vi_mem: framebuffer, region[1]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <1>; // vivcam1 sc132gs
@@ -1665,7 +1665,7 @@ output {
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <1>; //vivcam1 sc132gs
@@ -1687,7 +1687,7 @@ output {
 };
 
 &video7{
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1742,7 +1742,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1797,7 +1797,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1857,7 +1857,7 @@ dw {
 
 &video8{
 	vi_mem_pool_region = <1>;	// vi_mem: framebuffer, region[1]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1887,7 +1887,7 @@ output {
 };
 
 &video9{
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <1>; //vivcam1 sc132gs
@@ -1908,7 +1908,7 @@ output {
 
 
 &video10{ // TUNINGTOOL
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1929,8 +1929,8 @@ sensor1 {
 };
 
 &video11{
-	pipline0 { 
-		pipline_id = <0>;
+	channel0 { 
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -1955,7 +1955,7 @@ output {
 };
 
 &video12{ // TUNINGTOOL
-	pipline0 { // CSI2
+	channel0 { // CSI2
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310

+ 37 - 35
arch/riscv/boot/dts/thead/light-ant-ref.dts

@@ -1008,6 +1008,7 @@ &vvcam_sensor1 {
 &vvcam_sensor2 {
 	sensor_name = "GC5035";
 	sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
+	sensor_regulator_voltage_uV = <1800000 1200000 2800000>;
 	sensor_regulator_timing_us = <100 50 0>;
 	sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin 
 	sensor_rst = <&gpio1_porta 29 0>;
@@ -1025,6 +1026,7 @@ &vvcam_sensor2 {
 &vvcam_sensor3 {
 	sensor_name = "GC02M1B";
 	sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
+	sensor_regulator_voltage_uV = <1800000 1800000 2800000>;
 	sensor_regulator_timing_us = <100 50 0>;
 	sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin 
 	sensor_rst = <&gpio1_porta 29 0>;
@@ -1041,7 +1043,7 @@ &vvcam_sensor3 {
 
 &video0{
     vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1071,7 +1073,7 @@ output {
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1101,7 +1103,7 @@ output {
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1136,7 +1138,7 @@ output {
 
 &video1{
     vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1173,7 +1175,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1210,7 +1212,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1251,7 +1253,7 @@ dw {
 
 &video2{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1274,7 +1276,7 @@ output {
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1297,7 +1299,7 @@ output {
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1324,7 +1326,7 @@ output {
 
 &video3{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1353,7 +1355,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1382,7 +1384,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1415,7 +1417,7 @@ dw {
 
 &video4{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1460,7 +1462,7 @@ output {
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1505,7 +1507,7 @@ output {
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1554,7 +1556,7 @@ output {
 
 &video5{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1605,7 +1607,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1656,7 +1658,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //vivcam0 sc2310
@@ -1711,7 +1713,7 @@ dw {
 
 &video6{
 	vi_mem_pool_region = <1>;	// vi_mem: framebuffer, region[1]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <1>; // vivcam1 sc132gs
@@ -1729,7 +1731,7 @@ output {
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <1>; //vivcam1 sc132gs
@@ -1751,7 +1753,7 @@ output {
 };
 
 &video7{
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1810,7 +1812,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1869,7 +1871,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1933,7 +1935,7 @@ dw {
 
 &video8{
 	vi_mem_pool_region = <1>;	// vi_mem: framebuffer, region[1]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1966,7 +1968,7 @@ output {
 };
 
 &video9{
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <1>; //vivcam1 sc132gs
@@ -1987,7 +1989,7 @@ output {
 
 
 &video10{ // TUNINGTOOL
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -2011,8 +2013,8 @@ dma {
 };
 
 &video11{
-	pipline0 { 
-		pipline_id = <0>;
+	channel0 { 
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -2037,7 +2039,7 @@ output {
 };
 
 &video12{ // TUNINGTOOL
-	pipline0 { // CSI2
+	channel0 { // CSI2
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -2063,8 +2065,8 @@ dma {
 &video13{
     status = "okay";
     //vi_mem_pool_region = <0>;
-    pipline0 {
-        pipline_id = <0>;
+    channel0 {
+        channel_id = <0>;
         status = "okay";
         sensor0 {
             subdev_name = "vivcam";
@@ -2095,8 +2097,8 @@ output {
 &video14{
     vi_mem_pool_region = <2>;   // vi_mem: framebuffer, region[0]
     status = "okay";
-    pipline0 {
-        pipline_id = <0>;
+    channel0 {
+        channel_id = <0>;
         status = "okay";
         sensor0 {
             subdev_name = "vivcam";
@@ -2128,8 +2130,8 @@ output {
 &video15{
     status = "okay";
     //vi_mem_pool_region = <0>;
-    pipline0 {
-        pipline_id = <0>;
+    channel0 {
+        channel_id = <0>;
         status = "okay";
         sensor0 {
             subdev_name = "vivcam";

+ 33 - 33
arch/riscv/boot/dts/thead/light-b-product.dts

@@ -1107,7 +1107,7 @@ &vvcam_sensor6 {
 
 &video0{
 	vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1134,7 +1134,7 @@ output {
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1161,7 +1161,7 @@ output {
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1193,7 +1193,7 @@ output {
 
 &video1{
 	vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1226,7 +1226,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1259,7 +1259,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1296,7 +1296,7 @@ dw {
 
 &video2{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1323,7 +1323,7 @@ output {
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1350,7 +1350,7 @@ output {
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1381,7 +1381,7 @@ output {
 
 &video3{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1414,7 +1414,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1447,7 +1447,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1484,7 +1484,7 @@ dw {
 
 &video4{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1533,7 +1533,7 @@ output {
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1582,7 +1582,7 @@ output {
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1635,7 +1635,7 @@ output {
 
 &video5{
 	vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1690,7 +1690,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1745,7 +1745,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -1804,7 +1804,7 @@ dw {
 
 &video6{
 	vi_mem_pool_region = <1>;	// vi_mem: framebuffer, region[1]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; //sc132gs
@@ -1822,7 +1822,7 @@ output {
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; //sc132gs
@@ -1844,7 +1844,7 @@ output {
 };
 
 &video7{
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1899,7 +1899,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -1954,7 +1954,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -2014,7 +2014,7 @@ dw {
 
 &video8{
 	vi_mem_pool_region = <1>;	// vi_mem: framebuffer, region[1]
-    pipline0 {
+    channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -2044,7 +2044,7 @@ output {
 };
 
 &video9{
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; //sc132gs
@@ -2065,7 +2065,7 @@ output {
 
 
 &video10{ // TUNINGTOOL
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <2>; //<2>=vivcam2 : gc5035
@@ -2086,8 +2086,8 @@ sensor1 {
 };
 
 &video11{
-	pipline0 { 
-		pipline_id = <0>;
+	channel0 { 
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -2112,7 +2112,7 @@ output {
 };
 
 &video12{ // TUNINGTOOL
-	pipline0 { // CSI2
+	channel0 { // CSI2
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <0>; //sc2310
@@ -2135,8 +2135,8 @@ sensor1 {
 &video14{
     vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[0]
 	status = "okay";
-	pipline0 {
-		pipline_id = <0>;
+	channel0 {
+		channel_id = <0>;
 		status = "okay";
         sensor0 {
 			subdev_name = "vivcam";
@@ -2168,8 +2168,8 @@ output {
 &video15{
 	status = "okay";
 	//vi_mem_pool_region = <0>;
-	pipline0 {
-		pipline_id = <0>;
+	channel0 {
+		channel_id = <0>;
 		status = "okay";
         sensor0 {
 			subdev_name = "vivcam";

+ 2359 - 0
arch/riscv/boot/dts/thead/light-beagle-ref.dts

@@ -0,0 +1,2359 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ */
+
+/dts-v1/;
+
+#include "light.dtsi"
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "light-vi-devices.dtsi"
+/ {
+	model = "T-HEAD Light val board";
+	compatible = "thead,light-val", "thead,light";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x00000000 0x0 0x80000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000";
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		status = "disabled";
+		led0 {
+			label = "SYS_STATUS";
+			gpios = <&gpio1_porta 15 0>;	/* GPIO_ACTIVE_HIGH: 0 */
+			default-state = "off";
+		};
+	};
+
+	display-subsystem {
+		status = "okay";
+	};
+
+	lcd0_backlight: pwm-backlight@0 {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <7>;
+	};
+
+	light_iopmp: iopmp {
+		compatible = "thead,light-iopmp";
+
+		/* config#1: multiple valid regions */
+		iopmp_emmc: IOPMP_EMMC {
+			regions = <0x000000 0x100000>,
+				  <0x100000 0x200000>;
+			attr = <0xFFFFFFFF>;
+			dummy_slave= <0x800000>;
+		};
+
+		/* config#2: iopmp bypass */
+		iopmp_sdio0: IOPMP_SDIO0 {
+			bypass_en;
+		};
+
+		/* config#3: iopmp default region set */
+		iopmp_sdio1: IOPMP_SDIO1 {
+			attr = <0xFFFFFFFF>;
+			is_default_region;
+		};
+
+		iopmp_usb0: IOPMP_USB0 {
+			attr = <0xFFFFFFFF>;
+			is_default_region;
+		};
+
+		iopmp_ao: IOPMP_AO {
+			is_default_region;
+		};
+
+		iopmp_aud: IOPMP_AUD {
+			is_default_region;
+		};
+
+		iopmp_chip_dbg: IOPMP_CHIP_DBG {
+			is_default_region;
+		};
+
+		iopmp_eip120i: IOPMP_EIP120I {
+			is_default_region;
+		};
+
+		iopmp_eip120ii: IOPMP_EIP120II {
+			is_default_region;
+		};
+
+		iopmp_eip120iii: IOPMP_EIP120III {
+			is_default_region;
+		};
+
+		iopmp_isp0: IOPMP_ISP0 {
+			is_default_region;
+		};
+
+		iopmp_isp1: IOPMP_ISP1 {
+			is_default_region;
+		};
+
+		iopmp_dw200: IOPMP_DW200 {
+			is_default_region;
+		};
+
+		iopmp_vipre: IOPMP_VIPRE {
+			is_default_region;
+		};
+
+		iopmp_venc: IOPMP_VENC {
+			is_default_region;
+		};
+
+		iopmp_vdec: IOPMP_VDEC {
+			is_default_region;
+		};
+
+		iopmp_g2d: IOPMP_G2D {
+			is_default_region;
+		};
+
+		iopmp_fce: IOPMP_FCE {
+			is_default_region;
+		};
+
+		iopmp_npu: IOPMP_NPU {
+			is_default_region;
+		};
+
+		iopmp0_dpu: IOPMP0_DPU {
+			bypass_en;
+		};
+
+		iopmp1_dpu: IOPMP1_DPU {
+			bypass_en;
+		};
+
+		iopmp_gpu: IOPMP_GPU {
+			is_default_region;
+		};
+
+		iopmp_gmac1: IOPMP_GMAC1 {
+			is_default_region;
+		};
+
+		iopmp_gmac2: IOPMP_GMAC2 {
+			is_default_region;
+		};
+
+		iopmp_dmac: IOPMP_DMAC {
+			is_default_region;
+		};
+
+		iopmp_tee_dmac: IOPMP_TEE_DMAC {
+			is_default_region;
+		};
+
+		iopmp_dsp0: IOPMP_DSP0 {
+			is_default_region;
+		};
+
+		iopmp_dsp1: IOPMP_DSP1 {
+			is_default_region;
+		};
+	};
+
+	mbox_910t_client1: mbox_910t_client1 {
+		compatible = "thead,light-mbox-client";
+		mbox-names = "902";
+		mboxes = <&mbox_910t 1 0>;
+		status = "disabled";
+	};
+
+
+	mbox_910t_client2: mbox_910t_client2 {
+		compatible = "thead,light-mbox-client";
+		mbox-names = "906";
+		mboxes = <&mbox_910t 2 0>;
+		status = "disabled";
+	};
+
+	lightsound: lightsound@1 {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "Light-Sound-Card";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+	};
+
+	dummy_codec: dummy_codec {
+		#sound-dai-cells = <1>;
+		compatible = "linux,bt-sco";
+		status = "okay";
+	};
+
+	reg_vref_1v8: regulator-adc-verf {
+			compatible = "regulator-fixed";
+			regulator-name = "vref-1v8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+	status = "okay";
+	};
+
+        reg_tp_pwr_en: regulator-pwr-en {
+                compatible = "regulator-fixed";
+                regulator-name = "PWR_EN";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                gpio = <&gpio1_porta 12 1>;
+                enable-active-high;
+                regulator-always-on;
+        };
+
+	wcn_wifi: wireless-wlan {
+		compatible = "wlan-platdata";
+		clock-names = "clk_wifi";
+		ref-clock-frequency = <24000000>;
+		keep_wifi_power_on;
+		pinctrl-names = "default";
+		wifi_chip_type = "rtl8723ds";
+		WIFI,poweren_gpio = <&gpio2_porta 29 0>;
+		WIFI,reset_n = <&gpio2_porta 22 0>;
+		status = "okay";
+	};
+
+	wcn_bt: wireless-bluetooth {
+		compatible = "bluetooth-platdata";
+		pinctrl-names = "default", "rts_gpio";
+		BT,power_gpio    = <&gpio2_porta 29 0>;
+		status = "okay";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&pinctrl_volume>;
+		pinctrl-names = "default";
+		key-volumedown {
+			label = "Volume Down Key";
+			linux,code = <KEY_VOLUMEDOWN>;
+			debounce-interval = <1>;
+			gpios = <&gpio1_porta 19 0x1>;
+		};
+		key-volumeup {
+			label = "Volume Up Key";
+			linux,code = <KEY_VOLUMEUP>;
+			debounce-interval = <1>;
+			gpios = <&gpio2_porta 25 0x1>;
+		};
+	};
+
+	aon: aon {
+		compatible = "thead,light-aon";
+		mbox-names = "aon";
+		mboxes = <&mbox_910t 1 0>;
+		status = "okay";
+
+		pd: light-aon-pd {
+			compatible = "thead,light-aon-pd";
+			#power-domain-cells = <1>;
+		};
+
+		soc_aud_3v3_en_reg: soc_aud_3v3_en {
+			compatible = "regulator-fixed";
+			regulator-name = "soc_aud_3v3_en";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&ao_gpio_porta 7 1>;
+			enable-active-high;
+			regulator-always-on;
+		};
+
+		soc_aud_1v8_en_reg: soc_aud_1v8_en {
+			compatible = "regulator-fixed";
+			regulator-name = "soc_aud_1v8_en";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			gpio = <&ao_gpio_porta 8 1>;
+			enable-active-high;
+			regulator-always-on;
+		};
+
+		soc_vdd_3v3_en_reg: soc_vdd_3v3_en {
+			compatible = "regulator-fixed";
+			regulator-name = "soc_vdd_3v3_en";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio0_porta 30 1>;
+			enable-active-high;
+			regulator-always-on;
+		};
+
+		soc_lcd0_bias_en_reg: soc_lcd0_bias_en {
+			compatible = "regulator-fixed";
+			regulator-name = "soc_lcd0_bias_en";
+			regulator-min-microvolt = <5700000>;
+			regulator-max-microvolt = <5700000>;
+			gpio = <&gpio1_porta 10 1>;
+			enable-active-high;
+		};
+
+		soc_vdd18_lcd0_en_reg: soc_lcd0_en {
+			compatible = "regulator-fixed";
+			regulator-name = "soc_lcd0_en";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			gpio = <&gpio1_porta 9 1>;
+			enable-active-high;
+		};
+
+		soc_vdd5v_se_en_reg: soc_vdd5v_se_en {
+			compatible = "regulator-fixed";
+			regulator-name = "soc_vdd5v_se_en";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio2_porta 14 1>;
+			enable-active-high;
+			regulator-always-on;
+		};
+
+		soc_wcn33_en_reg: soc_wcn33_en {
+			compatible = "regulator-fixed";
+			regulator-name = "soc_wcn33_en";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio2_porta 29 1>;
+			enable-active-high;
+			regulator-always-on;
+		};
+
+		soc_vbus_en_reg: soc_vbus_en {
+			compatible = "regulator-fixed";
+			regulator-name = "soc_vbus_en";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio2_porta 28 1>;
+			enable-active-high;
+			regulator-always-on;
+		};
+
+
+        	soc_avdd28_rgb_reg: soc_avdd28_rgb {
+			compatible = "regulator-fixed";
+			regulator-name = "soc_avdd28_rgb";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			gpio = <&gpio1_porta 15 1>;
+			enable-active-high;
+		};
+
+        	soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
+			compatible = "regulator-fixed";
+			regulator-name = "soc_dovdd18_rgb";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			gpio = <&gpio1_porta 13 1>;
+			enable-active-high;
+		};
+
+        	soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
+			compatible = "regulator-fixed";
+			regulator-name = "soc_dvdd12_rgb";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			gpio = <&gpio1_porta 14 1>;
+			enable-active-high;
+		};
+
+        	soc_avdd25_ir_reg: soc_avdd25_ir {
+			compatible = "regulator-fixed";
+			regulator-name = "soc_avdd25_ir";
+			regulator-min-microvolt = <2500000>;
+			regulator-max-microvolt = <2500000>;
+			gpio = <&gpio0_porta 28 1>;
+			enable-active-high;
+		};
+
+        	soc_dovdd18_ir_reg: soc_dovdd18_ir {
+			compatible = "regulator-fixed";
+			regulator-name = "soc_dovdd18_ir";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			gpio = <&gpio1_porta 13 1>;
+			enable-active-high;
+		};
+
+        	soc_dvdd12_ir_reg: soc_dvdd12_ir {
+			compatible = "regulator-fixed";
+			regulator-name = "soc_dvdd12_ir";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			gpio = <&gpio0_porta 29 1>;
+			enable-active-high;
+		};
+
+		aon_reg_dialog: light-dialog-reg {
+			compatible = "thead,light-dialog-pmic-ant";
+			status = "okay";
+
+			dvdd_cpu_reg: appcpu_dvdd {
+				regulator-name = "appcpu_dvdd";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1570000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			dvddm_cpu_reg: appcpu_dvddm {
+				regulator-name = "appcpu_dvddm";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1570000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_aon_reg: soc_dvdd18_aon {
+				regulator-name = "soc_dvdd18_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd33_usb3_reg: soc_avdd33_usb3 {
+				regulator-name = "soc_avdd33_usb3";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_aon_reg: soc_dvdd08_aon {
+				regulator-name = "soc_dvdd08_aon";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
+				regulator-name = "soc_dvdd08_ddr";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
+				regulator-name = "soc_vdd_ddr_1v8";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
+				regulator-name = "soc_vdd_ddr_1v1";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
+				regulator-name = "soc_vdd_ddr_0v6";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dvdd18_ap_reg: soc_dvdd18_ap {
+				regulator-name = "soc_dvdd18_ap";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
+				regulator-name = "soc_avdd08_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
+				regulator-name = "soc_avdd18_mipi_hdmi";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd33_emmc_reg: soc_vdd33_emmc {
+				regulator-name = "soc_vdd33_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_vdd18_emmc_reg: soc_vdd18_emmc {
+				regulator-name = "soc_vdd18_emmc";
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			soc_dovdd18_scan_reg: soc_dovdd18_scan {
+				regulator-name = "soc_dovdd18_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+
+			soc_dvdd12_scan_reg: soc_dvdd12_scan {
+				regulator-name = "soc_dvdd12_scan";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+
+			soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
+				regulator-name = "soc_avdd28_scan_en";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <3600000>;
+			};
+
+		};
+
+		c910_cpufreq {
+			compatible = "thead,light-mpw-cpufreq";
+			status = "okay";
+		};
+
+		test: light-aon-test {
+			compatible = "thead,light-aon-test";
+		};
+	};
+
+};
+
+&resmem {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	ranges;
+
+	tee_mem: memory@1c000000 {
+		reg = <0x0 0x1c000000 0 0x2000000>;
+		no-map;
+	};
+
+	dsp0_mem: memory@20000000 {             /**0x2000_0000~0x2040_0000 4M**/
+		reg = <0x0 0x20000000 0x0 0x00280000   /* DSP FW code&data section 2.5M*/ 
+               0x0 0x20280000 0x0 0x00001000   /* DSP communication area 4K*/ 
+               0x0 0x20281000 0x0 0x00007000  /* Panic/log page 28K */
+               0x0 0x20288000 0x0 0x00178000>;  /* DSP shared memory 1.5M-32K*/
+		no-map;
+	};
+    dsp1_mem: memory@20400000 {             /**0x2040_0000~0x2080_0000 4M**/
+        reg = <0x0 0x20400000 0x0 0x00280000  /* DSP FW code&data section */ 
+               0x0 0x20680000 0x0 0x00001000 /* DSP communication area */
+               0x0 0x20681000 0x0 0x00007000    /* Panic/log page*/ 
+               0x0 0x20688000 0x0 0x00178000>;  /* DSP shared memory */
+        no-map;
+    };
+	vi_mem: framebuffer@10000000 {
+		reg = <0x0 0x10000000 0x0 0x02C00000	/* vi_mem_pool_region[0]  44 MB (default) */
+		       0x0 0x12C00000 0x0 0x01D00000	/* vi_mem_pool_region[1]  29 MB */
+		       0x0 0x14900000 0x0 0x01E00000>;	/* vi_mem_pool_region[2]  30 MB */
+		no-map;
+	};
+	facelib_mem: memory@17000000 {
+		reg = <0x0 0x17000000 0 0x02000000>;
+		no-map;
+	};
+
+};
+
+&adc {
+	vref-supply = <&reg_vref_1v8>;
+    #io-channel-cells = <1>;
+	status = "okay";
+};
+
+&audio_i2c0 {
+        clock-frequency = <100000>;
+        status = "okay";
+
+       es8156_audio_codec: es8156@8 {
+               #sound-dai-cells = <0>;
+               compatible = "everest,es8156";
+               reg = <0x08>;
+       };
+
+        es7210_audio_codec: es7210@40 {
+                #sound-dai-cells = <0>;
+                compatible = "MicArray_0";
+                reg = <0x40>;
+        };
+
+	audio_aw87519_pa@58 {
+		compatible = "awinic,aw87519_pa";
+		reg = <0x58>;
+		reset-gpio = <&ao_gpio4_porta 9 0x1>;
+		status = "okay";
+	};
+};
+
+&i2c1 {
+        clock-frequency = <100000>;
+        status = "okay";
+};
+
+&spi0 {
+	num-cs = <1>;
+	cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
+	rx-sample-delay-ns = <10>;
+	status = "disabled";
+
+	spi_norflash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q64jwm", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		w25q,fast-read;
+	};
+
+	spidev@1 {
+		compatible = "spidev";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		reg = <0x1>;
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&uart0 {
+	clock-frequency = <100000000>;
+};
+
+&qspi0 {
+	num-cs = <1>;
+	cs-gpios = <&gpio2_porta 3 0>;
+	rx-sample-dly = <4>;
+	status = "disabled";
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		spi-max-frequency = <100000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		reg = <0>;
+
+		partition@0 {
+			label = "ubi1";
+			reg = <0x00000000 0x08000000>;
+		};
+	};
+};
+
+&qspi1 {
+	compatible = "snps,dw-apb-ssi";
+	num-cs = <1>;
+	cs-gpios = <&gpio0_porta 1 0>;
+	status = "okay";
+
+	spidev@0 {
+		compatible = "spidev";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		reg = <0x0>;
+		spi-max-frequency = <50000000>;
+	};
+
+};
+
+&gmac0 {
+	phy-mode = "rgmii-id";
+	rx-clk-delay = <0x00>; /* for RGMII */
+	tx-clk-delay = <0x00>; /* for RGMII */
+	phy-handle = <&phy_88E1111_0>;
+	status = "okay";
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+
+		phy_88E1111_0: ethernet-phy@0 {
+			reg = <0x1>;
+		};
+
+		phy_88E1111_1: ethernet-phy@1 {
+			reg = <0x2>;
+		};
+	};
+};
+
+&gmac1 {
+	phy-mode = "rgmii-id";
+	rx-clk-delay = <0x00>; /* for RGMII */
+	tx-clk-delay = <0x00>; /* for RGMII */
+	phy-handle = <&phy_88E1111_1>;
+	status = "disabled";
+};
+
+&emmc {
+	max-frequency = <198000000>;
+	non-removable;
+	mmc-hs400-1_8v;
+	io_fixed_1v8;
+	is_emmc;
+	no-sdio;
+	no-sd;
+	pull_up;
+	bus-width = <8>;
+	status = "okay";
+};
+
+&sdhci0 {
+	max-frequency = <198000000>;
+	bus-width = <4>;
+	pull_up;
+	wprtn_ignore;
+	status = "okay";
+};
+
+&sdhci1 {
+	max-frequency = <100000000>;
+	bus-width = <4>;
+	pull_up;
+	no-sd;
+	no-mmc;
+	non-removable;
+	io_fixed_1v8;
+	post-power-on-delay-ms = <50>;
+	wprtn_ignore;
+	cap-sd-highspeed;
+	keep-power-in-suspend;
+	wakeup-source;
+	status = "okay";
+};
+
+&padctrl0_apsys { /* right-pinctrl */
+	light-evb-padctrl0 {
+			/*
+			 * Pin Configuration Node:
+			 * Format: <pin_id mux_node config>
+			 */
+			pinctrl_uart0: uart0grp {
+				thead,pins = <
+					FM_UART0_TXD	0x0	0x72
+					FM_UART0_RXD	0x0	0x72
+				>;
+			};
+
+			pinctrl_spi0: spi0grp {
+				thead,pins = <
+					FM_SPI_CSN	0x3	0x20a
+					FM_SPI_SCLK	0x0	0x20a
+					FM_SPI_MISO	0x0	0x23a
+					FM_SPI_MOSI	0x0	0x23a
+				>;
+			};
+
+			pinctrl_qspi0: qspi0grp {
+				thead,pins = <
+					FM_QSPI0_SCLK    0x0    0x20f
+					FM_QSPI0_CSN0    0x3    0x20f
+					FM_QSPI0_CSN1    0x0    0x20f
+					FM_QSPI0_D0_MOSI 0x0    0x23f
+					FM_QSPI0_D1_MISO 0x0    0x23f
+					FM_QSPI0_D2_WP   0x0    0x23f
+					FM_QSPI0_D3_HOLD 0x0    0x23f
+				>;
+			};
+
+			pinctrl_audio_i2s0: i2s0grp {
+				thead,pins = <
+					FM_QSPI0_SCLK    0x2    0x208
+					FM_QSPI0_CSN0    0x2    0x238
+					FM_QSPI0_CSN1    0x2    0x208
+					FM_QSPI0_D0_MOSI 0x2    0x238
+					FM_QSPI0_D1_MISO 0x2    0x238
+					FM_QSPI0_D2_WP   0x2    0x238
+					FM_QSPI0_D3_HOLD 0x2    0x238
+				>;
+			};
+
+			pinctrl_pwm: pwmgrp {
+				thead,pins = <
+					FM_GPIO3_2	0x1	0x208	/* pwm0 */
+				>;
+			};
+		};
+};
+
+&padctrl1_apsys { /* left-pinctrl */
+	light-evb-padctrl1 {
+			/*
+			 * Pin Configuration Node:
+			 * Format: <pin_id mux_node config>
+			 */
+			pinctrl_uart3: uart3grp {
+				thead,pins = <
+					FM_UART3_TXD	0x0	0x72
+					FM_UART3_RXD	0x0	0x72
+				>;
+			};
+
+			pinctrl_uart4: uart4grp {
+				thead,pins = <
+					FM_UART4_TXD	0x0	0x72
+					FM_UART4_RXD	0x0	0x72
+					FM_UART4_CTSN	0x0	0x72
+					FM_UART4_RTSN	0x0	0x72
+				>;
+			};
+
+			pinctrl_qspi1: qspi1grp {
+				thead,pins = <
+					FM_QSPI1_SCLK    0x0    0x20a
+					FM_QSPI1_CSN0    0x3    0x20a
+					FM_QSPI1_D0_MOSI 0x0    0x23a
+					FM_QSPI1_D1_MISO 0x0    0x23a
+				>;
+			};
+
+
+			pinctrl_iso7816: iso7816grp {
+				thead,pins = <
+					FM_QSPI1_SCLK		0x1	0x208
+					FM_QSPI1_D0_MOSI	0x1	0x238
+					FM_QSPI1_D1_MISO	0x1	0x238
+					FM_QSPI1_D2_WP		0x1	0x238
+					FM_QSPI1_D3_HOLD	0x1	0x238
+				>;
+			};
+
+			pinctrl_volume: volume_grp {
+				thead,pins = <
+					FM_CLK_OUT_2  0x3     0x208
+				>;
+			};
+		};
+};
+
+&padctrl_aosys {
+	light-aon-padctrl {
+			/*
+			 * Pin Configuration Node:
+			 * Format: <pin_id mux_node config>
+			 */
+
+			pinctrl_audiopa1: audiopa1_grp {
+				thead,pins = <
+					FM_AUDIO_PA1	0x3	0x72
+				>;
+			};
+
+			pinctrl_audiopa2: audiopa2_grp {
+				thead,pins = <
+					FM_AUDIO_PA2	0x0	0x72
+				>;
+			};
+
+	};
+};
+
+&i2c0 {
+    clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c1 {
+    clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c2 {
+    clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c3 {
+    clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c4 {
+    clock-frequency = <400000>;
+	status = "okay";
+};
+
+&isp0 {
+	status = "okay";
+};
+
+&isp1 {
+	status = "okay";
+};
+
+&isp_ry0 {
+	status = "okay";
+};
+
+&dewarp {
+	status = "okay";
+};
+
+&dec400_isp0 {
+	status = "okay";
+};
+
+&dec400_isp1 {
+	status = "okay";
+};
+
+&dec400_isp2 {
+	status = "okay";
+};
+
+&bm_visys {
+	status = "okay";
+};
+
+&bm_csi0 {
+	status = "okay";
+};
+
+&bm_csi1 {
+	status = "okay";
+};
+
+&bm_csi2 {
+	status = "okay";
+};
+
+&vi_pre {
+	//vi_pre_irq_en = <1>;
+	status = "okay";
+};
+
+&xtensa_dsp {
+	status = "okay";
+};
+
+&xtensa_dsp0 {
+	status = "okay";
+    memory-region = <&dsp0_mem>;
+};
+
+&xtensa_dsp1 {
+	status = "okay";
+    memory-region = <&dsp1_mem>;
+};
+
+&vvcam_flash_led0{
+    flash_led_name = "aw36413_aw36515";
+    floodlight_i2c_bus = /bits/ 8 <2>;
+    floodlight_en_pin = <&gpio1_porta 26 0>;
+    projection_i2c_bus = /bits/ 8 <1>;
+    flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin
+    io-channels = <&adc 2>;
+    io-channel-names = "projection_adc";
+    status = "okay";
+};
+
+&vvcam_sensor0 {
+	sensor_name = "SC2310";
+	sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
+	sensor_regulator_timing_us = <70 50 20>;
+	sensor_pdn = <&gpio1_porta 21 0>; //powerdown pin / shutdown pin 
+	sensor_rst = <&gpio1_porta 16 0>;
+	sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
+	DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
+	DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
+	AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
+    i2c_reg_width = /bits/ 8 <2>;
+    i2c_data_width = /bits/ 8 <1>;
+    i2c_addr = /bits/ 8 <0x30>;
+	i2c_bus = /bits/ 8 <3>;
+	status = "okay";
+};
+
+&vvcam_sensor1 {
+    sensor_name = "SC132GS";
+    sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR";
+    sensor_regulator_timing_us = <70 1000 2000>;
+    i2c_addr = /bits/ 8 <0x31>;
+    sensor_pdn = <&gpio1_porta 28 0>; //powerdown pin / shutdown pin 
+    sensor_rst = <&gpio1_porta 24 0>;
+	sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready
+    DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>;
+    DVDD12_IR-supply = <&soc_dvdd12_ir_reg>;
+    AVDD25_IR-supply = <&soc_avdd25_ir_reg>;
+    i2c_reg_width = /bits/ 8 <2>;
+    i2c_data_width = /bits/ 8 <1>;
+    i2c_bus = /bits/ 8 <2>;
+    status = "okay";
+};
+
+&vvcam_sensor2 {
+	sensor_name = "GC5035";
+	sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
+	sensor_regulator_timing_us = <100 50 0>;
+	sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin 
+	sensor_rst = <&gpio1_porta 29 0>;
+	sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
+	DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>;
+	DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
+	AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
+	i2c_addr = /bits/ 8 <0x37>;
+	i2c_bus = /bits/ 8 <4>;
+	i2c_reg_width = /bits/ 8 <1>;
+	i2c_data_width = /bits/ 8 <1>;
+	status = "okay";
+};
+
+&vvcam_sensor3 {
+	sensor_name = "GC02M1B";
+	sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
+	sensor_regulator_timing_us = <100 50 0>;
+	sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin 
+	sensor_rst = <&gpio1_porta 29 0>;
+	sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
+	DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>;
+	DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
+	AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
+	i2c_addr = /bits/ 8 <0x37>;
+	i2c_bus = /bits/ 8 <4>;
+	i2c_reg_width = /bits/ 8 <1>;
+	i2c_data_width = /bits/ 8 <1>;
+	status = "okay";
+};
+
+&video0{
+    vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
+    channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI0_ISP0";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+	channel1 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI0_ISP0";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_SP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+	channel2 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI0_ISP0";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_SP2_BP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+};
+
+
+&video1{
+    vi_mem_pool_region = <2>;	// vi_mem: framebuffer, region[2]
+    channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI0_ISP0";
+		};
+
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE0";
+			dw_dst_depth = <2>;
+		};
+	};
+	channel1 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI0_ISP0";
+		};
+
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE1";
+			dw_dst_depth = <2>;
+		};
+	};
+	channel2 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI0_ISP0";
+		};
+
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE2";
+			dw_dst_depth = <2>;
+		};
+	};
+};
+
+&video2{
+    vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
+    channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //vivcam0 sc2310
+			csi_idx = <1>; //<1>=CSI2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI1_ISP1";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+	channel1 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //vivcam0 sc2310
+			csi_idx = <1>; //<1>=CSI2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI1_ISP1";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_SP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+	channel2 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //vivcam0 sc2310
+			csi_idx = <1>; //<1>=CSI2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI1_ISP1";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_SP2_BP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+};
+
+&video3{
+    vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
+    channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //vivcam0 sc2310
+			csi_idx = <1>; //<1>=CSI2B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI1_ISP1";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE0";
+			dw_dst_depth = <2>;
+		};
+	};
+	channel1 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //vivcam0 sc2310
+			csi_idx = <1>; //<1>=CSI2B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI1_ISP1";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE1";
+			dw_dst_depth = <2>;
+		};
+	};
+	channel2 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //vivcam0 sc2310
+			csi_idx = <1>; //<1>=CSI2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI1_ISP1";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE2";
+			dw_dst_depth = <2>;
+		};
+	};
+};
+
+&video4{
+    vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
+    channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //vivcam0 sc2310
+			csi_idx = <1>; //<1>=CSI2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI1_ISP1";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_PP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <0>;
+			path_type = "DSP_PATH_ISP_RY";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		ry {
+			subdev_name = "ry";
+			idx = <0>;
+			path_type = "ISP_RY_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+	channel1 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //vivcam0 sc2310
+			csi_idx = <1>; //<1>=CSI2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI1_ISP1";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_PP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <0>;
+			path_type = "DSP_PATH_ISP_RY";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		ry {
+			subdev_name = "ry";
+			idx = <0>;
+			path_type = "ISP_RY_MI_PATH_SP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+	channel2 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //vivcam0 sc2310
+			csi_idx = <1>; //<1>=CSI2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI1_ISP1";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_PP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <0>;
+			path_type = "DSP_PATH_ISP_RY";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		ry {
+			subdev_name = "ry";
+			idx = <0>;
+			path_type = "ISP_RY_MI_PATH_SP2_BP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+};
+
+&video5{
+    vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
+    channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //vivcam0 sc2310
+			csi_idx = <1>; //<1>=CSI2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI1_ISP1";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_PP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <0>;
+			path_type = "DSP_PATH_ISP_RY";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		ry {
+			subdev_name = "ry";
+			idx = <0>;
+			path_type = "ISP_RY_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE0";
+			dw_dst_depth = <2>;
+		};
+	};
+	channel1 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //vivcam0 sc2310
+			csi_idx = <1>; //<1>=CSI2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI1_ISP1";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_PP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <0>;
+			path_type = "DSP_PATH_ISP_RY";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		ry {
+			subdev_name = "ry";
+			idx = <0>;
+			path_type = "ISP_RY_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE1";
+			dw_dst_depth = <2>;
+		};
+	};
+	channel2 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //vivcam0 sc2310
+			csi_idx = <1>; //<1>=CSI2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI1_ISP1";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <1>;
+			path_type = "ISP_MI_PATH_PP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <0>;
+			path_type = "DSP_PATH_ISP_RY";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		ry {
+			subdev_name = "ry";
+			idx = <0>;
+			path_type = "ISP_RY_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE2";
+			dw_dst_depth = <2>;
+		};
+	};
+};
+
+&video6{
+	vi_mem_pool_region = <1>;	// vi_mem: framebuffer, region[1]
+    channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <1>; // vivcam1 sc132gs
+			csi_idx = <2>; //<2>=CSI2X2_A
+			flash_led_idx = <0>;
+			mode_idx = <0>;
+			path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
+		};
+		dsp{
+			output {
+				max_width = <1080>;
+				max_height = <1280>;
+				bit_per_pixel = <16>;
+				frame_count = <3>;
+			};
+		};
+	};
+	channel1 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <1>; //vivcam1 sc132gs
+			csi_idx = <2>; //<2>=CSI2X2_A
+			flash_led_idx = <0>;
+			mode_idx = <0>;
+			path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
+		};
+		dsp{
+			output {
+				max_width = <1080>;
+				max_height = <1280>;
+				bit_per_pixel = <16>;
+				frame_count = <3>;
+			};
+		};
+	};
+
+};
+
+&video7{
+	channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI0_ISP0";
+		};
+
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_PP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <1>;
+			path_type = "DSP_PATH_ISP_RY";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		ry {
+			subdev_name = "ry";
+			idx = <0>;
+			path_type = "ISP_RY_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE0";
+			dw_dst_depth = <2>;
+		};
+	};
+	channel1 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI0_ISP0";
+		};
+
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_PP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <1>;
+			path_type = "DSP_PATH_ISP_RY";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		ry {
+			subdev_name = "ry";
+			idx = <0>;
+			path_type = "ISP_RY_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE1";
+			dw_dst_depth = <2>;
+		};
+	};
+	channel2 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI0_ISP0";
+		};
+
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_PP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <1>;
+			path_type = "DSP_PATH_ISP_RY";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		ry {
+			subdev_name = "ry";
+			idx = <0>;
+			path_type = "ISP_RY_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+		dw {
+			subdev_name = "dw";
+			idx = <0>;
+			path_type = "DW_DWE_VSE2";
+			dw_dst_depth = <2>;
+		};
+	};
+};
+
+
+&video8{
+	vi_mem_pool_region = <1>;	// vi_mem: framebuffer, region[1]
+	channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <3>;
+			path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+		};
+        dma {
+			path_type = "VIPRE_CSI0_DSP";
+		};
+		dsp {
+			subdev_name = "dsp";
+			idx = <0>;
+			path_type = "DSP_PATH_VIPRE_DDR";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+};
+
+&video9{
+	channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <1>; //vivcam1 sc132gs
+			csi_idx = <2>; //<2>=CSI2X2_A
+			mode_idx = <0>;
+			path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
+		};
+		dsp{
+			output {
+				max_width = <1080>;
+				max_height = <1280>;
+				bit_per_pixel = <16>;
+				frame_count = <3>;
+			};
+		};
+	};
+};
+
+
+&video10{ // TUNINGTOOL
+	channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <2>; //<2>=vivcam2 : gc5035
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <1>;
+			path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
+			skip_init = <1>;
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <3>; //<3>=vivcam3 : gc02m1b
+			csi_idx = <0>; //<0>=CSI2
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+			skip_init = <1>;
+		};
+        dma {
+			path_type = "VIPRE_CSI0_ISP0";
+		};
+	};
+};
+
+&video11{
+	channel0 { 
+		channel_id = <0>;
+		status = "okay";
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <1>; //sc132gs
+			csi_idx = <2>; //<2>=CSI2X2_A
+			flash_led_idx = <0>;
+			mode_idx = <0>;
+			path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <12>;
+				frame_count = <3>;
+			};
+		};
+	};
+};
+
+&video12{ // TUNINGTOOL
+	channel0 { // CSI2
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <0>; //sc2310
+			csi_idx = <1>; //<1>=CSI2_B
+			mode_idx = <1>;
+			path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
+			skip_init = <1>;
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <6>; //gc02m1b
+			csi_idx = <1>; //<1>=CSI2_B
+			mode_idx = <0>;
+			path_type = "SENSOR_1600x1200_RAW10_LINER";
+			skip_init = <1>;
+		};
+	};
+    dma {
+			path_type = "VIPRE_CSI1_ISP0";
+    };
+};
+
+&video13{
+    status = "okay";
+    //vi_mem_pool_region = <0>;
+    channel0 {
+        channel_id = <0>;
+        status = "okay";
+        sensor0 {
+            subdev_name = "vivcam";
+            idx = <0>; //sc2310
+			csi_idx = <1>; //<1>=CSI2_B
+            mode_idx = <1>;
+            path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+        };
+        dma {
+            subdev_name = "vipre";
+            idx = <0>;
+            path_type = "VIPRE_CSI0_ISP0";
+        };
+        isp {
+            subdev_name = "isp";
+            idx = <0>;
+            path_type = "ISP_MI_MCM_WR0";
+            output {
+                max_width = <1920>;
+                max_height = <1088>;
+                bit_per_pixel = <16>;
+                frame_count = <3>;
+            };
+        };
+    };
+};
+
+&video14{
+    vi_mem_pool_region = <2>;   // vi_mem: framebuffer, region[0]
+    status = "okay";
+    channel0 {
+        channel_id = <0>;
+        status = "okay";
+        sensor0 {
+            subdev_name = "vivcam";
+            idx = <1>; //sc132gs
+            csi_idx = <2>; //<2>=CSI2X2_A
+            flash_led_idx = <0>;
+            mode_idx = <0>;
+            path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
+        };
+        dma {
+            subdev_name = "vipre";
+            idx = <0>;
+            path_type = "VIPRE_CSI2_ISP1";
+        };
+        isp {
+            subdev_name = "isp";
+            idx = <1>;
+            path_type = "ISP_MI_MCM_WR0";
+            output {
+                max_width = <1080>;
+                max_height = <1280>;
+                bit_per_pixel = <16>;
+                frame_count = <3>;
+            };
+        };
+    };
+};
+
+&video15{
+    status = "okay";
+    //vi_mem_pool_region = <0>;
+    channel0 {
+        channel_id = <0>;
+        status = "okay";
+        sensor0 {
+            subdev_name = "vivcam";
+            idx = <0>; //<0>=vivcam0 :2310 
+			csi_idx = <1>; //<1>=CSI2_B
+            flash_led_idx = <0>;
+            mode_idx = <1>;
+            path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
+        };
+        dma {
+            subdev_name = "vipre";
+            idx = <0>;
+            path_type = "VIPRE_CSI0_DDR";
+        };
+    };
+};
+
+&trng {
+	status = "disabled";
+};
+
+&eip_28 {
+	status = "okay";
+};
+
+&vdec {
+	status = "okay";
+};
+
+&venc {
+	status = "okay";
+};
+
+&isp_venc_shake {
+	status = "okay";
+};
+
+&vidmem {
+	status = "okay";
+    memory-region = <&vi_mem>;
+};
+
+&gpu {
+	status = "okay";
+};
+
+&npu {
+	vha_clk_rate = <1000000000>;
+	status = "okay";
+};
+
+&fce {
+	memory-region = <&facelib_mem>;
+	status = "okay";
+};
+
+&dpu_enc0 {
+	status = "okay";
+
+	ports {
+		/* output */
+		port@1 {
+			reg = <1>;
+
+			enc0_out: endpoint {
+				remote-endpoint = <&dsi0_in>;
+			};
+		};
+	};
+};
+
+&dpu_enc1 {
+        ports {
+                /delete-node/ port@0;
+        };
+};
+
+&dpu {
+        status = "okay";
+};
+
+&dsi0 {
+        status = "okay";
+};
+
+&dhost_0 {
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+
+			dsi0_in: endpoint {
+				remote-endpoint = <&enc0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+
+			dsi0_out: endpoint {
+				remote-endpoint = <&panel0_in>;
+			};
+		};
+	};
+
+	panel0@0 {
+		compatible = "i2c_dsi,ili9881d";
+		reg = <0>;
+		mcu_auto_reset_enable = <0>;
+		tp_point_rotate = <0>;
+
+		port {
+			panel0_in: endpoint {
+				remote-endpoint = <&dsi0_out>;
+			};
+		};
+	};
+};
+
+&disp1_out {
+	remote-endpoint = <&hdmi_tx_in>;
+};
+
+&hdmi_tx {
+	status = "okay";
+
+	port@0 {
+		/* input */
+		hdmi_tx_in: endpoint {
+			remote-endpoint = <&disp1_out>;
+		};
+	};
+};
+
+&lightsound {
+        status = "okay";
+        simple-audio-card,dai-link@0 {          /* I2S - AUDIO SYS CODEC 8156*/
+                reg = <0>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s1 0>;
+                };
+                codec {
+                        sound-dai = <&es8156_audio_codec>;
+                };
+        };
+        simple-audio-card,dai-link@1 {          /* I2S - AUDIO SYS CODEC 7210*/
+                reg = <1>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&i2s3 0>;
+                };
+                codec {
+                        sound-dai = <&es7210_audio_codec>;
+                };
+        };
+        simple-audio-card,dai-link@2 {          /* I2S - HDMI */
+                reg = <2>;
+                format = "i2s";
+                cpu {
+                        sound-dai = <&light_i2s 1>;
+                };
+                codec {
+                        sound-dai = <&dummy_codec 2>;
+                };
+        };
+};
+
+&light_i2s {
+        status = "okay";
+};
+
+&i2s0 {
+        status = "okay";
+};
+
+&i2s1 {
+        status = "okay";
+};
+
+&i2s3 {
+        status = "okay";
+};
+
+&cpus {
+	c910_0: cpu@0 {
+		operating-points = <
+			/* kHz    uV */
+			300000	650000
+			800000	700000
+			1500000	800000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+		>;
+	};
+	c910_1: cpu@1 {
+		operating-points = <
+			/* kHz    uV */
+			300000	650000
+			800000	700000
+			1500000	800000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+		>;
+	};
+	c910_2: cpu@2 {
+
+		operating-points = <
+			/* kHz    uV */
+			300000	650000
+			800000	700000
+			1500000	800000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+		>;
+	};
+	c910_3: cpu@3 {
+
+		operating-points = <
+			/* kHz    uV */
+			300000	650000
+			800000	700000
+			1500000	800000
+		>;
+		light,dvddm-operating-points = <
+			/* kHz   uV */
+			300000	800000
+			800000	800000
+			1500000	800000
+		>;
+	};
+};

+ 116 - 19
arch/riscv/boot/dts/thead/light-beagle.dts

@@ -5,7 +5,7 @@
 
 /dts-v1/;
 
-#include "light-ant-ref.dts"
+#include "light-beagle-ref.dts"
 
 &vvcam_sensor4 { // beagle board J5 CSI0 connector
 	sensor_name = "IMX219";
@@ -30,13 +30,13 @@ &vvcam_sensor5 { // beagle board J4 CSI1 connector
 };
 
 /*
-sensor imx219 mounted on beagle board J4
+sensor imx219 mounted on beagle board J4 CSI1 (=light CSI2X2_A+CSI2X2_B   /   CSI2X2_A only)
 video0: sensor-vipre-isp0
 video1: sensor-vipre-isp0-dw
 video7: sensor-vipre-isp0-dsp1-ry-dw
 video10: tuningtool
 
-sensor imx219 mounted on beagle board J5
+sensor imx219 mounted on beagle board J5 CSI0 (=light CSI2)
 video2: sensor-vipre-isp1   
 video3: sensor-vipre-isp1-dw   
 video4: sensor-vipre-isp1-dsp0-ry
@@ -44,11 +44,108 @@ video5: sensor-vipre-isp1-dsp0-ry-dw
 video12: tuningtool
 */
 
+&video0{
+    vi_mem_pool_region = <0xFFFFFFFF>;	// vi_mem: framebuffer, region[2]
+    channel0 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <5>; // imx219
+			csi_idx = <2>; //<2>=CSI2X2_A
+			mode_idx = <0>;
+			path_type = "SENSOR_1080P_RAW10_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <0xff>; // invalid
+			csi_idx = <0xff>;
+			path_type = "SENSOR_VGA_RAW10_LINER";
+		};
+        dma {
+			subdev_name = "vipre";
+			idx = <0>;
+			path_type = "VIPRE_CSI2_ISP0";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_MP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <16>;
+				frame_count = <3>;
+			};
+		};
+	};
+	channel1 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <5>; // imx219
+			csi_idx = <2>; //<2>=CSI2X2_A
+			mode_idx = <0>;
+			path_type = "SENSOR_1080P_RAW10_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <0xff>; // invalid
+			csi_idx = <0xff>;
+			path_type = "SENSOR_VGA_RAW10_LINER";
+		};
+        dma {
+			subdev_name = "vipre";
+			idx = <0>;
+			path_type = "VIPRE_CSI2_ISP0";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_SP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <16>;
+				frame_count = <3>;
+			};
+		};
+	};
+	channel2 {
+		sensor0 {
+			subdev_name = "vivcam";
+			idx = <5>; // imx219
+			csi_idx = <2>; //<2>=CSI2X2_A
+			mode_idx = <0>;
+			path_type = "SENSOR_1080P_RAW10_LINER";
+		};
+		sensor1 {
+			subdev_name = "vivcam";
+			idx = <0xff>; // invalid
+			csi_idx = <0xff>;
+			path_type = "SENSOR_VGA_RAW10_LINER";
+		};
+        dma {
+			subdev_name = "vipre";
+			idx = <0>;
+			path_type = "VIPRE_CSI2_ISP0";
+		};
+		isp {
+			subdev_name = "isp";
+			idx = <0>;
+			path_type = "ISP_MI_PATH_SP2_BP";
+			output {
+				max_width = <1920>;
+				max_height = <1088>;
+				bit_per_pixel = <16>;
+				frame_count = <3>;
+			};
+		};
+	};
+};
+
 &video2 {
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
 	status = "okay";
-	pipline0 {
-		pipline_id = <0>;
+	channel0 {
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -80,8 +177,8 @@ output {
 			};
 		};
 	};
-	pipline1 {
-		pipline_id = <1>;
+	channel1 {
+		channel_id = <1>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -113,8 +210,8 @@ output {
 			};
 		};
 	};
-	pipline2 {
-		pipline_id = <2>;
+	channel2 {
+		channel_id = <2>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -150,7 +247,7 @@ output {
 
 &video3{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; // imx219
@@ -187,7 +284,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; // imx219
@@ -224,7 +321,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; // imx219
@@ -265,7 +362,7 @@ dw {
 
 &video4{
     vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; // imx219
@@ -318,7 +415,7 @@ output {
 			};
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; // imx219
@@ -371,7 +468,7 @@ output {
 			};
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; // imx219
@@ -428,7 +525,7 @@ output {
 
 &video5{
 	vi_mem_pool_region = <0>;	// vi_mem: framebuffer, region[0]
-	pipline0 {
+	channel0 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; // imx219
@@ -487,7 +584,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline1 {
+	channel1 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; // imx219
@@ -546,7 +643,7 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-	pipline2 {
+	channel2 {
 		sensor0 {
 			subdev_name = "vivcam";
 			idx = <4>; // imx219
@@ -605,4 +702,4 @@ dw {
 			dw_dst_depth = <2>;
 		};
 	};
-};
+};

+ 1 - 1
arch/riscv/boot/dts/thead/light-crash.dts

@@ -456,7 +456,7 @@ &gmac1 {
 	rx-clk-delay = <0x00>; /* for RGMII */
 	tx-clk-delay = <0x00>; /* for RGMII */
 	phy-handle = <&phy_88E1111_1>;
-	status = "disabled";
+	status = "okay";
 };
 
 &emmc {

+ 2 - 2
arch/riscv/boot/dts/thead/light-fm-emu.dts

@@ -451,8 +451,8 @@ &vvcam_sensor0 {
 
 &video{
 	status = "okay";
-	piplane0 {
-				pipline_id = <0>;
+	channel0 {
+				channel_id = <0>;
 				status = "okay";
 				sensor0 {
 					subdev_name = "vivcam";

+ 54 - 54
arch/riscv/boot/dts/thead/light-vi-devices.dtsi

@@ -5,8 +5,8 @@
 
 &video0{
 	status = "okay";
-	pipline0 {
-		pipline_id = <0>;
+	channel0 {
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -31,8 +31,8 @@ isp {
 			path_type = "ISP_MI_PATH_MP";
 		};
 	};
-	pipline1 {
-		pipline_id = <1>;
+	channel1 {
+		channel_id = <1>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -57,8 +57,8 @@ isp {
 			path_type = "ISP_MI_PATH_SP";
 		};
 	};
-	pipline2 {
-		pipline_id = <2>;
+	channel2 {
+		channel_id = <2>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -87,8 +87,8 @@ isp {
 
 &video1{
 	status = "okay";
-	pipline0 { // VSE0
-		pipline_id = <0>;
+	channel0 { // VSE0
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -118,8 +118,8 @@ dw {
 			path_type = "DW_DWE_VSE0";
 		};
 	};
-	pipline1 { // VSE1
-		pipline_id = <1>;
+	channel1 { // VSE1
+		channel_id = <1>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -149,8 +149,8 @@ dw {
 			path_type = "DW_DWE_VSE1";
 		};
 	};
-	pipline2 { // VSE2
-		pipline_id = <2>;
+	channel2 { // VSE2
+		channel_id = <2>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -184,8 +184,8 @@ dw {
 
 &video2 {
 	status = "okay";
-	pipline0 {
-		pipline_id = <0>;
+	channel0 {
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -210,8 +210,8 @@ isp {
 			path_type = "ISP_MI_PATH_MP";
 		};
 	};
-	pipline1 {
-		pipline_id = <1>;
+	channel1 {
+		channel_id = <1>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -236,8 +236,8 @@ isp {
 			path_type = "ISP_MI_PATH_SP";
 		};
 	};
-	pipline2 {
-		pipline_id = <2>;
+	channel2 {
+		channel_id = <2>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -267,8 +267,8 @@ isp {
 
 &video3 {
 	status = "okay";
-		pipline0 {
-		pipline_id = <0>;
+		channel0 {
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -298,8 +298,8 @@ dw {
 			path_type = "DW_DWE_VSE0";
 		};
 	};
-	pipline1 {
-		pipline_id = <1>;
+	channel1 {
+		channel_id = <1>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -330,8 +330,8 @@ dw {
 			path_type = "DW_DWE_VSE1";
 		};
 	};
-	pipline2 {
-		pipline_id = <2>;
+	channel2 {
+		channel_id = <2>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -365,8 +365,8 @@ dw {
 
 &video4 {
 	status = "okay";
-	pipline0 {
-		pipline_id = <0>;
+	channel0 {
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -402,8 +402,8 @@ ry {
 			path_type = "ISP_RY_MI_PATH_MP";
 		};
 	};
-	pipline1 {
-		pipline_id = <1>;
+	channel1 {
+		channel_id = <1>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -438,8 +438,8 @@ ry {
 			path_type = "ISP_RY_MI_PATH_SP";
 		};
 	};
-	pipline2 {
-		pipline_id = <2>;
+	channel2 {
+		channel_id = <2>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -478,8 +478,8 @@ ry {
 
 &video5 {
 	status = "okay";
-	pipline0 {
-		pipline_id = <0>;
+	channel0 {
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -520,8 +520,8 @@ dw {
 			path_type = "DW_DWE_VSE0";
 		};
 	};
-	pipline1 {
-		pipline_id = <1>;
+	channel1 {
+		channel_id = <1>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -561,8 +561,8 @@ dw {
 			path_type = "DW_DWE_VSE1";
 		};
 	};
-	pipline2 {
-		pipline_id = <2>;
+	channel2 {
+		channel_id = <2>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -607,8 +607,8 @@ dw {
 
 &video6 {
 	status = "okay";
-	pipline0 {
-		pipline_id = <0>;
+	channel0 {
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -633,8 +633,8 @@ dsp {
 			path_type = "DSP_PATH_VIPRE_ODD";
 		};
 	};
-	pipline1 {
-		pipline_id = <1>;
+	channel1 {
+		channel_id = <1>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -664,8 +664,8 @@ dsp {
 
 &video7{
 	status = "okay";
-	pipline0 {
-		pipline_id = <0>;
+	channel0 {
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -706,8 +706,8 @@ dw {
 		};
 
 	};
-	pipline1 {
-		pipline_id = <1>;
+	channel1 {
+		channel_id = <1>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -747,8 +747,8 @@ dw {
 			path_type = "DW_DWE_VSE1";
 		};
 	};
-	pipline2 {
-		pipline_id = <2>;
+	channel2 {
+		channel_id = <2>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -793,8 +793,8 @@ dw {
 
 &video8{
 	status = "okay";
-	pipline0 {
-		pipline_id = <0>;
+	channel0 {
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -824,8 +824,8 @@ dsp {
 
 &video9 { //IR debug
 	status = "okay";
-	pipline0 {
-		pipline_id = <0>;
+	channel0 {
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -857,7 +857,7 @@ dsp {
 
 &video10{ // TUNING TOOL
 	status = "okay";
-	pipline0 { // CSI2X2_B
+	channel0 { // CSI2X2_B
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -884,8 +884,8 @@ dma {
 
 &video11{
 	status = "okay";
-	pipline0 {
-		pipline_id = <0>;
+	channel0 {
+		channel_id = <0>;
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";
@@ -915,7 +915,7 @@ isp {
 
 &video12{ // TUNING TOOL
 	status = "okay";
-	pipline0 { // CSI2
+	channel0 { // CSI2
 		status = "okay";
 		sensor0 {
 			subdev_name = "vivcam";

+ 41 - 48
arch/riscv/boot/dts/thead/light.dtsi

@@ -1761,65 +1761,58 @@ bm_visys: bm_visys@ffe4040000 {
 		};
 
 		bm_csi0: csi@ffe4000000{ //CSI2
-			compatible = "thead,light-bm-csi";
-			reg = < 0xff 0xe4000000 0x0 0x10000>;
-			interrupt-parent = <&intc>;
-			interrupts = <128>;
-			dphyglueiftester = <0x180>;
-			sysreg_mipi_csi_ctrl = <0x140>;
-			clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PCLK>,
-			         <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PIXCLK>,
-				 <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
-				 <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
-				 <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
-				clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
-            phy_name = "CSI_4LANE";
-			status = "disabled";
+		    compatible = "thead,light-bm-csi";
+		    reg = < 0xff 0xe4000000 0x0 0x10000>;
+		    interrupt-parent = <&intc>;
+		    interrupts = <128>;
+		    dphyglueiftester = <0x180>;
+		    sysreg_mipi_csi_ctrl = <0x140>;
+		    clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PCLK>,
+		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_PIXCLK>,
+		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>;
+		    clock-names = "pclk", "pixclk", "cfg_clk";
+		    phy_name = "CSI_4LANE";
+		    status = "disabled";
 		};
 
-        csia_reg: visys-reg@ffe4020000 {
+		csia_reg: visys-reg@ffe4020000 {
 		    compatible = "thead,light-visys-reg", "syscon";
-			reg = < 0xff 0xe4020000 0x0 0x10000>;
-            status = "okay";
+		    reg = < 0xff 0xe4020000 0x0 0x10000>;
+		    status = "okay";
 		};
 
 		bm_csi1: csi@ffe4010000{ //CSI2X2_B
-			compatible = "thead,light-bm-csi";
-			reg = < 0xff 0xe4010000 0x0 0x10000>;
-			interrupt-parent = <&intc>;
-			interrupts = <126>; // 110 + 16 int_mipi_csi2x2_int0
-			dphyglueiftester = <0x182>; // for FPGA PHY only. ASIC not needed.
-			sysreg_mipi_csi_ctrl = <0x148>;
-            visys-regmap = <&visys_reg>;
-            csia-regmap = <&csia_reg>;
-			clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PCLK>,
-			         <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PIXCLK>,
-				 <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
-				 <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
-				 <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
-			clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
-            phy_name = "CSI_B";
-			status = "disabled";
+		    compatible = "thead,light-bm-csi";
+		    reg = < 0xff 0xe4010000 0x0 0x10000>;
+		    interrupt-parent = <&intc>;
+		    interrupts = <126>; // 110 + 16 int_mipi_csi2x2_int0
+		    dphyglueiftester = <0x182>; // for FPGA PHY only. ASIC not needed.
+		    sysreg_mipi_csi_ctrl = <0x148>;
+		    visys-regmap = <&visys_reg>;
+		    csia-regmap = <&csia_reg>;
+		    clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PCLK>,
+		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_PIXCLK>,
+		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>;
+		    clock-names = "pclk", "pixclk", "cfg_clk";
+		    phy_name = "CSI_B";
+		    status = "disabled";
 		};
 
 		bm_csi2: csi@ffe4020000{ //CSI2X2_A
-			compatible = "thead,light-bm-csi";
-			reg = < 0xff 0xe4020000 0x0 0x10000>;
-			interrupt-parent = <&intc>;
-			interrupts = <127>;
-			dphyglueiftester = <0x184>;
-			sysreg_mipi_csi_ctrl = <0x144>;
-			clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PCLK>,
-			         <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PIXCLK>,
-				 <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK>,
-				 <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK>,
-				 <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
-			clock-names = "pclk", "pixclk", "cfg_clk0", "cfg_clk1", "cfg_clk2";
-            phy_name = "CSI_A";
-			status = "disabled";
+		    compatible = "thead,light-bm-csi";
+		    reg = < 0xff 0xe4020000 0x0 0x10000>;
+		    interrupt-parent = <&intc>;
+		    interrupts = <127>;
+		    dphyglueiftester = <0x184>;
+		    sysreg_mipi_csi_ctrl = <0x144>;
+		    clocks = <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PCLK>,
+		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_PIXCLK>,
+		             <&visys_clk_gate LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK>;
+		    clock-names = "pclk", "pixclk", "cfg_clk";
+		    phy_name = "CSI_A";
+		    status = "disabled";
 		};
 
-
 		bm_isp0: bm_isp@ffe4100000 {
 			compatible = "thead,light-bm-isp";
 			reg = <0xff 0xe4100000 0x0 0x10000>;

+ 310 - 0
arch/riscv/configs/fire_defconfig

@@ -0,0 +1,310 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_CGROUPS=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+# CONFIG_BUG is not set
+CONFIG_BPF_SYSCALL=y
+CONFIG_PERF_EVENTS=y
+CONFIG_FORCE_MAX_ZONEORDER=15
+CONFIG_SOC_SIFIVE=y
+CONFIG_SOC_THEAD=y
+CONFIG_SMP=y
+CONFIG_VECTOR=y
+CONFIG_VECTOR_0_7=y
+CONFIG_KEXEC=y
+CONFIG_CRASH_DUMP=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_CMA=y
+CONFIG_CMA_DEBUGFS=y
+CONFIG_CMA_AREAS=16
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_BRIDGE=y
+CONFIG_VSOCKETS=y
+# CONFIG_VSOCKETS_LOOPBACK is not set
+CONFIG_VIRTIO_VSOCKETS=y
+CONFIG_NETLINK_DIAG=y
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_RTL3WIRE=y
+CONFIG_CFG80211=y
+CONFIG_RFKILL=y
+CONFIG_NET_9P=y
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_TESTS=m
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_SLRAM=m
+CONFIG_MTD_PHRAM=m
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_LIGHT_DSMART_CARD=y
+CONFIG_EEPROM_AT24=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+CONFIG_VIRTIO_NET=y
+CONFIG_MACB=y
+CONFIG_STMMAC_ETH=y
+CONFIG_DWMAC_LIGHT=y
+CONFIG_MICROSEMI_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_USB_USBNET=m
+# CONFIG_USB_NET_AX8817X is not set
+# CONFIG_USB_NET_AX88179_178A is not set
+# CONFIG_USB_NET_NET1080 is not set
+CONFIG_RTL8723DS=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_GOODIX=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_DW_QUAD=y
+CONFIG_SPI_DESIGNWARE=y
+CONFIG_SPI_DW_MMIO=y
+CONFIG_SPI_SPIDEV=y
+# CONFIG_PTP_1588_CLOCK is not set
+CONFIG_PINCTRL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_SENSORS_MR75203=y
+CONFIG_THERMAL=y
+CONFIG_CPU_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_WATCHDOG=y
+CONFIG_DW_WATCHDOG=y
+CONFIG_LIGHT_PMIC_WATCHDOG=y
+CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
+CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
+CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
+#CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
+CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y
+CONFIG_WATCHDOG_OPEN_TIMEOUT=32
+CONFIG_ABX500_CORE=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_MEDIA_SUPPORT=y
+# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
+# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_ASPEED=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_MEDIA_TUNER_SIMPLE is not set
+# CONFIG_MEDIA_TUNER_TDA18250 is not set
+# CONFIG_MEDIA_TUNER_TDA8290 is not set
+# CONFIG_MEDIA_TUNER_TDA827X is not set
+# CONFIG_MEDIA_TUNER_TDA18271 is not set
+# CONFIG_MEDIA_TUNER_TDA9887 is not set
+# CONFIG_MEDIA_TUNER_TEA5761 is not set
+# CONFIG_MEDIA_TUNER_TEA5767 is not set
+# CONFIG_MEDIA_TUNER_MSI001 is not set
+# CONFIG_MEDIA_TUNER_MT20XX is not set
+# CONFIG_MEDIA_TUNER_MT2060 is not set
+# CONFIG_MEDIA_TUNER_MT2063 is not set
+# CONFIG_MEDIA_TUNER_MT2266 is not set
+# CONFIG_MEDIA_TUNER_MT2131 is not set
+# CONFIG_MEDIA_TUNER_QT1010 is not set
+# CONFIG_MEDIA_TUNER_XC2028 is not set
+# CONFIG_MEDIA_TUNER_XC5000 is not set
+# CONFIG_MEDIA_TUNER_XC4000 is not set
+# CONFIG_MEDIA_TUNER_MXL5005S is not set
+# CONFIG_MEDIA_TUNER_MXL5007T is not set
+# CONFIG_MEDIA_TUNER_MC44S803 is not set
+# CONFIG_MEDIA_TUNER_MAX2165 is not set
+# CONFIG_MEDIA_TUNER_TDA18218 is not set
+# CONFIG_MEDIA_TUNER_FC0011 is not set
+# CONFIG_MEDIA_TUNER_FC0012 is not set
+# CONFIG_MEDIA_TUNER_FC0013 is not set
+# CONFIG_MEDIA_TUNER_TDA18212 is not set
+# CONFIG_MEDIA_TUNER_E4000 is not set
+# CONFIG_MEDIA_TUNER_FC2580 is not set
+# CONFIG_MEDIA_TUNER_M88RS6000T is not set
+# CONFIG_MEDIA_TUNER_TUA9001 is not set
+# CONFIG_MEDIA_TUNER_SI2157 is not set
+# CONFIG_MEDIA_TUNER_IT913X is not set
+# CONFIG_MEDIA_TUNER_R820T is not set
+# CONFIG_MEDIA_TUNER_MXL301RF is not set
+# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
+# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
+CONFIG_DRM=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
+CONFIG_DRM_PANEL_ILI9881D=y
+CONFIG_DRM_VERISILICON=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_THEAD_LIGHT=y
+CONFIG_SND_SOC_AW87519=y
+CONFIG_SND_SOC_BT_SCO=y
+CONFIG_SND_SOC_ES7210=y
+CONFIG_SND_SOC_ES8156=y
+CONFIG_SND_SOC_WM8960=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_AUDIO_GRAPH_CARD=y
+CONFIG_UHID=y
+CONFIG_HID_PID=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_DWC3=m
+# CONFIG_USB_DWC3_OF_SIMPLE is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_ACC=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_EEM=y
+CONFIG_USB_G_NCM=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_G_MULTI=m
+CONFIG_USB_G_MULTI_CDC=y
+CONFIG_USB_ROLE_SWITCH=m
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_XGENE=y
+CONFIG_DMADEVICES=y
+CONFIG_DW_AXI_DMAC=y
+CONFIG_DMATEST=y
+CONFIG_SW_SYNC=y
+CONFIG_UDMABUF=y
+CONFIG_DMABUF_SELFTESTS=m
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_KHV_MMIO=y
+CONFIG_VHOST_NET=y
+CONFIG_VHOST_VSOCK=y
+CONFIG_CLK_LIGHT_FM=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_LIGHT=y
+CONFIG_HWSPINLOCK_LIGHT_TEST=m
+CONFIG_MAILBOX=y
+CONFIG_IIO=y
+CONFIG_IIO_SW_DEVICE=y
+CONFIG_PWM=y
+CONFIG_PWM_LIGHT=y
+CONFIG_NVMEM_THEAD_LIGHT_EFUSE=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_OPTEE_BENCHMARK=y
+CONFIG_LIGHT_GPU_VIV=m
+# CONFIG_LIGHT_NET is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_HUGETLBFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_9P_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_DH=y
+CONFIG_CRYPTO_CURVE25519=y
+CONFIG_CRYPTO_CHACHA20POLY1305=y
+CONFIG_CRYPTO_OFB=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SM3=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_PERNUMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=32
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+# CONFIG_RCU_TRACE is not set
+CONFIG_OVERLAY_FS=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+# CONFIG_SUSPEND is not set
+# CONFIG_PM_SLEEP is not set

+ 310 - 0
arch/riscv/configs/fire_emu_defconfig

@@ -0,0 +1,310 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_CGROUPS=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+# CONFIG_BUG is not set
+CONFIG_BPF_SYSCALL=y
+CONFIG_PERF_EVENTS=y
+CONFIG_FORCE_MAX_ZONEORDER=15
+CONFIG_SOC_SIFIVE=y
+CONFIG_SOC_THEAD=y
+CONFIG_SMP=y
+CONFIG_VECTOR=y
+CONFIG_VECTOR_0_7=y
+CONFIG_KEXEC=y
+CONFIG_CRASH_DUMP=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_CMA=y
+CONFIG_CMA_DEBUGFS=y
+CONFIG_CMA_AREAS=16
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_BRIDGE=y
+CONFIG_VSOCKETS=y
+# CONFIG_VSOCKETS_LOOPBACK is not set
+CONFIG_VIRTIO_VSOCKETS=y
+CONFIG_NETLINK_DIAG=y
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_RTL3WIRE=y
+CONFIG_CFG80211=y
+CONFIG_RFKILL=y
+CONFIG_NET_9P=y
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_TESTS=m
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_SLRAM=m
+CONFIG_MTD_PHRAM=m
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_LIGHT_DSMART_CARD=y
+CONFIG_EEPROM_AT24=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+CONFIG_VIRTIO_NET=y
+CONFIG_MACB=y
+CONFIG_STMMAC_ETH=y
+CONFIG_DWMAC_LIGHT=y
+CONFIG_MICROSEMI_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_USB_USBNET=m
+# CONFIG_USB_NET_AX8817X is not set
+# CONFIG_USB_NET_AX88179_178A is not set
+# CONFIG_USB_NET_NET1080 is not set
+CONFIG_RTL8723DS=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_GOODIX=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_DW_QUAD=y
+CONFIG_SPI_DESIGNWARE=y
+CONFIG_SPI_DW_MMIO=y
+CONFIG_SPI_SPIDEV=y
+# CONFIG_PTP_1588_CLOCK is not set
+CONFIG_PINCTRL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_SENSORS_MR75203=y
+CONFIG_THERMAL=y
+CONFIG_CPU_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_WATCHDOG=y
+CONFIG_DW_WATCHDOG=y
+CONFIG_LIGHT_PMIC_WATCHDOG=y
+CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
+CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
+CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
+#CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
+CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y
+CONFIG_WATCHDOG_OPEN_TIMEOUT=32
+CONFIG_ABX500_CORE=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_MEDIA_SUPPORT=y
+# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
+# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_ASPEED=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_MEDIA_TUNER_SIMPLE is not set
+# CONFIG_MEDIA_TUNER_TDA18250 is not set
+# CONFIG_MEDIA_TUNER_TDA8290 is not set
+# CONFIG_MEDIA_TUNER_TDA827X is not set
+# CONFIG_MEDIA_TUNER_TDA18271 is not set
+# CONFIG_MEDIA_TUNER_TDA9887 is not set
+# CONFIG_MEDIA_TUNER_TEA5761 is not set
+# CONFIG_MEDIA_TUNER_TEA5767 is not set
+# CONFIG_MEDIA_TUNER_MSI001 is not set
+# CONFIG_MEDIA_TUNER_MT20XX is not set
+# CONFIG_MEDIA_TUNER_MT2060 is not set
+# CONFIG_MEDIA_TUNER_MT2063 is not set
+# CONFIG_MEDIA_TUNER_MT2266 is not set
+# CONFIG_MEDIA_TUNER_MT2131 is not set
+# CONFIG_MEDIA_TUNER_QT1010 is not set
+# CONFIG_MEDIA_TUNER_XC2028 is not set
+# CONFIG_MEDIA_TUNER_XC5000 is not set
+# CONFIG_MEDIA_TUNER_XC4000 is not set
+# CONFIG_MEDIA_TUNER_MXL5005S is not set
+# CONFIG_MEDIA_TUNER_MXL5007T is not set
+# CONFIG_MEDIA_TUNER_MC44S803 is not set
+# CONFIG_MEDIA_TUNER_MAX2165 is not set
+# CONFIG_MEDIA_TUNER_TDA18218 is not set
+# CONFIG_MEDIA_TUNER_FC0011 is not set
+# CONFIG_MEDIA_TUNER_FC0012 is not set
+# CONFIG_MEDIA_TUNER_FC0013 is not set
+# CONFIG_MEDIA_TUNER_TDA18212 is not set
+# CONFIG_MEDIA_TUNER_E4000 is not set
+# CONFIG_MEDIA_TUNER_FC2580 is not set
+# CONFIG_MEDIA_TUNER_M88RS6000T is not set
+# CONFIG_MEDIA_TUNER_TUA9001 is not set
+# CONFIG_MEDIA_TUNER_SI2157 is not set
+# CONFIG_MEDIA_TUNER_IT913X is not set
+# CONFIG_MEDIA_TUNER_R820T is not set
+# CONFIG_MEDIA_TUNER_MXL301RF is not set
+# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set
+# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set
+CONFIG_DRM=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
+CONFIG_DRM_PANEL_ILI9881D=y
+CONFIG_DRM_VERISILICON=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_THEAD_LIGHT=y
+CONFIG_SND_SOC_AW87519=y
+CONFIG_SND_SOC_BT_SCO=y
+CONFIG_SND_SOC_ES7210=y
+CONFIG_SND_SOC_ES8156=y
+CONFIG_SND_SOC_WM8960=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_AUDIO_GRAPH_CARD=y
+CONFIG_UHID=y
+CONFIG_HID_PID=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_DWC3=m
+# CONFIG_USB_DWC3_OF_SIMPLE is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_ACC=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_EEM=y
+CONFIG_USB_G_NCM=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_G_MULTI=m
+CONFIG_USB_G_MULTI_CDC=y
+CONFIG_USB_ROLE_SWITCH=m
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_XGENE=y
+CONFIG_DMADEVICES=y
+CONFIG_DW_AXI_DMAC=y
+CONFIG_DMATEST=y
+CONFIG_SW_SYNC=y
+CONFIG_UDMABUF=y
+CONFIG_DMABUF_SELFTESTS=m
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_KHV_MMIO=y
+CONFIG_VHOST_NET=y
+CONFIG_VHOST_VSOCK=y
+CONFIG_CLK_LIGHT_FM=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_LIGHT=y
+CONFIG_HWSPINLOCK_LIGHT_TEST=m
+CONFIG_MAILBOX=y
+CONFIG_IIO=y
+CONFIG_IIO_SW_DEVICE=y
+CONFIG_PWM=y
+CONFIG_PWM_LIGHT=y
+CONFIG_NVMEM_THEAD_LIGHT_EFUSE=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_OPTEE_BENCHMARK=y
+CONFIG_LIGHT_GPU_VIV=m
+# CONFIG_LIGHT_NET is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_HUGETLBFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_9P_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_DH=y
+CONFIG_CRYPTO_CURVE25519=y
+CONFIG_CRYPTO_CHACHA20POLY1305=y
+CONFIG_CRYPTO_OFB=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SM3=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_PERNUMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=32
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+# CONFIG_RCU_TRACE is not set
+CONFIG_OVERLAY_FS=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+# CONFIG_SUSPEND is not set
+# CONFIG_PM_SLEEP is not set

+ 1 - 0
arch/riscv/configs/light_defconfig

@@ -197,6 +197,7 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y
 CONFIG_DRM=y
 CONFIG_DRM_PANEL_SIMPLE=y
 CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
+CONFIG_DRM_PANEL_ILI9881D=y
 CONFIG_DRM_VERISILICON=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_PWM=y

+ 2 - 0
arch/riscv/include/asm/Kbuild

@@ -3,5 +3,7 @@ generic-y += early_ioremap.h
 generic-y += extable.h
 generic-y += flat.h
 generic-y += kvm_para.h
+generic-y += qrwlock.h
+generic-y += qrwlock_types.h
 generic-y += user.h
 generic-y += vmlinux.lds.h

+ 0 - 5
arch/riscv/include/asm/csr.h

@@ -143,11 +143,6 @@
 #define CSR_VTYPE		0xc21
 #define CSR_VLENB		0xc22
 
-#define CSR_SMIR		0x9c0
-#define CSR_SMEL		0x9c1
-#define CSR_SMEH		0x9c2
-#define CSR_SMCIR		0x9c3
-
 #ifdef CONFIG_RISCV_M_MODE
 # define CSR_STATUS	CSR_MSTATUS
 # define CSR_IE		CSR_MIE

+ 62 - 105
arch/riscv/include/asm/spinlock.h

@@ -1,135 +1,92 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2015 Regents of the University of California
- * Copyright (C) 2017 SiFive
- */
-
-#ifndef _ASM_RISCV_SPINLOCK_H
-#define _ASM_RISCV_SPINLOCK_H
-
-#include <linux/kernel.h>
-#include <asm/current.h>
-#include <asm/fence.h>
+/* SPDX-License-Identifier: GPL-2.0 */
 
 /*
- * Simple spin lock operations.  These provide no fairness guarantees.
+ * 'Generic' ticket-lock implementation.
+ *
+ * It relies on atomic_fetch_add() having well defined forward progress
+ * guarantees under contention. If your architecture cannot provide this, stick
+ * to a test-and-set lock.
+ *
+ * It also relies on atomic_fetch_add() being safe vs smp_store_release() on a
+ * sub-word of the value. This is generally true for anything LL/SC although
+ * you'd be hard pressed to find anything useful in architecture specifications
+ * about this. If your architecture cannot do this you might be better off with
+ * a test-and-set.
+ *
+ * It further assumes atomic_*_release() + atomic_*_acquire() is RCpc and hence
+ * uses atomic_fetch_add() which is RCsc to create an RCsc hot path, along with
+ * a full fence after the spin to upgrade the otherwise-RCpc
+ * atomic_cond_read_acquire().
+ *
+ * The implementation uses smp_cond_load_acquire() to spin, so if the
+ * architecture has WFE like instructions to sleep instead of poll for word
+ * modifications be sure to implement that (see ARM64 for example).
+ *
  */
 
-/* FIXME: Replace this with a ticket lock, like MIPS. */
+#ifndef __ASM_GENERIC_SPINLOCK_H
+#define __ASM_GENERIC_SPINLOCK_H
 
-#define arch_spin_is_locked(x)	(READ_ONCE((x)->lock) != 0)
+#include <linux/atomic.h>
+#include <asm/spinlock_types.h>
 
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
+static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
 {
-	smp_store_release(&lock->lock, 0);
+	u32 val = atomic_fetch_add(1<<16, lock);
+	u16 ticket = val >> 16;
+
+	if (ticket == (u16)val)
+		return;
+
+	/*
+	 * atomic_cond_read_acquire() is RCpc, but rather than defining a
+	 * custom cond_read_rcsc() here we just emit a full fence.  We only
+	 * need the prior reads before subsequent writes ordering from
+	 * smb_mb(), but as atomic_cond_read_acquire() just emits reads and we
+	 * have no outstanding writes due to the atomic_fetch_add() the extra
+	 * orderings are free.
+	 */
+	atomic_cond_read_acquire(lock, ticket == (u16)VAL);
+	smp_mb();
 }
 
-static inline int arch_spin_trylock(arch_spinlock_t *lock)
+static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock)
 {
-	int tmp = 1, busy;
+	u32 old = atomic_read(lock);
 
-	__asm__ __volatile__ (
-		"	amoswap.w %0, %2, %1\n"
-		RISCV_ACQUIRE_BARRIER
-		: "=r" (busy), "+A" (lock->lock)
-		: "r" (tmp)
-		: "memory");
+	if ((old >> 16) != (old & 0xffff))
+		return false;
 
-	return !busy;
+	return atomic_try_cmpxchg(lock, &old, old + (1<<16)); /* SC, for RCsc */
 }
 
-static inline void arch_spin_lock(arch_spinlock_t *lock)
+static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
-	while (1) {
-		if (arch_spin_is_locked(lock))
-			continue;
+	u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
+	u32 val = atomic_read(lock);
 
-		if (arch_spin_trylock(lock))
-			break;
-	}
+	smp_store_release(ptr, (u16)val + 1);
 }
 
-/***********************************************************/
-
-static inline void arch_read_lock(arch_rwlock_t *lock)
+static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock)
 {
-	int tmp;
-
-	__asm__ __volatile__(
-		"1:	lr.w	%1, %0\n"
-		"	bltz	%1, 1b\n"
-		"	addi	%1, %1, 1\n"
-		"	sc.w	%1, %1, %0\n"
-		"	bnez	%1, 1b\n"
-		RISCV_ACQUIRE_BARRIER
-		: "+A" (lock->lock), "=&r" (tmp)
-		:: "memory");
-}
+	u32 val = atomic_read(lock);
 
-static inline void arch_write_lock(arch_rwlock_t *lock)
-{
-	int tmp;
-
-	__asm__ __volatile__(
-		"1:	lr.w	%1, %0\n"
-		"	bnez	%1, 1b\n"
-		"	li	%1, -1\n"
-		"	sc.w	%1, %1, %0\n"
-		"	bnez	%1, 1b\n"
-		RISCV_ACQUIRE_BARRIER
-		: "+A" (lock->lock), "=&r" (tmp)
-		:: "memory");
+	return ((val >> 16) != (val & 0xffff));
 }
 
-static inline int arch_read_trylock(arch_rwlock_t *lock)
+static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock)
 {
-	int busy;
-
-	__asm__ __volatile__(
-		"1:	lr.w	%1, %0\n"
-		"	bltz	%1, 1f\n"
-		"	addi	%1, %1, 1\n"
-		"	sc.w	%1, %1, %0\n"
-		"	bnez	%1, 1b\n"
-		RISCV_ACQUIRE_BARRIER
-		"1:\n"
-		: "+A" (lock->lock), "=&r" (busy)
-		:: "memory");
-
-	return !busy;
-}
+	u32 val = atomic_read(lock);
 
-static inline int arch_write_trylock(arch_rwlock_t *lock)
-{
-	int busy;
-
-	__asm__ __volatile__(
-		"1:	lr.w	%1, %0\n"
-		"	bnez	%1, 1f\n"
-		"	li	%1, -1\n"
-		"	sc.w	%1, %1, %0\n"
-		"	bnez	%1, 1b\n"
-		RISCV_ACQUIRE_BARRIER
-		"1:\n"
-		: "+A" (lock->lock), "=&r" (busy)
-		:: "memory");
-
-	return !busy;
+	return (s16)((val >> 16) - (val & 0xffff)) > 1;
 }
 
-static inline void arch_read_unlock(arch_rwlock_t *lock)
+static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
 {
-	__asm__ __volatile__(
-		RISCV_RELEASE_BARRIER
-		"	amoadd.w x0, %1, %0\n"
-		: "+A" (lock->lock)
-		: "r" (-1)
-		: "memory");
+	return !arch_spin_is_locked(&lock);
 }
 
-static inline void arch_write_unlock(arch_rwlock_t *lock)
-{
-	smp_store_release(&lock->lock, 0);
-}
+#include <asm/qrwlock.h>
 
-#endif /* _ASM_RISCV_SPINLOCK_H */
+#endif /* __ASM_GENERIC_SPINLOCK_H */

+ 12 - 20
arch/riscv/include/asm/spinlock_types.h

@@ -1,25 +1,17 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2015 Regents of the University of California
- */
-
-#ifndef _ASM_RISCV_SPINLOCK_TYPES_H
-#define _ASM_RISCV_SPINLOCK_TYPES_H
+/* SPDX-License-Identifier: GPL-2.0 */
 
-#ifndef __LINUX_SPINLOCK_TYPES_H
-# error "please don't include this file directly"
-#endif
+#ifndef __ASM_GENERIC_SPINLOCK_TYPES_H
+#define __ASM_GENERIC_SPINLOCK_TYPES_H
 
-typedef struct {
-	volatile unsigned int lock;
-} arch_spinlock_t;
+#include <linux/types.h>
+typedef atomic_t arch_spinlock_t;
 
-#define __ARCH_SPIN_LOCK_UNLOCKED	{ 0 }
-
-typedef struct {
-	volatile unsigned int lock;
-} arch_rwlock_t;
+/*
+ * qrwlock_types depends on arch_spinlock_t, so we must typedef that before the
+ * include.
+ */
+#include <asm/qrwlock_types.h>
 
-#define __ARCH_RW_LOCK_UNLOCKED		{ 0 }
+#define __ARCH_SPIN_LOCK_UNLOCKED	ATOMIC_INIT(0)
 
-#endif /* _ASM_RISCV_SPINLOCK_TYPES_H */
+#endif /* __ASM_GENERIC_SPINLOCK_TYPES_H */

+ 3 - 19
arch/riscv/include/asm/tlbflush.h

@@ -14,7 +14,7 @@
 static inline void local_flush_tlb_all(void)
 {
 #ifdef CONFIG_NO_SFENCE_VMA
-	csr_write(CSR_SMCIR, 1 << 26);
+	csr_write(0x9c3, 1 << 26);
 #else
 	__asm__ __volatile__ ("sfence.vma" : : : "memory");
 #endif
@@ -24,7 +24,7 @@ static inline void local_flush_tlb_all(void)
 static inline void local_flush_tlb_page(unsigned long addr)
 {
 #ifdef CONFIG_NO_SFENCE_VMA
-	csr_write(CSR_SMCIR, 1 << 26);
+	csr_write(0x9c3, 1 << 26);
 #else
 	__asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory");
 #endif
@@ -58,23 +58,7 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
 static inline void flush_tlb_kernel_range(unsigned long start,
 	unsigned long end)
 {
-#ifdef CONFIG_NO_SFENCE_VMA
-	csr_write(CSR_SMCIR, 1 << 26);
-#else
-	start &= PAGE_MASK;
-	end   += PAGE_SIZE - 1;
-	end   &= PAGE_MASK;
-
-	if ((end - start) > SZ_1M) {
-		flush_tlb_all();
-		return;
-	}
-
-	while (start < end) {
-		__asm__ __volatile__ ("sfence.vma %0" : : "r" (start) : "memory");
-		start += PAGE_SIZE;
-	}
-#endif
+	flush_tlb_all();
 }
 
 #endif /* _ASM_RISCV_TLBFLUSH_H */

+ 1 - 1
arch/riscv/kernel/entry.S

@@ -251,7 +251,7 @@ ret_from_syscall_rejected:
 	andi t0, t0, _TIF_SYSCALL_WORK
 	bnez t0, handle_syscall_trace_exit
 
-ret_from_exception:
+ENTRY(ret_from_exception)
 	REG_L s0, PT_STATUS(sp)
 	csrc CSR_STATUS, SR_IE
 #ifdef CONFIG_TRACE_IRQFLAGS

+ 30 - 10
arch/riscv/kernel/stacktrace.c

@@ -21,8 +21,10 @@ struct stackframe {
 	unsigned long ra;
 };
 
+extern asmlinkage void ret_from_exception(void);
+
 void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs,
-			     bool (*fn)(unsigned long, void *), void *arg)
+			     bool (*fn)(unsigned long, unsigned long, void *), void *arg)
 {
 	unsigned long fp, sp, pc;
 
@@ -46,7 +48,7 @@ void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs,
 		unsigned long low, high;
 		struct stackframe *frame;
 
-		if (unlikely(!__kernel_text_address(pc) || fn(pc, arg)))
+		if (unlikely(!__kernel_text_address(pc) || fn(pc, 0, arg)))
 			break;
 
 		/* Validate frame pointer */
@@ -57,16 +59,29 @@ void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs,
 		/* Unwind stack frame */
 		frame = (struct stackframe *)fp - 1;
 		sp = fp;
-		fp = frame->fp;
-		pc = ftrace_graph_ret_addr(current, NULL, frame->ra,
-					   (unsigned long *)(fp - 8));
+		if (regs && (regs->epc == pc) && (frame->fp & 0x7)) {
+			fp = frame->ra;
+			pc = regs->ra;
+		} else {
+			fp = frame->fp;
+			pc = ftrace_graph_ret_addr(current, NULL, frame->ra,
+						   &frame->ra);
+			if (pc == (unsigned long)ret_from_exception) {
+				if (unlikely(!__kernel_text_address(pc) || fn(pc, sp, arg)))
+					break;
+
+				pc = ((struct pt_regs *)sp)->epc;
+				fp = ((struct pt_regs *)sp)->s0;
+			}
+		}
+
 	}
 }
 
 #else /* !CONFIG_FRAME_POINTER */
 
 void notrace walk_stackframe(struct task_struct *task,
-	struct pt_regs *regs, bool (*fn)(unsigned long, void *), void *arg)
+	struct pt_regs *regs, bool (*fn)(unsigned long, unsigned long, void *), void *arg)
 {
 	unsigned long sp, pc;
 	unsigned long *ksp;
@@ -88,7 +103,7 @@ void notrace walk_stackframe(struct task_struct *task,
 
 	ksp = (unsigned long *)sp;
 	while (!kstack_end(ksp)) {
-		if (__kernel_text_address(pc) && unlikely(fn(pc, arg)))
+		if (__kernel_text_address(pc) && unlikely(fn(pc, 0, arg)))
 			break;
 		pc = (*ksp++) - 0x4;
 	}
@@ -97,11 +112,15 @@ void notrace walk_stackframe(struct task_struct *task,
 #endif /* CONFIG_FRAME_POINTER */
 
 
-static bool print_trace_address(unsigned long pc, void *arg)
+static bool print_trace_address(unsigned long pc, unsigned long regs, void *arg)
 {
 	const char *loglvl = arg;
 
 	print_ip_sym(loglvl, pc);
+
+	if (regs)
+		show_regs((struct pt_regs *)regs);
+
 	return false;
 }
 
@@ -109,9 +128,10 @@ void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl)
 {
 	pr_cont("Call Trace:\n");
 	walk_stackframe(task, NULL, print_trace_address, (void *)loglvl);
+	pr_cont("End Trace.\n");
 }
 
-static bool save_wchan(unsigned long pc, void *arg)
+static bool save_wchan(unsigned long pc, unsigned long regs, void *arg)
 {
 	if (!in_sched_functions(pc)) {
 		unsigned long *p = arg;
@@ -148,7 +168,7 @@ static bool __save_trace(unsigned long pc, void *arg, bool nosched)
 	return (trace->nr_entries >= trace->max_entries);
 }
 
-static bool save_trace(unsigned long pc, void *arg)
+static bool save_trace(unsigned long pc, unsigned long regs, void *arg)
 {
 	return __save_trace(pc, arg, false);
 }

+ 3 - 1
arch/riscv/mm/cacheflush.c

@@ -84,8 +84,10 @@ void flush_icache_pte(pte_t pte)
 {
 	struct page *page = pte_page(pte);
 
-	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+	if (!test_bit(PG_dcache_clean, &page->flags)) {
 		flush_icache_all();
+		set_bit(PG_dcache_clean, &page->flags);
+	}
 }
 #endif /* CONFIG_MMU */
 

+ 35 - 1
arch/riscv/mm/context.c

@@ -56,14 +56,48 @@ void switch_mm(struct mm_struct *prev, struct mm_struct *next,
 	 */
 	cpu = smp_processor_id();
 
-	cpumask_clear_cpu(cpu, mm_cpumask(prev));
 	cpumask_set_cpu(cpu, mm_cpumask(next));
 
 #ifdef CONFIG_MMU
+	__asm__ __volatile__(
+			"jal t0,1f\n\t"
+			"1: \n\t"
+			"jal t0,2f\n\t"
+			"2: \n\t"
+			"jal t0,3f\n\t"
+			"3: \n\t"
+			"jal t0,4f\n\t"
+			"4: \n\t"
+			"jal t0,5f\n\t"
+			"5: \n\t"
+			"jal t0,6f\n\t"
+			"6: \n\t"
+			"jal t0,7f\n\t"
+			"7: \n\t"
+			"jal t0,8f\n\t"
+			"8: \n\t"
+			"jal t0,9f\n\t"
+			"9: \n\t"
+			"jal t0,10f\n\t"
+			"10: \n\t"
+			"jal t0,11f\n\t"
+			"11: \n\t"
+			"jal t0,12f\n\t"
+			"12: \n\t"
+			::: "memory", "t0");
+
 	check_and_switch_context(next, cpu);
 	asid = (next->context.asid.counter & SATP_ASID_MASK)
 		<< SATP_ASID_SHIFT;
 
+	local_flush_tlb_page(0);
+
+	/* flush utlb before setting satp */
+	__asm__ __volatile__(
+			"li t0, 0\n\t"
+			"sfence.vma t0, t0\n\t"
+			::: "memory", "t0");
+
 	csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE | asid);
 #endif
 

+ 0 - 68
arch/riscv/mm/tlbflush.c

@@ -3,73 +3,6 @@
 #include <linux/mm.h>
 #include <linux/smp.h>
 #include <linux/sched.h>
-
-#define XUANTIE
-#ifdef  XUANTIE
-#include <asm/mmu_context.h>
-
-void flush_tlb_all(void)
-{
-#ifdef CONFIG_NO_SFENCE_VMA
-	csr_write(CSR_SMCIR, 1 << 26);
-#else
-	__asm__ __volatile__ ("sfence.vma" : : : "memory");
-#endif
-}
-
-void flush_tlb_mm(struct mm_struct *mm)
-{
-	int newpid = cpu_asid(mm);
-
-#ifdef CONFIG_NO_SFENCE_VMA
-	csr_write(CSR_SMCIR, (1 << 27) | newpid);
-#else
-	__asm__ __volatile__ ("sfence.vma zero, %0"
-				:
-				: "r"(newpid)
-				: "memory");
-#endif
-}
-
-void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
-{
-	int newpid = cpu_asid(vma->vm_mm);
-
-#ifdef CONFIG_NO_SFENCE_VMA
-	csr_write(CSR_SMCIR, (1 << 27) | newpid);
-#else
-	addr &= PAGE_MASK;
-
-	__asm__ __volatile__ ("sfence.vma %0, %1"
-				:
-				: "r"(addr), "r"(newpid)
-				: "memory");
-#endif
-}
-
-void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
-			unsigned long end)
-{
-	unsigned long newpid = cpu_asid(vma->vm_mm);
-
-#ifdef CONFIG_NO_SFENCE_VMA
-	csr_write(CSR_SMCIR, (1 << 27) | newpid);
-#else
-	start &= PAGE_MASK;
-	end   += PAGE_SIZE - 1;
-	end   &= PAGE_MASK;
-
-	while (start < end) {
-		__asm__ __volatile__ ("sfence.vma %0, %1"
-					:
-					: "r"(start), "r"(newpid)
-					: "memory");
-		start += PAGE_SIZE;
-	}
-#endif
-}
-#else
-
 #include <asm/sbi.h>
 
 void flush_tlb_all(void)
@@ -121,4 +54,3 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 {
 	__sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start);
 }
-#endif

+ 0 - 2
drivers/clk/thead/clk-light-fm.c

@@ -608,8 +608,6 @@ static int light_clocks_probe(struct platform_device *pdev)
 
 #ifndef FPGA_EMU
 	/* HW defalut */
-	clk_prepare_enable(clks[CPU_PLL1_FOUTPOSTDIV]);
-	udelay(1);
 	clk_set_parent(clks[C910_CCLK], clks[CPU_PLL1_FOUTPOSTDIV]);
 #else
 	clk_set_parent(clks[C910_CCLK_I0], clks[OSC_24M]);

+ 2 - 2
drivers/clk/thead/gate/visys-gate.c

@@ -80,9 +80,9 @@ static int light_visys_clk_probe(struct platform_device *pdev)
 	gates[LIGHT_CLKGEN_MIPI_CSI0_CFG_CLK] = thead_gate_clk_register("clkgen_mipi_csi0_cfg_clk", NULL,
 									visys_regmap, 0xa0, 8, GATE_NOT_SHARED, NULL, dev);
 	gates[LIGHT_CLKGEN_MIPI_CSI1_CFG_CLK] = thead_gate_clk_register("clkgen_mipi_csi1_cfg_clk", NULL,
-									visys_regmap, 0xa0, 7, GATE_NOT_SHARED, NULL, dev);
-	gates[LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK] = thead_gate_clk_register("clkgen_mipi_csi2_cfg_clk", NULL,
 									visys_regmap, 0xa0, 6, GATE_NOT_SHARED, NULL, dev);
+	gates[LIGHT_CLKGEN_MIPI_CSI2_CFG_CLK] = thead_gate_clk_register("clkgen_mipi_csi2_cfg_clk", NULL,
+									visys_regmap, 0xa0, 7, GATE_NOT_SHARED, NULL, dev);
 	gates[LIGHT_CLKGEN_DW200_CLK_VSE] = thead_gate_clk_register("clkgen_dw200_clk_vse", NULL,
 									visys_regmap, 0xa0, 5, GATE_NOT_SHARED, NULL, dev);
 	gates[LIGHT_CLKGEN_DW200_CLK_DWE] = thead_gate_clk_register("clkgen_dw200_clk_dwe", NULL,

+ 3 - 3
drivers/cpufreq/light-mpw-cpufreq.c

@@ -268,7 +268,7 @@ static int panic_cpufreq_notifier_call(struct notifier_block *nb,
 	struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
 	u32 val = readl(ap_sys_reg);
 
-	pr_debug("[%s,%d]Enter panic_cpufreq_notifier_call\n", __func__, __LINE__);
+	pr_info("enter panic_cpufreq_notifier_call\n");
 
 	/*
 	 * set CPU PLL1's frequency as minimum to compatible voltage
@@ -277,7 +277,7 @@ static int panic_cpufreq_notifier_call(struct notifier_block *nb,
 	if (strcmp(__clk_get_name(clk_get_parent(clks[LIGHT_C910_CCLK].clk)),
 		__clk_get_name(clks[LIGHT_C910_CCLK_I0].clk))) {
 		pr_debug("[%s,%d]\n", __func__, __LINE__);
-
+		clk_prepare_enable(clks[LIGHT_CPU_PLL0_FOUTPOSTDIV].clk);
 		clk_set_rate(clks[LIGHT_CPU_PLL0_FOUTPOSTDIV].clk, policy->min * 1000);
 		udelay(1);
 		clk_set_parent(clks[LIGHT_C910_CCLK].clk, clks[LIGHT_C910_CCLK_I0].clk);
@@ -296,7 +296,7 @@ static int panic_cpufreq_notifier_call(struct notifier_block *nb,
 	clk_set_rate(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk, policy->min * 1000);
 	udelay(1);
 
-	pr_debug("finish to execute cpufreq notifier callback on panic\n");
+	pr_info("finish to execute cpufreq notifier callback on panic\n");
 
 	return 0;
 }

+ 10 - 0
drivers/gpu/drm/panel/Kconfig

@@ -500,4 +500,14 @@ config DRM_PANEL_XINPENG_XPP055C272
 	  Say Y here if you want to enable support for the Xinpeng
 	  XPP055C272 controller for 720x1280 LCD panels with MIPI/RGB/SPI
 	  system interfaces.
+
+config DRM_PANEL_ILI9881D
+	tristate "ILI9881D-based panels"
+	depends on OF
+	depends on DRM_MIPI_DSI
+	depends on BACKLIGHT_CLASS_DEVICE
+	help
+	  Say Y if you want to enable support for panels based on the
+	  ILI9881d controller.
+
 endmenu

+ 1 - 0
drivers/gpu/drm/panel/Makefile

@@ -53,3 +53,4 @@ obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += panel-tpo-tpg110.o
 obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o
 obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o
 obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += panel-xinpeng-xpp055c272.o
+obj-$(CONFIG_DRM_PANEL_ILI9881D) += panel-ili9881d.o

+ 909 - 0
drivers/gpu/drm/panel/panel-ili9881d.c

@@ -0,0 +1,909 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ILI9881D panel driver
+ *
+ * Copyright (c) 2020 Seeed Studio
+ */
+#include "panel-ili9881d.h"
+#include <linux/version.h>
+
+#define ILI9881_PAGE(_page)	DSI_DCS_WRITE(dsi, 0xff, 0x98, 0x81, _page)
+#define IILI9881_COMMAND(_cmd, _data...)		DSI_DCS_WRITE(dsi, _cmd, _data)
+#define DCS_CMD_READ_ID1        0xDA
+
+#define ILI_9881D_I2C_ADAPTER	1
+#define ILI_9881D_I2C_ADDR	0x45
+
+
+#define GOODIX_STATUS_SIZE		2
+#define GOODIX_CONTACT_SIZE		8
+#define GOODIX_BUFFER_STATUS_READY	(((uint32_t)0x01) << 7)//BIT(7)
+#define GOODIX_HAVE_KEY		(((uint32_t)0x01) << 4)//BIT(4)
+
+#define TP_DEFAULT_WIDTH	1280
+#define TP_DEFAULT_HEIGHT	720
+#define TP_MAX_POINTS	5
+#define TP_POLL_INTERVAL	15
+
+static struct i2c_mipi_dsi *ili9881d_mipi_dsi;
+
+static int goodix_ts_read_input_report(struct i2c_mipi_dsi *md, u8 *data)
+{
+	int header = GOODIX_STATUS_SIZE + GOODIX_CONTACT_SIZE;
+	int i, ret, touch_num;
+
+	for (i = 0; i < 2; i++) {
+		ret = i2c_md_read(md, REG_TP_STATUS, data, header);
+		if (ret < 0)
+			return -EIO;
+
+		if (data[0] & GOODIX_BUFFER_STATUS_READY) {
+			touch_num = data[0] & 0x0f;
+			if (touch_num > TP_MAX_POINTS)
+				return -EPROTO;
+
+			if (touch_num > 1) {
+				ret = i2c_md_read(md, REG_TP_POINT, data+header, (touch_num-1)*GOODIX_CONTACT_SIZE);
+				if (ret < 0)
+					return -EIO;
+			}
+			return touch_num;
+		}
+
+		usleep_range(3000, 5000); /* Poll every 3 - 5 ms */
+	}
+
+	/*
+	 * The Goodix panel will send spurious interrupts after a
+	 * 'finger up' event, which will always cause a timeout.
+	 */
+	return -ENOMSG;
+}
+
+//TODO
+//need more work for it's compatibility
+static void x_y_rotate(int *x, int *y)
+{
+	int temp_x, temp_y;
+	int temp;
+
+	if (*x < 0 || *y < 0) {
+		pr_err("%s<%d> parameter error\n", __func__, __LINE__);
+		return;
+	}
+	//1 move rectangle center to (0,0)
+	temp_x = *x - TP_DEFAULT_WIDTH/2;
+	temp_y = *y - TP_DEFAULT_HEIGHT/2;
+
+	//2 rotate the point anti-clockwise for 90 degree
+	temp = temp_x;
+	temp_x = temp_y;
+	temp_y = temp;
+
+	temp_x *= (-1);
+	temp_y *= 1;
+
+	//3 zoom
+	temp_x = temp_x * TP_DEFAULT_WIDTH / TP_DEFAULT_HEIGHT;
+	temp_y = temp_y * TP_DEFAULT_HEIGHT / TP_DEFAULT_WIDTH;
+
+	//4 move rectangle center back to (TP_DEFAULT_WIDTH/2, TP_DEFAULT_HEIGHT/2)
+	temp_x += TP_DEFAULT_WIDTH/2;
+	temp_y += TP_DEFAULT_HEIGHT/2;
+
+	*x = temp_x;
+	*y = temp_y;
+}
+
+static void goodix_ts_report_touch_8b(struct i2c_mipi_dsi *md, u8 *coor_data)
+{
+	struct input_dev *input_dev = md->input;
+	int id = coor_data[7];
+	int input_x = 0;
+	int input_y = 0;
+	int input_w = coor_data[4];
+
+	input_x = coor_data[1];
+	input_x <<= 8;
+	input_x += coor_data[0];
+
+	input_y = coor_data[3];
+	input_y <<= 8;
+	input_y += coor_data[2];
+
+	if (md->tp_point_rotate)
+		x_y_rotate(&input_x, &input_y);
+
+	input_mt_slot(input_dev, id);
+	input_mt_report_slot_state(input_dev, MT_TOOL_FINGER, true);
+	touchscreen_report_pos(input_dev, &md->prop, input_x, input_y, true);
+	input_report_abs(input_dev, ABS_MT_TOUCH_MAJOR, input_w);
+	input_report_abs(input_dev, ABS_MT_WIDTH_MAJOR, input_w);
+}
+
+static void tp_poll_func(struct input_dev *input)
+{
+	struct i2c_mipi_dsi *md = (struct i2c_mipi_dsi *)input_get_drvdata(input);
+	u8  point_data[GOODIX_STATUS_SIZE + TP_MAX_POINTS * GOODIX_CONTACT_SIZE] = { 0 };
+	int touch_num;
+	int i;
+
+	touch_num = goodix_ts_read_input_report(md, point_data);
+	if (touch_num < 0)
+		return;
+
+	for (i = 0; i < touch_num; i++)
+		goodix_ts_report_touch_8b(md, &point_data[GOODIX_STATUS_SIZE + i*GOODIX_CONTACT_SIZE]);
+
+	input_mt_sync_frame(input);
+	input_sync(input);
+}
+
+int tp_init(struct i2c_mipi_dsi *md)
+{
+	struct i2c_client *i2c = md->i2c;
+	struct device *dev = &i2c->dev;
+	struct input_dev *input;
+	int ret;
+
+	input = devm_input_allocate_device(dev);
+	if (!input) {
+		dev_err(dev, "Failed to allocate input device\n");
+		return -ENOMEM;
+	}
+	md->input = input;
+	input_set_drvdata(input, md);
+
+	input->dev.parent = dev;
+	input->name = "seeed-tp";
+	input->id.bustype = BUS_I2C;
+	input->id.vendor = 0x1234;
+	input->id.product = 0x1001;
+	input->id.version = 0x0100;
+
+	input_set_abs_params(input, ABS_MT_WIDTH_MAJOR, 0, 255, 0, 0);
+	input_set_abs_params(input, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0);
+	input_set_abs_params(input, ABS_MT_POSITION_X, 0, TP_DEFAULT_WIDTH, 0, 0);
+	input_set_abs_params(input, ABS_MT_POSITION_Y, 0, TP_DEFAULT_HEIGHT, 0, 0);
+
+	ret = input_mt_init_slots(input, TP_MAX_POINTS, INPUT_MT_DIRECT | INPUT_MT_DROP_UNUSED);
+	if (ret) {
+		dev_err(dev, "could not init mt slots, %d\n", ret);
+		return ret;
+	}
+
+	ret = input_setup_polling(input, tp_poll_func);
+	if (ret) {
+		dev_err(dev, "could not set up polling mode, %d\n", ret);
+		return ret;
+	}
+	input_set_poll_interval(input, TP_POLL_INTERVAL);
+
+	ret = input_register_device(input);
+	if (ret) {
+		dev_err(dev, "could not register input device, %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int tp_deinit(struct i2c_mipi_dsi *md)
+{
+	input_unregister_device(md->input);
+	return 0;
+}
+
+static const struct drm_display_mode ili9881d_modes = {
+	.clock		= 76000,
+
+	.hdisplay	= 800,
+	.hsync_start	= 800 + 60,
+	.hsync_end	= 800 + 60 + 40,
+	.htotal		= 800 + 60 + 40 + 60,
+
+	.vdisplay	= 1280,
+	.vsync_start	= 1280 + 16,
+	.vsync_end	= 1280 + 16 + 8,
+	.vtotal		= 1280 + 16 + 8 + 16,
+
+	.width_mm	= 62,
+	.height_mm	= 110,
+
+	.flags          = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+};
+
+static int ili9881d_get_modes(struct drm_panel *panel, struct drm_connector *connector)
+{
+	struct drm_display_mode *mode;
+
+	mode = drm_mode_duplicate(connector->dev, &ili9881d_modes);
+	if (!mode) {
+		dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
+			mode->hdisplay, mode->vdisplay,
+			drm_mode_vrefresh(mode));
+		return -ENOMEM;
+	}
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+	drm_mode_set_name(mode);
+
+	connector->display_info.width_mm = mode->width_mm;
+	connector->display_info.height_mm = mode->height_mm;
+	drm_mode_probed_add(connector, mode);
+
+	return 1;
+}
+
+static int ili9881d_read_id(struct mipi_dsi_device *dsi, u8 *id1)
+{
+	int ret;
+
+	ret = mipi_dsi_dcs_read(dsi, DCS_CMD_READ_ID1, id1, 1);
+	if (ret < 0) {
+		dev_err(&dsi->dev, "could not read ID1\n");
+		return ret;
+	}
+	dev_info(&dsi->dev, "ID1 : %02x\n", *id1);
+
+	return 0;
+}
+
+static int ili9881d_enable(struct drm_panel *panel)
+{
+	struct mipi_dsi_device *dsi = ili9881d_mipi_dsi->dsi;
+	int ret = 0;
+	u8 id1;
+
+	DBG_FUNC();
+
+	if (!dsi)
+		return -1;
+
+	dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+	ILI9881_PAGE(0x00);
+	mipi_dsi_set_maximum_return_packet_size(dsi, 1);
+
+	ret = ili9881d_read_id(dsi, &id1);
+	if (ret < 0) {
+		dev_info(&dsi->dev, "No LCD connected,pls check your hardware! ret:%d\n", ret);
+		return -ENODEV;
+	}
+
+	ILI9881_PAGE(0x01);
+	IILI9881_COMMAND(0x91,0x00);
+	IILI9881_COMMAND(0x92,0x00);
+	IILI9881_COMMAND(0x93,0x72);
+	IILI9881_COMMAND(0x94,0x00);
+	IILI9881_COMMAND(0x95,0x00);
+	IILI9881_COMMAND(0x96,0x09);
+	IILI9881_COMMAND(0x97,0x00);
+	IILI9881_COMMAND(0x98,0x00);
+
+	IILI9881_COMMAND(0x09,0x01);
+	IILI9881_COMMAND(0x0a,0x00);
+	IILI9881_COMMAND(0x0b,0x00);
+	IILI9881_COMMAND(0x0c,0x01);
+	IILI9881_COMMAND(0x0d,0x00);
+	IILI9881_COMMAND(0x0e,0x00);
+	IILI9881_COMMAND(0x0f,0x1D);
+	IILI9881_COMMAND(0x10,0x1D);
+	IILI9881_COMMAND(0x11,0x00);
+	IILI9881_COMMAND(0x12,0x00);
+	IILI9881_COMMAND(0x13,0x00);
+	IILI9881_COMMAND(0x14,0x00);
+	IILI9881_COMMAND(0x15,0x00);
+	IILI9881_COMMAND(0x16,0x00);
+	IILI9881_COMMAND(0x17,0x00);
+	IILI9881_COMMAND(0x18,0x00);
+	IILI9881_COMMAND(0x19,0x00);
+	IILI9881_COMMAND(0x1a,0x00);
+	IILI9881_COMMAND(0x1b,0x00);
+	IILI9881_COMMAND(0x1c,0x00);
+	IILI9881_COMMAND(0x1d,0x00);
+	IILI9881_COMMAND(0x1e,0xc0);
+	IILI9881_COMMAND(0x1f,0x00);
+	IILI9881_COMMAND(0x20,0x06);
+	IILI9881_COMMAND(0x21,0x02);
+	IILI9881_COMMAND(0x22,0x00);
+	IILI9881_COMMAND(0x23,0x00);
+	IILI9881_COMMAND(0x24,0x00);
+	IILI9881_COMMAND(0x25,0x00);
+	IILI9881_COMMAND(0x26,0x00);
+	IILI9881_COMMAND(0x27,0x00);
+	IILI9881_COMMAND(0x28,0x33);
+	IILI9881_COMMAND(0x29,0x03);
+	IILI9881_COMMAND(0x2a,0x00);
+	IILI9881_COMMAND(0x2b,0x00);
+	IILI9881_COMMAND(0x2c,0x00);
+	IILI9881_COMMAND(0x2d,0x00);
+	IILI9881_COMMAND(0x2e,0x00);
+	IILI9881_COMMAND(0x2f,0x00);
+	IILI9881_COMMAND(0x30,0x00);
+	IILI9881_COMMAND(0x31,0x00);
+	IILI9881_COMMAND(0x32,0x00);
+	IILI9881_COMMAND(0x33,0x00);
+	IILI9881_COMMAND(0x34,0x04);
+	IILI9881_COMMAND(0x35,0x00);
+	IILI9881_COMMAND(0x36,0x00);
+	IILI9881_COMMAND(0x37,0x00);
+	IILI9881_COMMAND(0x38,0x3C);
+	IILI9881_COMMAND(0x39,0x07);
+	IILI9881_COMMAND(0x3a,0x00);
+	IILI9881_COMMAND(0x3b,0x00);
+	IILI9881_COMMAND(0x3c,0x00);
+
+	IILI9881_COMMAND(0x40,0x03);
+	IILI9881_COMMAND(0x41,0x20);
+	IILI9881_COMMAND(0x42,0x00);
+	IILI9881_COMMAND(0x43,0x00);
+	IILI9881_COMMAND(0x44,0x03);
+	IILI9881_COMMAND(0x45,0x00);
+	IILI9881_COMMAND(0x46,0x01);
+	IILI9881_COMMAND(0x47,0x08);
+	IILI9881_COMMAND(0x48,0x00);
+	IILI9881_COMMAND(0x49,0x00);
+	IILI9881_COMMAND(0x4a,0x00);
+	IILI9881_COMMAND(0x4b,0x00);
+
+	// ==== GL[3OUT=
+	IILI9881_COMMAND(0x4c,0x01);
+	IILI9881_COMMAND(0x4d,0x54);
+	IILI9881_COMMAND(0x4e,0x57);
+	IILI9881_COMMAND(0x4f,0x9b);
+	IILI9881_COMMAND(0x50,0xf9);
+	IILI9881_COMMAND(0x51,0x27);
+	IILI9881_COMMAND(0x52,0x2f);
+	IILI9881_COMMAND(0x53,0xf2);
+	IILI9881_COMMAND(0x54,0xff);
+	IILI9881_COMMAND(0x55,0xff);
+	IILI9881_COMMAND(0x56,0xff);
+
+	// ==== GR[3OUT==
+	IILI9881_COMMAND(0x57,0x01);
+	IILI9881_COMMAND(0x58,0x54);
+	IILI9881_COMMAND(0x59,0x46);
+	IILI9881_COMMAND(0x5a,0x8a);
+	IILI9881_COMMAND(0x5b,0xf8);
+	IILI9881_COMMAND(0x5c,0x26);
+	IILI9881_COMMAND(0x5d,0x2f);
+	IILI9881_COMMAND(0x5e,0xf2);
+	IILI9881_COMMAND(0x5f,0xff);
+	IILI9881_COMMAND(0x60,0xff);
+	IILI9881_COMMAND(0x61,0xff);
+
+	IILI9881_COMMAND(0x62,0x06);
+
+	// == GOUT:4]_BWUTL[5:0]==
+	IILI9881_COMMAND(0x63,0x01);
+	IILI9881_COMMAND(0x64,0x00);
+	IILI9881_COMMAND(0x65,0xa4);
+	IILI9881_COMMAND(0x66,0xa5);
+	IILI9881_COMMAND(0x67,0x58);
+	IILI9881_COMMAND(0x68,0x5a);
+	IILI9881_COMMAND(0x69,0x54);
+	IILI9881_COMMAND(0x6a,0x56);
+	IILI9881_COMMAND(0x6b,0x06);
+	IILI9881_COMMAND(0x6c,0xff);
+	IILI9881_COMMAND(0x6d,0x08);
+	IILI9881_COMMAND(0x6e,0x02);
+	IILI9881_COMMAND(0x6f,0xff);
+	IILI9881_COMMAND(0x70,0x02);
+	IILI9881_COMMAND(0x71,0x02);
+	IILI9881_COMMAND(0x72,0xff);
+	IILI9881_COMMAND(0x73,0xff);
+	IILI9881_COMMAND(0x74,0xff);
+	IILI9881_COMMAND(0x75,0xff);
+	IILI9881_COMMAND(0x76,0xff);
+	IILI9881_COMMAND(0x77,0xff);
+	IILI9881_COMMAND(0x78,0xff);
+
+	// == GOUT:4]_BWUTR[5:0]==
+	IILI9881_COMMAND(0x79,0x01);
+	IILI9881_COMMAND(0x7a,0x00);
+	IILI9881_COMMAND(0x7b,0xa4);
+	IILI9881_COMMAND(0x7c,0xa5);
+	IILI9881_COMMAND(0x7d,0x59);
+	IILI9881_COMMAND(0x7e,0x5b);
+	IILI9881_COMMAND(0x7f,0x55);
+	IILI9881_COMMAND(0x80,0x57);
+	IILI9881_COMMAND(0x81,0x07);
+	IILI9881_COMMAND(0x82,0xff);
+	IILI9881_COMMAND(0x83,0x09);
+	IILI9881_COMMAND(0x84,0x02);
+	IILI9881_COMMAND(0x85,0xff);
+	IILI9881_COMMAND(0x86,0x02);
+	IILI9881_COMMAND(0x87,0x02);
+	IILI9881_COMMAND(0x88,0xff);
+	IILI9881_COMMAND(0x89,0xff);
+	IILI9881_COMMAND(0x8a,0xff);
+	IILI9881_COMMAND(0x8b,0xff);
+	IILI9881_COMMAND(0x8c,0xff);
+	IILI9881_COMMAND(0x8d,0xff);
+	IILI9881_COMMAND(0x8e,0xff);
+
+	IILI9881_COMMAND(0x8f,0x00);
+	IILI9881_COMMAND(0x90,0x00);
+
+	IILI9881_COMMAND(0x9d,0x00);
+	IILI9881_COMMAND(0x9e,0x00);
+
+	IILI9881_COMMAND(0xa0,0x35);
+	IILI9881_COMMAND(0xa1,0x00);
+	IILI9881_COMMAND(0xa2,0x00);
+	IILI9881_COMMAND(0xa3,0x00);
+	IILI9881_COMMAND(0xa4,0x00);
+	IILI9881_COMMAND(0xa5,0x00);
+	IILI9881_COMMAND(0xa6,0x08);
+	IILI9881_COMMAND(0xa7,0x00);
+	IILI9881_COMMAND(0xa8,0x00);
+	IILI9881_COMMAND(0xa9,0x00);
+	IILI9881_COMMAND(0xaa,0x00);
+	IILI9881_COMMAND(0xab,0x00);
+	IILI9881_COMMAND(0xac,0x00);
+	IILI9881_COMMAND(0xad,0x00);
+	IILI9881_COMMAND(0xae,0xff);
+	IILI9881_COMMAND(0xaf,0x00);
+	IILI9881_COMMAND(0xb0,0x00);
+
+	ILI9881_PAGE(0x02);
+	IILI9881_COMMAND(0x08,0x11);
+	IILI9881_COMMAND(0x0a,0x0c);
+	IILI9881_COMMAND(0x0f,0x06);
+	IILI9881_COMMAND(0xA0,0x00,0x26,0x35,0x16,0x19,0x2C,0x1F,0x1F,0x96,0x1C,0x28,0x80,0x1A,0x18,0x4C,0x21,0x27,0x55,0x65,0x39);
+	IILI9881_COMMAND(0xC0,0x00,0x26,0x35,0x16,0x19,0x2C,0x1F,0x1F,0x96,0x1C,0x28,0x80,0x1A,0x18,0x4C,0x21,0x27,0x55,0x65,0x39);
+
+	//===== GIP code finish =====//
+	IILI9881_COMMAND(0x4C,0xA4); // PS_EN on ,0x default :A4
+	IILI9881_COMMAND(0x18,0xF4); // SH on ,0x default E4 
+
+	//=========================//
+	ILI9881_PAGE(0x04);
+	IILI9881_COMMAND(0x5D,0xAF); // VREG1 5.5V 
+	IILI9881_COMMAND(0x5E,0xAF); // VREG2 5.5V
+	IILI9881_COMMAND(0x60,0x9B); // VCM1 
+	IILI9881_COMMAND(0x62,0x9B); // VCM2 
+	IILI9881_COMMAND(0x82,0x38); // VREF_VGH_MOD_CLPSEL 16V 
+	IILI9881_COMMAND(0x84,0x38); // VREF_VGH_DC 16V     
+	IILI9881_COMMAND(0x86,0x18); // VREF_VGL_CLPSEL -10V       
+	IILI9881_COMMAND(0x66,0xC4); // VGH_AC x4 ,0xdefault :04
+	IILI9881_COMMAND(0xC1,0xF0); // VGH_DC x4 ,0xdefault :70
+	IILI9881_COMMAND(0x70,0x60);
+	IILI9881_COMMAND(0x71,0x00);
+
+	//=========================//
+	IILI9881_COMMAND(0x5B,0x33); // vcore_sel Voltage
+	IILI9881_COMMAND(0x6C,0x10); // vcore bias L
+	IILI9881_COMMAND(0x77,0x03); // vcore_sel Voltage
+	IILI9881_COMMAND(0x7B,0x02); // vcore bias R
+
+	//=========================//
+	ILI9881_PAGE(0x01);
+	IILI9881_COMMAND(0xF0,0x00); // 1280 Gate NL
+	IILI9881_COMMAND(0xF1,0xC8); // 1280 Gate NL
+
+	ILI9881_PAGE(0x05);
+	IILI9881_COMMAND(0x22,0x3A); // RGB to BGR
+
+	ILI9881_PAGE(0x00);
+	IILI9881_COMMAND(0x35,0x00);
+
+	IILI9881_COMMAND(0x11);
+	msleep(120);
+	IILI9881_COMMAND(0x29);
+
+	return 0;
+}
+
+static const struct drm_panel_funcs ili9881d_funcs = {
+	.get_modes = ili9881d_get_modes,
+	.enable = ili9881d_enable,
+};
+
+static void ili9881d_set_dsi(struct mipi_dsi_device *dsi)
+{
+	dsi->mode_flags = (MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM);
+	dsi->format = MIPI_DSI_FMT_RGB888;
+	dsi->lanes = 4;
+}
+
+const struct panel_data ili9881d_data = {
+	.set_dsi = ili9881d_set_dsi,
+	.funcs = &ili9881d_funcs,
+};
+
+static int i2c_md_read(struct i2c_mipi_dsi *md, u8 reg, u8 *buf, int len)
+{
+	struct i2c_client *client = md->i2c;
+	struct i2c_msg msgs[1];
+	u8 addr_buf[1] = { reg };
+	u8 data_buf[1] = { 0, };
+	int ret;
+
+	mutex_lock(&md->mutex);
+
+	/* Write register address */
+	msgs[0].addr = client->addr;
+	msgs[0].flags = 0;
+	msgs[0].len = ARRAY_SIZE(addr_buf);
+	msgs[0].buf = addr_buf;
+
+	ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
+	if (ret != ARRAY_SIZE(msgs)) {
+		mutex_unlock(&md->mutex);
+		return -EIO;
+	}
+
+	usleep_range(1000, 1500);
+
+	/* Read data from register */
+	msgs[0].addr = client->addr;
+	msgs[0].flags = I2C_M_RD;
+	if (buf == NULL) {
+		msgs[0].len = 1;
+		msgs[0].buf = data_buf;
+	} else {
+		msgs[0].len = len;
+		msgs[0].buf = buf;
+	}
+
+	ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
+	if (ret != ARRAY_SIZE(msgs)) {
+		mutex_unlock(&md->mutex);
+		return -EIO;
+	}
+	mutex_unlock(&md->mutex);
+
+	if (buf == NULL)
+		return data_buf[0];
+	else
+		return ret;
+}
+
+static void i2c_md_write(struct i2c_mipi_dsi *md, u8 reg, u8 val)
+{
+	struct i2c_client *client = md->i2c;
+	int ret;
+
+	mutex_lock(&md->mutex);
+	ret = i2c_smbus_write_byte_data(client, reg, val);
+	if (ret)
+		dev_err(&client->dev, "I2C write failed: %d\n", ret);
+
+	usleep_range(1000, 1500);
+	mutex_unlock(&md->mutex);
+}
+
+/* panel_funcs */
+static int panel_prepare(struct drm_panel *panel)
+{
+	int ret = 0;
+	struct i2c_mipi_dsi *md = panel_to_md(panel);
+	const struct drm_panel_funcs *funcs = md->panel_data->funcs;
+
+	DBG_FUNC("");
+
+	/* i2c */
+	/* reset pin */
+	i2c_md_write(md, REG_LCD_RST, 0);
+	msleep(20);
+	i2c_md_write(md, REG_LCD_RST, 1);
+	msleep(20);
+
+	/* panel */
+	if (funcs && funcs->prepare) {
+		ret = funcs->prepare(panel);
+		if (ret < 0) {
+			i2c_md_write(md, REG_POWERON, 0);
+			i2c_md_write(md, REG_LCD_RST, 0);
+			i2c_md_write(md, REG_PWM, 0);
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+static int panel_unprepare(struct drm_panel *panel)
+{
+	int ret = 0;
+	struct i2c_mipi_dsi *md = panel_to_md(panel);
+	const struct drm_panel_funcs *funcs = md->panel_data->funcs;
+
+	DBG_FUNC("");
+	if (funcs && funcs->unprepare) {
+		ret = funcs->unprepare(panel);
+		if (ret < 0)
+			return ret;
+	}
+
+	return ret;
+}
+
+static int panel_enable(struct drm_panel *panel)
+{
+	int ret = 0;
+	struct i2c_mipi_dsi *md = panel_to_md(panel);
+	const struct drm_panel_funcs *funcs = md->panel_data->funcs;
+
+	DBG_FUNC("");
+	/* panel */
+	if (funcs && funcs->enable) {
+		ret = funcs->enable(panel);
+		if (ret < 0)
+			return ret;
+	}
+
+	/* i2c */
+	i2c_md_write(md, REG_PWM, md->brightness);
+
+	return ret;
+}
+
+static int panel_disable(struct drm_panel *panel)
+{
+	int ret = 0;
+	struct i2c_mipi_dsi *md = panel_to_md(panel);
+	const struct drm_panel_funcs *funcs = md->panel_data->funcs;
+
+	DBG_FUNC("");
+	/* i2c */
+	i2c_md_write(md, REG_PWM, 0);
+	i2c_md_write(md, REG_LCD_RST, 0);
+
+	/* panel */
+	if (funcs && funcs->disable) {
+		ret = funcs->disable(panel);
+		if (ret < 0)
+			return ret;
+	}
+
+	return ret;
+}
+
+static int panel_get_modes(struct drm_panel *panel, struct drm_connector *connector)
+{
+	int ret = 0;
+	struct i2c_mipi_dsi *md = panel_to_md(panel);
+	const struct drm_panel_funcs *funcs = md->panel_data->funcs;
+
+	if (funcs && funcs->get_modes) {
+		ret = funcs->get_modes(panel, connector);
+		if (ret < 0)
+			return ret;
+	}
+
+	return ret;
+}
+
+static const struct drm_panel_funcs panel_funcs = {
+	.prepare = panel_prepare,
+	.unprepare = panel_unprepare,
+	.enable = panel_enable,
+	.disable = panel_disable,
+	.get_modes = panel_get_modes,
+};
+
+/* backlight */
+static int backlight_update(struct backlight_device *bd)
+{
+	struct i2c_mipi_dsi *md = bl_get_data(bd);
+	int brightness = bd->props.brightness;
+
+	if (bd->props.power != FB_BLANK_UNBLANK ||
+		bd->props.fb_blank != FB_BLANK_UNBLANK ||
+		(bd->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))) {
+			brightness = 0;
+		}
+
+	md->brightness = brightness;
+	i2c_md_write(md, REG_PWM, brightness);
+
+	return 0;
+}
+
+static const struct backlight_ops backlight_ops = {
+	.options = BL_CORE_SUSPENDRESUME,
+	.update_status	= backlight_update,
+};
+
+static int backlight_init(struct i2c_mipi_dsi *md)
+{
+	struct device *dev = &md->i2c->dev;
+	struct backlight_properties props;
+	struct backlight_device *bd;
+
+	memset(&props, 0, sizeof(props));
+	props.type = BACKLIGHT_RAW;
+	props.max_brightness = 255;
+	bd = devm_backlight_device_register(dev, dev_name(dev),
+					dev, md, &backlight_ops,
+					&props);
+	if (IS_ERR(bd)) {
+		dev_err(dev, "failed to register backlight\n");
+		return PTR_ERR(bd);
+	}
+
+	bd->props.brightness = 255;
+	backlight_update_status(bd);
+
+	return 0;
+}
+
+static int i2c_md_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+	struct device *dev = &i2c->dev;
+	struct i2c_mipi_dsi *md = ili9881d_mipi_dsi;
+	int ret = 0;
+
+	DBG_FUNC("start");
+
+	i2c_set_clientdata(i2c, md);
+	mutex_init(&md->mutex);
+	md->i2c = i2c;
+
+	md->panel_data = &ili9881d_data;
+	if (!md->panel_data) {
+		dev_err(dev, "No valid panel data.\n");
+		return -ENODEV;
+	}
+
+	ret = i2c_md_read(md, REG_ID, NULL, 0);
+	if (ret != 0xC3) {
+		dev_err(dev, "Unknown chip id: 0x%02x\n", ret);
+		return -ENODEV;
+	}
+	dev_info(dev, "I2C Address:0x%x read id: 0x%x\n", i2c->addr, ret);
+
+	/* Turn on */
+	i2c_md_write(md, REG_POWERON, 1);
+
+	DBG_FUNC("finished.");
+
+	return 0;
+}
+
+static int i2c_md_remove(struct i2c_client *i2c)
+{
+	struct i2c_mipi_dsi *md = i2c_get_clientdata(i2c);
+
+	DBG_FUNC();
+	tp_deinit(md);
+
+	/* Turn off power */
+	i2c_md_write(md, REG_POWERON, 0);
+	i2c_md_write(md, REG_LCD_RST, 0);
+	i2c_md_write(md, REG_PWM, 0);
+
+	mipi_dsi_detach(md->dsi);
+	drm_panel_remove(&md->panel);
+
+	return 0;
+}
+
+static void i2c_md_shutdown(struct i2c_client *i2c)
+{
+	struct i2c_mipi_dsi *md = i2c_get_clientdata(i2c);
+
+	DBG_FUNC();
+	tp_deinit(md);
+
+	/* Turn off power */
+	i2c_md_write(md, REG_POWERON, 0);
+	i2c_md_write(md, REG_LCD_RST, 0);
+	i2c_md_write(md, REG_PWM, 0);
+
+	mipi_dsi_detach(md->dsi);
+	drm_panel_remove(&md->panel);
+}
+
+static const struct of_device_id i2c_md_of_ids[] = {
+	{
+		.compatible = "ili9881d",
+	},
+	{ }
+};
+MODULE_DEVICE_TABLE(of, i2c_md_of_ids);
+
+static struct i2c_driver i2c_md_driver = {
+	.driver = {
+		.name = "i2c_mipi_dsi",
+		.of_match_table = i2c_md_of_ids,
+	},
+	.probe = i2c_md_probe,
+	.remove = i2c_md_remove,
+	.shutdown = i2c_md_shutdown,
+};
+
+static int ili9881d_hack_create_device(void)
+{
+	struct i2c_adapter *adapter;
+	struct i2c_client *client;
+	struct i2c_board_info info = {
+		.type = "ili9881d",
+		.addr = ILI_9881D_I2C_ADDR,
+	};
+
+	adapter = i2c_get_adapter(ILI_9881D_I2C_ADAPTER);
+	if (!adapter) {
+		pr_err("%s: i2c_get_adapter(%d) failed\n", __func__,
+			ILI_9881D_I2C_ADAPTER);
+		return -EINVAL;
+	}
+
+	client = i2c_new_client_device(adapter, &info);
+	if (IS_ERR(client)) {
+		pr_err("%s: creating I2C device failed\n", __func__);
+		i2c_put_adapter(adapter);
+		return PTR_ERR(client);
+	}
+
+	return 0;
+}
+
+static int ili9881d_dsi_probe(struct mipi_dsi_device *dsi)
+{
+	int ret;
+	struct i2c_mipi_dsi *ctx;
+
+	ctx = devm_kzalloc(&dsi->dev, sizeof(*ctx), GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+	ili9881d_mipi_dsi = ctx;
+
+	ili9881d_hack_create_device();
+	ret = i2c_add_driver(&i2c_md_driver);
+	if (ret < 0) {
+		dev_err(&dsi->dev, "i2c_add_driver ret:%d\n", ret);
+		return ret;
+	}
+
+	mipi_dsi_set_drvdata(dsi, ctx);
+	ctx->dsi = dsi;
+
+	ctx->panel_data->set_dsi(ctx->dsi);
+	drm_panel_init(&ctx->panel, &dsi->dev, &panel_funcs, DRM_MODE_CONNECTOR_DSI);
+	drm_panel_add(&ctx->panel);
+
+	tp_init(ctx);
+	backlight_init(ctx);
+
+	ret = device_property_read_u32(&dsi->dev, "mcu_auto_reset_enable", &ctx->mcu_auto_reset);
+	if (ret < 0)
+		dev_err(&dsi->dev, "Can't get the data of mcu_auto_reset!\n");
+	i2c_md_write(ctx, REG_MCU_AUTO_RESET, (ctx->mcu_auto_reset&0xff));
+
+	ret = device_property_read_u32(&dsi->dev, "tp_point_rotate", &ctx->tp_point_rotate);
+	if (ret < 0)
+		dev_err(&dsi->dev, "Can't get the data of tp_point_rotate!\n");
+
+	return mipi_dsi_attach(dsi);
+}
+
+static int ili9881d_dsi_remove(struct mipi_dsi_device *dsi)
+{
+	struct i2c_mipi_dsi *ctx = mipi_dsi_get_drvdata(dsi);
+
+	mipi_dsi_detach(dsi);
+	drm_panel_remove(&ctx->panel);
+
+	return 0;
+}
+
+static const struct of_device_id ili9881d_of_match[] = {
+	{ .compatible = "i2c_dsi,ili9881d", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, ili9881d_of_match);
+
+static struct mipi_dsi_driver ili9881d_dsi_driver = {
+	.probe		= ili9881d_dsi_probe,
+	.remove		= ili9881d_dsi_remove,
+	.driver = {
+		.name		= "ili9881d-dsi",
+		.of_match_table	= ili9881d_of_match,
+	},
+};
+module_mipi_dsi_driver(ili9881d_dsi_driver);
+
+MODULE_DESCRIPTION("Ilitek ILI9881D Controller Driver");
+MODULE_LICENSE("GPL v2");

+ 128 - 0
drivers/gpu/drm/panel/panel-ili9881d.h

@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * mipi_dsi.h - MIPI dsi module
+ *
+ * Copyright (c) 2020 Seeed Studio
+ *
+ * I2C slave address: 0x45
+ */
+
+#ifndef __MIPI_DSI_H__
+#define __MIPI_DSI_H__
+
+
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/pm.h>
+
+#include <drm/drm_crtc.h>
+#include <drm/drm_device.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_modes.h>
+
+#include <video/mipi_display.h>
+
+#include <linux/input.h>
+#include <linux/input/mt.h>
+#include <linux/input/touchscreen.h>
+
+
+#ifdef I2C_DSI_DBG
+#define DBG_FUNC(format, x...)		printk(KERN_INFO "[DSI]%s:" format"\n", __func__, ##x)
+#define DBG_PRINT(format, x...)		printk(KERN_INFO "[DSI]" format"\n", ##x)
+#else
+#define DBG_FUNC(format, x...)
+#define DBG_PRINT(format, x...)
+#endif
+
+#define DSI_DRIVER_NAME		        "i2c_mipi_dsi"
+
+/* i2c: commands */
+enum REG_ADDR {
+	REG_ID = 0x80,
+	REG_PORTA,	/* BIT(2) for horizontal flip, BIT(3) for vertical flip */
+	REG_PORTB,  // --
+	REG_PORTC,
+	REG_PORTD,
+	REG_POWERON,// --
+	REG_PWM,    // --
+	REG_DDRA,
+	REG_DDRB,
+	REG_DDRC,
+	REG_DDRD,
+	REG_TEST,
+	REG_WR_ADDRL,
+	REG_WR_ADDRH,
+	REG_READH,
+	REG_READL,
+	REG_WRITEH,
+	REG_WRITEL,
+	REG_ID2,
+
+	REG_LCD_RST,
+	REG_TP_RST,
+	REG_TP_STATUS,
+	REG_TP_POINT,
+	REG_TP_VERSION,
+	REG_ADC1,
+	REG_ADC2,
+	REG_MCU_AUTO_RESET,
+
+	REG_MAX
+};
+
+#define DSI_DCS_WRITE(dsi, seq...)		\
+	{									\
+		int ret = 0;					\
+		const u8 d[] = { seq };			\
+		ret = mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d));	\
+		if (ret < 0)		\
+			return ret;		\
+	}
+
+struct panel_data {
+	void (*set_dsi)(struct mipi_dsi_device *dsi);
+	const struct drm_panel_funcs *funcs;
+};
+
+struct i2c_mipi_dsi {
+	struct i2c_client *i2c;
+	struct mutex mutex;
+
+	// panel
+	struct drm_panel panel;
+	struct panel_data *panel_data;
+
+	// dsi
+	struct mipi_dsi_device *dsi;
+
+	// tp
+	struct input_dev *input;
+	struct touchscreen_properties prop;
+	uint32_t tp_point_rotate;
+
+	// backlight
+	int brightness;
+
+	// mcu auto reset enable when the tp driver is not working
+	uint32_t mcu_auto_reset;
+};
+#define panel_to_md(_p)	container_of(_p, struct i2c_mipi_dsi, panel)
+
+static int i2c_md_read(struct i2c_mipi_dsi *md, u8 reg, u8 *buf, int len);
+
+#endif /*End of header guard macro */

+ 1 - 0
drivers/i2c/busses/i2c-designware-core.h

@@ -107,6 +107,7 @@
 
 #define DW_IC_STATUS_ACTIVITY		0x1
 #define DW_IC_STATUS_TFE		BIT(2)
+#define DW_IC_STATUS_RFNE               BIT(3)
 #define DW_IC_STATUS_MASTER_ACTIVITY	BIT(5)
 #define DW_IC_STATUS_SLAVE_ACTIVITY	BIT(6)
 

+ 6 - 2
drivers/i2c/busses/i2c-designware-master.c

@@ -613,7 +613,7 @@ static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
  */
 static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
 {
-	u32 stat;
+	u32 stat, status;
 
 	stat = i2c_dw_read_clear_intrbits(dev);
 	if (stat & DW_IC_INTR_TX_ABRT) {
@@ -641,7 +641,11 @@ static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
 	 */
 
 tx_aborted:
-	if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
+	regmap_read(dev->map, DW_IC_STATUS, &status);
+	if ((stat & DW_IC_INTR_TX_ABRT) || dev->msg_err ||
+			((status & DW_IC_STATUS_TFE) &&
+			 (!(status & DW_IC_STATUS_RFNE)) &&
+			 (!(status & DW_IC_STATUS_MASTER_ACTIVITY))))
 		complete(&dev->cmd_complete);
 	else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
 		/* Workaround to trigger pending interrupt */

+ 126 - 0
drivers/nvmem/light-efuse.c

@@ -37,6 +37,7 @@
 #define SHADOW_RDATA6   0xd8
 #define SHADOW_RDATA7   0xdc
 
+#define TEE_SYS_EFUSE_LC_PRELD_OFF	0x64
 #define TEE_SYS_EFUSE_DBG_KEY1_OFF	0x70
 #define ENABLE_DFT_FUNC_MASK		GENMASK(3, 0)
 #define ENABLE_DFT_FUNC			0x5
@@ -837,14 +838,139 @@ static ssize_t rip_lc_store(struct device *dev,
 	return ret < 0 ? ret : count;
 }
 
+static ssize_t lc_preld_show(struct device *dev,
+			     struct device_attribute *attr, char *buf)
+{
+	struct light_efuse_priv *priv = dev_get_drvdata(dev);
+	int ret;
+	u32 data;
+
+	ret = regmap_read(priv->teesys_regs, TEE_SYS_EFUSE_LC_PRELD_OFF, &data);
+	if (ret) {
+		dev_err(dev, "failed to read data from LC_PRELD area\n");
+		return ret;
+	}
+
+	return sprintf(buf, "0x%08x\n", data);
+}
+
+static ssize_t update_lc_store(struct device *dev,
+			       struct device_attribute *attr,
+			       const char *buf, size_t count)
+{
+	struct light_efuse_priv *priv = dev_get_drvdata(dev);
+	int ret;
+	u32 value, data;
+	const char *p, *life_cycle = buf;
+	int len;
+
+	p = memchr(buf, '\n', count);
+	len = p ? p - buf : count;
+
+	dev_dbg(dev, "life_cycle: %s, buf: %s, len: %d\n", life_cycle, buf, len);
+
+	if (!strncmp(life_cycle, "LC_RMA", len)) {
+		/* If target life cycle is RMA, open permission in teesystem regs */
+		ret = regmap_read(priv->teesys_regs,
+				  TEE_SYS_EFUSE_DBG_KEY1_OFF,
+				  &data); /* Register from tee system */
+		if (ret) {
+			dev_err(dev, "failed to read data from DBG_KEY1 area\n");
+			return ret;
+		}
+
+		data &= ~0xf;
+		data |= 0x5;
+		ret = regmap_write(priv->teesys_regs,
+				   TEE_SYS_EFUSE_DBG_KEY1_OFF,
+				   data);
+		if (ret) {
+			dev_err(dev, "failed to write data to DBG_KEY1 area\n");
+			return ret;
+		}
+
+		value = 0x1A946F9B;
+	} else if (!strncmp(life_cycle, "LC_OEM", len))
+		value = 0x64EA9B8E;
+	else if (!strncmp(life_cycle, "LC_PRO", len))
+		value = 0xB0E047A8;
+	else if (!strncmp(life_cycle, "LC_DEV", len))
+		value = 0x59DD3BDF;
+	else if (!strncmp(life_cycle, "LC_RIP", len))
+		value = 0xEE45E8A7;
+	else if (!strncmp(life_cycle, "LC_KILL_KEY1", len))
+		value = 0x7D8E9CA1;
+	else if (!strncmp(life_cycle, "LC_KILL_KEY0", len))
+		value = 0xC29F604B;
+	else {
+		dev_err(dev, "invalid life cycle type!\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Check permission:
+	 * Check it every time to avoid wp0~3 are changed somewhere
+	 */
+	efuse_permission_magic_config(priv->base, cmd_perm_magic_num, CMD_UPDATE_LC);
+
+	/* Config life cycle */
+	efuse_life_cycle_para_config(priv->base, value);
+
+	/* set command */
+	ret = efuse_cmd_start(priv->base, CON_CMD_UP_LC);
+	if (ret)
+		goto exit;
+
+	/* Wait controller completed */
+	ret = efuse_idle_check(priv->base);
+
+exit:
+	/* Check status, if there has error, reort and clear status */
+	ret |= efuse_status_check(priv->base);
+	if (ret)
+		dev_err(dev, "error occurs while starting write\n");
+
+	efuse_data_clear(priv->base);
+
+	if (strncmp(life_cycle, "LC_RMA", len))
+		goto out;
+
+	dev_info(dev, "set LC_RMA life cycle\n");
+	/* If target life cycle is RMA, close permission in teesystem regs */
+	ret = regmap_read(priv->teesys_regs,
+			  TEE_SYS_EFUSE_DBG_KEY1_OFF,
+			  &data); /* Register from tee system */
+	if (ret) {
+		dev_err(dev, "failed to read data from DBG_KEY1 area\n");
+		return ret;
+	}
+
+	data &= ~0xf;
+	data |= 0xa;
+	ret = regmap_write(priv->teesys_regs,
+			   TEE_SYS_EFUSE_DBG_KEY1_OFF,
+			   data);
+	if (ret) {
+		dev_err(dev, "failed to write data to DBG_KEY1 area\n");
+		return ret;
+	}
+
+out:
+	return ret < 0 ? ret : count;
+}
+
 static DEVICE_ATTR_WO(rma_lc);
 static DEVICE_ATTR_WO(rip_lc);
 static DEVICE_ATTR_RW(efuse_nvmem);
+static DEVICE_ATTR_RO(lc_preld);
+static DEVICE_ATTR_WO(update_lc);
 
 static struct attribute *light_efuse_sysfs_entries[] = {
 	&dev_attr_efuse_nvmem.attr,
 	&dev_attr_rip_lc.attr,
 	&dev_attr_rma_lc.attr,
+	&dev_attr_lc_preld.attr,
+	&dev_attr_update_lc.attr,
 	NULL
 };
 

+ 0 - 12
include/asm-generic/spinlock.h

@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_GENERIC_SPINLOCK_H
-#define __ASM_GENERIC_SPINLOCK_H
-/*
- * You need to implement asm/spinlock.h for SMP support. The generic
- * version does not handle SMP.
- */
-#ifdef CONFIG_SMP
-#error need an architecture specific asm/spinlock.h
-#endif
-
-#endif /* __ASM_GENERIC_SPINLOCK_H */