light-beagle-ref.dts 46 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2021 Alibaba Group Holding Limited.
  4. */
  5. /dts-v1/;
  6. #include "light.dtsi"
  7. #include <dt-bindings/input/linux-event-codes.h>
  8. #include <dt-bindings/gpio/gpio.h>
  9. #include "light-vi-devices.dtsi"
  10. / {
  11. model = "T-HEAD Light val board";
  12. compatible = "thead,light-val", "thead,light";
  13. memory@0 {
  14. device_type = "memory";
  15. reg = <0x0 0x00000000 0x0 0x80000000>;
  16. };
  17. chosen {
  18. bootargs = "console=ttyS0,115200 crashkernel=256M-:128M earlycon clk_ignore_unused sram=0xffe0000000,0x180000";
  19. stdout-path = "serial0:115200n8";
  20. };
  21. leds {
  22. compatible = "gpio-leds";
  23. status = "disabled";
  24. led0 {
  25. label = "SYS_STATUS";
  26. gpios = <&gpio1_porta 15 0>; /* GPIO_ACTIVE_HIGH: 0 */
  27. default-state = "off";
  28. };
  29. };
  30. display-subsystem {
  31. status = "okay";
  32. };
  33. lcd0_backlight: pwm-backlight@0 {
  34. compatible = "pwm-backlight";
  35. pwms = <&pwm 0 5000000>;
  36. brightness-levels = <0 4 8 16 32 64 128 255>;
  37. default-brightness-level = <7>;
  38. };
  39. light_iopmp: iopmp {
  40. compatible = "thead,light-iopmp";
  41. /* config#1: multiple valid regions */
  42. iopmp_emmc: IOPMP_EMMC {
  43. regions = <0x000000 0x100000>,
  44. <0x100000 0x200000>;
  45. attr = <0xFFFFFFFF>;
  46. dummy_slave= <0x800000>;
  47. };
  48. /* config#2: iopmp bypass */
  49. iopmp_sdio0: IOPMP_SDIO0 {
  50. bypass_en;
  51. };
  52. /* config#3: iopmp default region set */
  53. iopmp_sdio1: IOPMP_SDIO1 {
  54. attr = <0xFFFFFFFF>;
  55. is_default_region;
  56. };
  57. iopmp_usb0: IOPMP_USB0 {
  58. attr = <0xFFFFFFFF>;
  59. is_default_region;
  60. };
  61. iopmp_ao: IOPMP_AO {
  62. is_default_region;
  63. };
  64. iopmp_aud: IOPMP_AUD {
  65. is_default_region;
  66. };
  67. iopmp_chip_dbg: IOPMP_CHIP_DBG {
  68. is_default_region;
  69. };
  70. iopmp_eip120i: IOPMP_EIP120I {
  71. is_default_region;
  72. };
  73. iopmp_eip120ii: IOPMP_EIP120II {
  74. is_default_region;
  75. };
  76. iopmp_eip120iii: IOPMP_EIP120III {
  77. is_default_region;
  78. };
  79. iopmp_isp0: IOPMP_ISP0 {
  80. is_default_region;
  81. };
  82. iopmp_isp1: IOPMP_ISP1 {
  83. is_default_region;
  84. };
  85. iopmp_dw200: IOPMP_DW200 {
  86. is_default_region;
  87. };
  88. iopmp_vipre: IOPMP_VIPRE {
  89. is_default_region;
  90. };
  91. iopmp_venc: IOPMP_VENC {
  92. is_default_region;
  93. };
  94. iopmp_vdec: IOPMP_VDEC {
  95. is_default_region;
  96. };
  97. iopmp_g2d: IOPMP_G2D {
  98. is_default_region;
  99. };
  100. iopmp_fce: IOPMP_FCE {
  101. is_default_region;
  102. };
  103. iopmp_npu: IOPMP_NPU {
  104. is_default_region;
  105. };
  106. iopmp0_dpu: IOPMP0_DPU {
  107. bypass_en;
  108. };
  109. iopmp1_dpu: IOPMP1_DPU {
  110. bypass_en;
  111. };
  112. iopmp_gpu: IOPMP_GPU {
  113. is_default_region;
  114. };
  115. iopmp_gmac1: IOPMP_GMAC1 {
  116. is_default_region;
  117. };
  118. iopmp_gmac2: IOPMP_GMAC2 {
  119. is_default_region;
  120. };
  121. iopmp_dmac: IOPMP_DMAC {
  122. is_default_region;
  123. };
  124. iopmp_tee_dmac: IOPMP_TEE_DMAC {
  125. is_default_region;
  126. };
  127. iopmp_dsp0: IOPMP_DSP0 {
  128. is_default_region;
  129. };
  130. iopmp_dsp1: IOPMP_DSP1 {
  131. is_default_region;
  132. };
  133. };
  134. mbox_910t_client1: mbox_910t_client1 {
  135. compatible = "thead,light-mbox-client";
  136. mbox-names = "902";
  137. mboxes = <&mbox_910t 1 0>;
  138. status = "disabled";
  139. };
  140. mbox_910t_client2: mbox_910t_client2 {
  141. compatible = "thead,light-mbox-client";
  142. mbox-names = "906";
  143. mboxes = <&mbox_910t 2 0>;
  144. status = "disabled";
  145. };
  146. lightsound: lightsound@1 {
  147. compatible = "simple-audio-card";
  148. simple-audio-card,name = "Light-Sound-Card";
  149. #address-cells = <1>;
  150. #size-cells = <0>;
  151. status = "disabled";
  152. };
  153. dummy_codec: dummy_codec {
  154. #sound-dai-cells = <1>;
  155. compatible = "linux,bt-sco";
  156. status = "okay";
  157. };
  158. reg_vref_1v8: regulator-adc-verf {
  159. compatible = "regulator-fixed";
  160. regulator-name = "vref-1v8";
  161. regulator-min-microvolt = <1800000>;
  162. regulator-max-microvolt = <1800000>;
  163. status = "okay";
  164. };
  165. reg_tp_pwr_en: regulator-pwr-en {
  166. compatible = "regulator-fixed";
  167. regulator-name = "PWR_EN";
  168. regulator-min-microvolt = <2800000>;
  169. regulator-max-microvolt = <2800000>;
  170. gpio = <&gpio1_porta 12 1>;
  171. enable-active-high;
  172. regulator-always-on;
  173. };
  174. wcn_wifi: wireless-wlan {
  175. compatible = "wlan-platdata";
  176. clock-names = "clk_wifi";
  177. ref-clock-frequency = <24000000>;
  178. keep_wifi_power_on;
  179. pinctrl-names = "default";
  180. wifi_chip_type = "rtl8723ds";
  181. WIFI,poweren_gpio = <&gpio2_porta 29 0>;
  182. WIFI,reset_n = <&gpio2_porta 22 0>;
  183. status = "okay";
  184. };
  185. wcn_bt: wireless-bluetooth {
  186. compatible = "bluetooth-platdata";
  187. pinctrl-names = "default", "rts_gpio";
  188. BT,power_gpio = <&gpio2_porta 29 0>;
  189. status = "okay";
  190. };
  191. gpio-keys {
  192. compatible = "gpio-keys";
  193. pinctrl-0 = <&pinctrl_volume>;
  194. pinctrl-names = "default";
  195. key-volumedown {
  196. label = "Volume Down Key";
  197. linux,code = <KEY_VOLUMEDOWN>;
  198. debounce-interval = <1>;
  199. gpios = <&gpio1_porta 19 0x1>;
  200. };
  201. key-volumeup {
  202. label = "Volume Up Key";
  203. linux,code = <KEY_VOLUMEUP>;
  204. debounce-interval = <1>;
  205. gpios = <&gpio2_porta 25 0x1>;
  206. };
  207. };
  208. aon: aon {
  209. compatible = "thead,light-aon";
  210. mbox-names = "aon";
  211. mboxes = <&mbox_910t 1 0>;
  212. status = "okay";
  213. pd: light-aon-pd {
  214. compatible = "thead,light-aon-pd";
  215. #power-domain-cells = <1>;
  216. };
  217. soc_aud_3v3_en_reg: soc_aud_3v3_en {
  218. compatible = "regulator-fixed";
  219. regulator-name = "soc_aud_3v3_en";
  220. regulator-min-microvolt = <3300000>;
  221. regulator-max-microvolt = <3300000>;
  222. gpio = <&ao_gpio_porta 7 1>;
  223. enable-active-high;
  224. regulator-always-on;
  225. };
  226. soc_aud_1v8_en_reg: soc_aud_1v8_en {
  227. compatible = "regulator-fixed";
  228. regulator-name = "soc_aud_1v8_en";
  229. regulator-min-microvolt = <1800000>;
  230. regulator-max-microvolt = <1800000>;
  231. gpio = <&ao_gpio_porta 8 1>;
  232. enable-active-high;
  233. regulator-always-on;
  234. };
  235. soc_vdd_3v3_en_reg: soc_vdd_3v3_en {
  236. compatible = "regulator-fixed";
  237. regulator-name = "soc_vdd_3v3_en";
  238. regulator-min-microvolt = <3300000>;
  239. regulator-max-microvolt = <3300000>;
  240. gpio = <&gpio0_porta 30 1>;
  241. enable-active-high;
  242. regulator-always-on;
  243. };
  244. soc_lcd0_bias_en_reg: soc_lcd0_bias_en {
  245. compatible = "regulator-fixed";
  246. regulator-name = "soc_lcd0_bias_en";
  247. regulator-min-microvolt = <5700000>;
  248. regulator-max-microvolt = <5700000>;
  249. gpio = <&gpio1_porta 10 1>;
  250. enable-active-high;
  251. };
  252. soc_vdd18_lcd0_en_reg: soc_lcd0_en {
  253. compatible = "regulator-fixed";
  254. regulator-name = "soc_lcd0_en";
  255. regulator-min-microvolt = <1800000>;
  256. regulator-max-microvolt = <1800000>;
  257. gpio = <&gpio1_porta 9 1>;
  258. enable-active-high;
  259. };
  260. soc_vdd5v_se_en_reg: soc_vdd5v_se_en {
  261. compatible = "regulator-fixed";
  262. regulator-name = "soc_vdd5v_se_en";
  263. regulator-min-microvolt = <5000000>;
  264. regulator-max-microvolt = <5000000>;
  265. gpio = <&gpio2_porta 14 1>;
  266. enable-active-high;
  267. regulator-always-on;
  268. };
  269. soc_wcn33_en_reg: soc_wcn33_en {
  270. compatible = "regulator-fixed";
  271. regulator-name = "soc_wcn33_en";
  272. regulator-min-microvolt = <3300000>;
  273. regulator-max-microvolt = <3300000>;
  274. gpio = <&gpio2_porta 29 1>;
  275. enable-active-high;
  276. regulator-always-on;
  277. };
  278. soc_vbus_en_reg: soc_vbus_en {
  279. compatible = "regulator-fixed";
  280. regulator-name = "soc_vbus_en";
  281. regulator-min-microvolt = <3300000>;
  282. regulator-max-microvolt = <3300000>;
  283. gpio = <&gpio2_porta 28 1>;
  284. enable-active-high;
  285. regulator-always-on;
  286. };
  287. soc_avdd28_rgb_reg: soc_avdd28_rgb {
  288. compatible = "regulator-fixed";
  289. regulator-name = "soc_avdd28_rgb";
  290. regulator-min-microvolt = <2800000>;
  291. regulator-max-microvolt = <2800000>;
  292. gpio = <&gpio1_porta 15 1>;
  293. enable-active-high;
  294. };
  295. soc_dovdd18_rgb_reg: soc_dovdd18_rgb {
  296. compatible = "regulator-fixed";
  297. regulator-name = "soc_dovdd18_rgb";
  298. regulator-min-microvolt = <2800000>;
  299. regulator-max-microvolt = <2800000>;
  300. gpio = <&gpio1_porta 13 1>;
  301. enable-active-high;
  302. };
  303. soc_dvdd12_rgb_reg: soc_dvdd12_rgb {
  304. compatible = "regulator-fixed";
  305. regulator-name = "soc_dvdd12_rgb";
  306. regulator-min-microvolt = <2800000>;
  307. regulator-max-microvolt = <2800000>;
  308. gpio = <&gpio1_porta 14 1>;
  309. enable-active-high;
  310. };
  311. soc_avdd25_ir_reg: soc_avdd25_ir {
  312. compatible = "regulator-fixed";
  313. regulator-name = "soc_avdd25_ir";
  314. regulator-min-microvolt = <2500000>;
  315. regulator-max-microvolt = <2500000>;
  316. gpio = <&gpio0_porta 28 1>;
  317. enable-active-high;
  318. };
  319. soc_dovdd18_ir_reg: soc_dovdd18_ir {
  320. compatible = "regulator-fixed";
  321. regulator-name = "soc_dovdd18_ir";
  322. regulator-min-microvolt = <1800000>;
  323. regulator-max-microvolt = <1800000>;
  324. gpio = <&gpio1_porta 13 1>;
  325. enable-active-high;
  326. };
  327. soc_dvdd12_ir_reg: soc_dvdd12_ir {
  328. compatible = "regulator-fixed";
  329. regulator-name = "soc_dvdd12_ir";
  330. regulator-min-microvolt = <1200000>;
  331. regulator-max-microvolt = <1200000>;
  332. gpio = <&gpio0_porta 29 1>;
  333. enable-active-high;
  334. };
  335. aon_reg_dialog: light-dialog-reg {
  336. compatible = "thead,light-dialog-pmic-ant";
  337. status = "okay";
  338. dvdd_cpu_reg: appcpu_dvdd {
  339. regulator-name = "appcpu_dvdd";
  340. regulator-min-microvolt = <300000>;
  341. regulator-max-microvolt = <1570000>;
  342. regulator-boot-on;
  343. regulator-always-on;
  344. };
  345. dvddm_cpu_reg: appcpu_dvddm {
  346. regulator-name = "appcpu_dvddm";
  347. regulator-min-microvolt = <300000>;
  348. regulator-max-microvolt = <1570000>;
  349. regulator-boot-on;
  350. regulator-always-on;
  351. };
  352. soc_dvdd18_aon_reg: soc_dvdd18_aon {
  353. regulator-name = "soc_dvdd18_aon";
  354. regulator-boot-on;
  355. regulator-always-on;
  356. };
  357. soc_avdd33_usb3_reg: soc_avdd33_usb3 {
  358. regulator-name = "soc_avdd33_usb3";
  359. regulator-boot-on;
  360. regulator-always-on;
  361. };
  362. soc_dvdd08_aon_reg: soc_dvdd08_aon {
  363. regulator-name = "soc_dvdd08_aon";
  364. regulator-boot-on;
  365. regulator-always-on;
  366. };
  367. soc_dvdd08_ddr_reg: soc_dvdd08_ddr {
  368. regulator-name = "soc_dvdd08_ddr";
  369. regulator-boot-on;
  370. regulator-always-on;
  371. };
  372. soc_vdd_ddr_1v8_reg: soc_vdd_ddr_1v8 {
  373. regulator-name = "soc_vdd_ddr_1v8";
  374. regulator-boot-on;
  375. regulator-always-on;
  376. };
  377. soc_vdd_ddr_1v1_reg: soc_vdd_ddr_1v1 {
  378. regulator-name = "soc_vdd_ddr_1v1";
  379. regulator-boot-on;
  380. regulator-always-on;
  381. };
  382. soc_vdd_ddr_0v6_reg: soc_vdd_ddr_0v6 {
  383. regulator-name = "soc_vdd_ddr_0v6";
  384. regulator-boot-on;
  385. regulator-always-on;
  386. };
  387. soc_dvdd18_ap_reg: soc_dvdd18_ap {
  388. regulator-name = "soc_dvdd18_ap";
  389. regulator-boot-on;
  390. regulator-always-on;
  391. };
  392. soc_avdd08_mipi_hdmi_reg: soc_avdd08_mipi_hdmi {
  393. regulator-name = "soc_avdd08_mipi_hdmi";
  394. regulator-boot-on;
  395. regulator-always-on;
  396. };
  397. soc_avdd18_mipi_hdmi_reg: soc_avdd18_mipi_hdmi {
  398. regulator-name = "soc_avdd18_mipi_hdmi";
  399. regulator-boot-on;
  400. regulator-always-on;
  401. };
  402. soc_vdd33_emmc_reg: soc_vdd33_emmc {
  403. regulator-name = "soc_vdd33_emmc";
  404. regulator-boot-on;
  405. regulator-always-on;
  406. };
  407. soc_vdd18_emmc_reg: soc_vdd18_emmc {
  408. regulator-name = "soc_vdd18_emmc";
  409. regulator-boot-on;
  410. regulator-always-on;
  411. };
  412. soc_dovdd18_scan_reg: soc_dovdd18_scan {
  413. regulator-name = "soc_dovdd18_scan";
  414. regulator-min-microvolt = <900000>;
  415. regulator-max-microvolt = <3600000>;
  416. };
  417. soc_dvdd12_scan_reg: soc_dvdd12_scan {
  418. regulator-name = "soc_dvdd12_scan";
  419. regulator-min-microvolt = <900000>;
  420. regulator-max-microvolt = <3600000>;
  421. };
  422. soc_avdd28_scan_en_reg: soc_avdd28_scan_en {
  423. regulator-name = "soc_avdd28_scan_en";
  424. regulator-min-microvolt = <900000>;
  425. regulator-max-microvolt = <3600000>;
  426. };
  427. };
  428. c910_cpufreq {
  429. compatible = "thead,light-mpw-cpufreq";
  430. status = "okay";
  431. };
  432. test: light-aon-test {
  433. compatible = "thead,light-aon-test";
  434. };
  435. };
  436. };
  437. &resmem {
  438. #address-cells = <2>;
  439. #size-cells = <2>;
  440. ranges;
  441. tee_mem: memory@1c000000 {
  442. reg = <0x0 0x1c000000 0 0x2000000>;
  443. no-map;
  444. };
  445. dsp0_mem: memory@20000000 { /**0x2000_0000~0x2040_0000 4M**/
  446. reg = <0x0 0x20000000 0x0 0x00280000 /* DSP FW code&data section 2.5M*/
  447. 0x0 0x20280000 0x0 0x00001000 /* DSP communication area 4K*/
  448. 0x0 0x20281000 0x0 0x00007000 /* Panic/log page 28K */
  449. 0x0 0x20288000 0x0 0x00178000>; /* DSP shared memory 1.5M-32K*/
  450. no-map;
  451. };
  452. dsp1_mem: memory@20400000 { /**0x2040_0000~0x2080_0000 4M**/
  453. reg = <0x0 0x20400000 0x0 0x00280000 /* DSP FW code&data section */
  454. 0x0 0x20680000 0x0 0x00001000 /* DSP communication area */
  455. 0x0 0x20681000 0x0 0x00007000 /* Panic/log page*/
  456. 0x0 0x20688000 0x0 0x00178000>; /* DSP shared memory */
  457. no-map;
  458. };
  459. vi_mem: framebuffer@10000000 {
  460. reg = <0x0 0x10000000 0x0 0x02C00000 /* vi_mem_pool_region[0] 44 MB (default) */
  461. 0x0 0x12C00000 0x0 0x01D00000 /* vi_mem_pool_region[1] 29 MB */
  462. 0x0 0x14900000 0x0 0x01E00000>; /* vi_mem_pool_region[2] 30 MB */
  463. no-map;
  464. };
  465. facelib_mem: memory@17000000 {
  466. reg = <0x0 0x17000000 0 0x02000000>;
  467. no-map;
  468. };
  469. };
  470. &adc {
  471. vref-supply = <&reg_vref_1v8>;
  472. #io-channel-cells = <1>;
  473. status = "okay";
  474. };
  475. &audio_i2c0 {
  476. clock-frequency = <100000>;
  477. status = "okay";
  478. es8156_audio_codec: es8156@8 {
  479. #sound-dai-cells = <0>;
  480. compatible = "everest,es8156";
  481. reg = <0x08>;
  482. };
  483. es7210_audio_codec: es7210@40 {
  484. #sound-dai-cells = <0>;
  485. compatible = "MicArray_0";
  486. reg = <0x40>;
  487. };
  488. audio_aw87519_pa@58 {
  489. compatible = "awinic,aw87519_pa";
  490. reg = <0x58>;
  491. reset-gpio = <&ao_gpio4_porta 9 0x1>;
  492. status = "okay";
  493. };
  494. };
  495. &i2c1 {
  496. clock-frequency = <100000>;
  497. status = "okay";
  498. };
  499. &spi0 {
  500. num-cs = <1>;
  501. cs-gpios = <&gpio2_porta 15 0>; // GPIO_ACTIVE_HIGH: 0
  502. rx-sample-delay-ns = <10>;
  503. status = "disabled";
  504. spi_norflash@0 {
  505. #address-cells = <1>;
  506. #size-cells = <1>;
  507. compatible = "winbond,w25q64jwm", "jedec,spi-nor";
  508. reg = <0>;
  509. spi-max-frequency = <50000000>;
  510. w25q,fast-read;
  511. };
  512. spidev@1 {
  513. compatible = "spidev";
  514. #address-cells = <0x1>;
  515. #size-cells = <0x1>;
  516. reg = <0x1>;
  517. spi-max-frequency = <50000000>;
  518. };
  519. };
  520. &uart0 {
  521. clock-frequency = <100000000>;
  522. };
  523. &qspi0 {
  524. num-cs = <1>;
  525. cs-gpios = <&gpio2_porta 3 0>;
  526. rx-sample-dly = <4>;
  527. status = "disabled";
  528. spi-flash@0 {
  529. #address-cells = <1>;
  530. #size-cells = <1>;
  531. compatible = "spi-nand";
  532. spi-max-frequency = <100000000>;
  533. spi-tx-bus-width = <4>;
  534. spi-rx-bus-width = <4>;
  535. reg = <0>;
  536. partition@0 {
  537. label = "ubi1";
  538. reg = <0x00000000 0x08000000>;
  539. };
  540. };
  541. };
  542. &qspi1 {
  543. compatible = "snps,dw-apb-ssi";
  544. num-cs = <1>;
  545. cs-gpios = <&gpio0_porta 1 0>;
  546. status = "okay";
  547. spidev@0 {
  548. compatible = "spidev";
  549. #address-cells = <0x1>;
  550. #size-cells = <0x1>;
  551. reg = <0x0>;
  552. spi-max-frequency = <50000000>;
  553. };
  554. };
  555. &gmac0 {
  556. phy-mode = "rgmii-id";
  557. rx-clk-delay = <0x00>; /* for RGMII */
  558. tx-clk-delay = <0x00>; /* for RGMII */
  559. phy-handle = <&phy_88E1111_0>;
  560. status = "okay";
  561. mdio0 {
  562. #address-cells = <1>;
  563. #size-cells = <0>;
  564. compatible = "snps,dwmac-mdio";
  565. phy_88E1111_0: ethernet-phy@0 {
  566. reg = <0x1>;
  567. };
  568. phy_88E1111_1: ethernet-phy@1 {
  569. reg = <0x2>;
  570. };
  571. };
  572. };
  573. &gmac1 {
  574. phy-mode = "rgmii-id";
  575. rx-clk-delay = <0x00>; /* for RGMII */
  576. tx-clk-delay = <0x00>; /* for RGMII */
  577. phy-handle = <&phy_88E1111_1>;
  578. status = "disabled";
  579. };
  580. &emmc {
  581. max-frequency = <198000000>;
  582. non-removable;
  583. mmc-hs400-1_8v;
  584. io_fixed_1v8;
  585. is_emmc;
  586. no-sdio;
  587. no-sd;
  588. pull_up;
  589. bus-width = <8>;
  590. status = "okay";
  591. };
  592. &sdhci0 {
  593. max-frequency = <198000000>;
  594. bus-width = <4>;
  595. pull_up;
  596. wprtn_ignore;
  597. status = "okay";
  598. };
  599. &sdhci1 {
  600. max-frequency = <100000000>;
  601. bus-width = <4>;
  602. pull_up;
  603. no-sd;
  604. no-mmc;
  605. non-removable;
  606. io_fixed_1v8;
  607. post-power-on-delay-ms = <50>;
  608. wprtn_ignore;
  609. cap-sd-highspeed;
  610. keep-power-in-suspend;
  611. wakeup-source;
  612. status = "okay";
  613. };
  614. &padctrl0_apsys { /* right-pinctrl */
  615. light-evb-padctrl0 {
  616. /*
  617. * Pin Configuration Node:
  618. * Format: <pin_id mux_node config>
  619. */
  620. pinctrl_uart0: uart0grp {
  621. thead,pins = <
  622. FM_UART0_TXD 0x0 0x72
  623. FM_UART0_RXD 0x0 0x72
  624. >;
  625. };
  626. pinctrl_spi0: spi0grp {
  627. thead,pins = <
  628. FM_SPI_CSN 0x3 0x20a
  629. FM_SPI_SCLK 0x0 0x20a
  630. FM_SPI_MISO 0x0 0x23a
  631. FM_SPI_MOSI 0x0 0x23a
  632. >;
  633. };
  634. pinctrl_qspi0: qspi0grp {
  635. thead,pins = <
  636. FM_QSPI0_SCLK 0x0 0x20f
  637. FM_QSPI0_CSN0 0x3 0x20f
  638. FM_QSPI0_CSN1 0x0 0x20f
  639. FM_QSPI0_D0_MOSI 0x0 0x23f
  640. FM_QSPI0_D1_MISO 0x0 0x23f
  641. FM_QSPI0_D2_WP 0x0 0x23f
  642. FM_QSPI0_D3_HOLD 0x0 0x23f
  643. >;
  644. };
  645. pinctrl_audio_i2s0: i2s0grp {
  646. thead,pins = <
  647. FM_QSPI0_SCLK 0x2 0x208
  648. FM_QSPI0_CSN0 0x2 0x238
  649. FM_QSPI0_CSN1 0x2 0x208
  650. FM_QSPI0_D0_MOSI 0x2 0x238
  651. FM_QSPI0_D1_MISO 0x2 0x238
  652. FM_QSPI0_D2_WP 0x2 0x238
  653. FM_QSPI0_D3_HOLD 0x2 0x238
  654. >;
  655. };
  656. pinctrl_pwm: pwmgrp {
  657. thead,pins = <
  658. FM_GPIO3_2 0x1 0x208 /* pwm0 */
  659. >;
  660. };
  661. };
  662. };
  663. &padctrl1_apsys { /* left-pinctrl */
  664. light-evb-padctrl1 {
  665. /*
  666. * Pin Configuration Node:
  667. * Format: <pin_id mux_node config>
  668. */
  669. pinctrl_uart3: uart3grp {
  670. thead,pins = <
  671. FM_UART3_TXD 0x0 0x72
  672. FM_UART3_RXD 0x0 0x72
  673. >;
  674. };
  675. pinctrl_uart4: uart4grp {
  676. thead,pins = <
  677. FM_UART4_TXD 0x0 0x72
  678. FM_UART4_RXD 0x0 0x72
  679. FM_UART4_CTSN 0x0 0x72
  680. FM_UART4_RTSN 0x0 0x72
  681. >;
  682. };
  683. pinctrl_qspi1: qspi1grp {
  684. thead,pins = <
  685. FM_QSPI1_SCLK 0x0 0x20a
  686. FM_QSPI1_CSN0 0x3 0x20a
  687. FM_QSPI1_D0_MOSI 0x0 0x23a
  688. FM_QSPI1_D1_MISO 0x0 0x23a
  689. >;
  690. };
  691. pinctrl_iso7816: iso7816grp {
  692. thead,pins = <
  693. FM_QSPI1_SCLK 0x1 0x208
  694. FM_QSPI1_D0_MOSI 0x1 0x238
  695. FM_QSPI1_D1_MISO 0x1 0x238
  696. FM_QSPI1_D2_WP 0x1 0x238
  697. FM_QSPI1_D3_HOLD 0x1 0x238
  698. >;
  699. };
  700. pinctrl_volume: volume_grp {
  701. thead,pins = <
  702. FM_CLK_OUT_2 0x3 0x208
  703. >;
  704. };
  705. };
  706. };
  707. &padctrl_aosys {
  708. light-aon-padctrl {
  709. /*
  710. * Pin Configuration Node:
  711. * Format: <pin_id mux_node config>
  712. */
  713. pinctrl_audiopa1: audiopa1_grp {
  714. thead,pins = <
  715. FM_AUDIO_PA1 0x3 0x72
  716. >;
  717. };
  718. pinctrl_audiopa2: audiopa2_grp {
  719. thead,pins = <
  720. FM_AUDIO_PA2 0x0 0x72
  721. >;
  722. };
  723. };
  724. };
  725. &i2c0 {
  726. clock-frequency = <400000>;
  727. status = "okay";
  728. };
  729. &i2c1 {
  730. clock-frequency = <400000>;
  731. status = "okay";
  732. };
  733. &i2c2 {
  734. clock-frequency = <400000>;
  735. status = "okay";
  736. };
  737. &i2c3 {
  738. clock-frequency = <400000>;
  739. status = "okay";
  740. };
  741. &i2c4 {
  742. clock-frequency = <400000>;
  743. status = "okay";
  744. };
  745. &isp0 {
  746. status = "okay";
  747. };
  748. &isp1 {
  749. status = "okay";
  750. };
  751. &isp_ry0 {
  752. status = "okay";
  753. };
  754. &dewarp {
  755. status = "okay";
  756. };
  757. &dec400_isp0 {
  758. status = "okay";
  759. };
  760. &dec400_isp1 {
  761. status = "okay";
  762. };
  763. &dec400_isp2 {
  764. status = "okay";
  765. };
  766. &bm_visys {
  767. status = "okay";
  768. };
  769. &bm_csi0 {
  770. status = "okay";
  771. };
  772. &bm_csi1 {
  773. status = "okay";
  774. };
  775. &bm_csi2 {
  776. status = "okay";
  777. };
  778. &vi_pre {
  779. //vi_pre_irq_en = <1>;
  780. status = "okay";
  781. };
  782. &xtensa_dsp {
  783. status = "okay";
  784. };
  785. &xtensa_dsp0 {
  786. status = "okay";
  787. memory-region = <&dsp0_mem>;
  788. };
  789. &xtensa_dsp1 {
  790. status = "okay";
  791. memory-region = <&dsp1_mem>;
  792. };
  793. &vvcam_flash_led0{
  794. flash_led_name = "aw36413_aw36515";
  795. floodlight_i2c_bus = /bits/ 8 <2>;
  796. floodlight_en_pin = <&gpio1_porta 26 0>;
  797. projection_i2c_bus = /bits/ 8 <1>;
  798. flash_led_touch_pin = <&gpio1_porta 27 0>; //flash led touch pin
  799. io-channels = <&adc 2>;
  800. io-channel-names = "projection_adc";
  801. status = "okay";
  802. };
  803. &vvcam_sensor0 {
  804. sensor_name = "SC2310";
  805. sensor_regulators = "DOVDD18_RGB", "DVDD12_RGB", "AVDD28_RGB";
  806. sensor_regulator_timing_us = <70 50 20>;
  807. sensor_pdn = <&gpio1_porta 21 0>; //powerdown pin / shutdown pin
  808. sensor_rst = <&gpio1_porta 16 0>;
  809. sensor_pdn_delay_us = <4000>; //powerdown pin / shutdown pin actived till I2C ready
  810. DOVDD18_RGB-supply = <&soc_dovdd18_rgb_reg>;
  811. DVDD12_RGB-supply = <&soc_dvdd12_rgb_reg>;
  812. AVDD28_RGB-supply = <&soc_avdd28_rgb_reg>;
  813. i2c_reg_width = /bits/ 8 <2>;
  814. i2c_data_width = /bits/ 8 <1>;
  815. i2c_addr = /bits/ 8 <0x30>;
  816. i2c_bus = /bits/ 8 <3>;
  817. status = "okay";
  818. };
  819. &vvcam_sensor1 {
  820. sensor_name = "SC132GS";
  821. sensor_regulators = "DOVDD18_IR", "DVDD12_IR", "AVDD25_IR";
  822. sensor_regulator_timing_us = <70 1000 2000>;
  823. i2c_addr = /bits/ 8 <0x31>;
  824. sensor_pdn = <&gpio1_porta 28 0>; //powerdown pin / shutdown pin
  825. sensor_rst = <&gpio1_porta 24 0>;
  826. sensor_pdn_delay_us = <2000>; //powerdown pin / shutdown pin actived till I2C ready
  827. DOVDD18_IR-supply = <&soc_dovdd18_ir_reg>;
  828. DVDD12_IR-supply = <&soc_dvdd12_ir_reg>;
  829. AVDD25_IR-supply = <&soc_avdd25_ir_reg>;
  830. i2c_reg_width = /bits/ 8 <2>;
  831. i2c_data_width = /bits/ 8 <1>;
  832. i2c_bus = /bits/ 8 <2>;
  833. status = "okay";
  834. };
  835. &vvcam_sensor2 {
  836. sensor_name = "GC5035";
  837. sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
  838. sensor_regulator_timing_us = <100 50 0>;
  839. sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin
  840. sensor_rst = <&gpio1_porta 29 0>;
  841. sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
  842. DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>;
  843. DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
  844. AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
  845. i2c_addr = /bits/ 8 <0x37>;
  846. i2c_bus = /bits/ 8 <4>;
  847. i2c_reg_width = /bits/ 8 <1>;
  848. i2c_data_width = /bits/ 8 <1>;
  849. status = "okay";
  850. };
  851. &vvcam_sensor3 {
  852. sensor_name = "GC02M1B";
  853. sensor_regulators = "DOVDD18_SCAN", "DVDD12_SCAN", "AVDD28_SCAN";
  854. sensor_regulator_timing_us = <100 50 0>;
  855. sensor_pdn = <&gpio1_porta 30 0>; //powerdown pin / shutdown pin
  856. sensor_rst = <&gpio1_porta 29 0>;
  857. sensor_pdn_delay_us = <1000>; //powerdown pin / shutdown pin actived till I2C ready
  858. DOVDD18_SCAN-supply = <&soc_dovdd18_scan_reg>;
  859. DVDD12_SCAN-supply = <&soc_dvdd12_scan_reg>;
  860. AVDD28_SCAN-supply = <&soc_avdd28_scan_en_reg>;
  861. i2c_addr = /bits/ 8 <0x37>;
  862. i2c_bus = /bits/ 8 <4>;
  863. i2c_reg_width = /bits/ 8 <1>;
  864. i2c_data_width = /bits/ 8 <1>;
  865. status = "okay";
  866. };
  867. &video0{
  868. vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
  869. channel0 {
  870. sensor0 {
  871. subdev_name = "vivcam";
  872. idx = <2>; //<2>=vivcam2 : gc5035
  873. csi_idx = <0>; //<0>=CSI2
  874. mode_idx = <3>;
  875. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  876. };
  877. sensor1 {
  878. subdev_name = "vivcam";
  879. idx = <3>; //<3>=vivcam3 : gc02m1b
  880. csi_idx = <0>; //<0>=CSI2
  881. mode_idx = <0>;
  882. path_type = "SENSOR_1600x1200_RAW10_LINER";
  883. };
  884. dma {
  885. path_type = "VIPRE_CSI0_ISP0";
  886. };
  887. isp {
  888. subdev_name = "isp";
  889. idx = <0>;
  890. path_type = "ISP_MI_PATH_MP";
  891. output {
  892. max_width = <1920>;
  893. max_height = <1088>;
  894. bit_per_pixel = <12>;
  895. frame_count = <3>;
  896. };
  897. };
  898. };
  899. channel1 {
  900. sensor0 {
  901. subdev_name = "vivcam";
  902. idx = <2>; //<2>=vivcam2 : gc5035
  903. csi_idx = <0>; //<0>=CSI2
  904. mode_idx = <3>;
  905. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  906. };
  907. sensor1 {
  908. subdev_name = "vivcam";
  909. idx = <3>; //<3>=vivcam3 : gc02m1b
  910. csi_idx = <0>; //<0>=CSI2
  911. mode_idx = <0>;
  912. path_type = "SENSOR_1600x1200_RAW10_LINER";
  913. };
  914. dma {
  915. path_type = "VIPRE_CSI0_ISP0";
  916. };
  917. isp {
  918. subdev_name = "isp";
  919. idx = <0>;
  920. path_type = "ISP_MI_PATH_SP";
  921. output {
  922. max_width = <1920>;
  923. max_height = <1088>;
  924. bit_per_pixel = <12>;
  925. frame_count = <3>;
  926. };
  927. };
  928. };
  929. channel2 {
  930. sensor0 {
  931. subdev_name = "vivcam";
  932. idx = <2>; //<2>=vivcam2 : gc5035
  933. csi_idx = <0>; //<0>=CSI2
  934. mode_idx = <3>;
  935. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  936. };
  937. sensor1 {
  938. subdev_name = "vivcam";
  939. idx = <3>; //<3>=vivcam3 : gc02m1b
  940. csi_idx = <0>; //<0>=CSI2
  941. mode_idx = <0>;
  942. path_type = "SENSOR_1600x1200_RAW10_LINER";
  943. };
  944. dma {
  945. path_type = "VIPRE_CSI0_ISP0";
  946. };
  947. isp {
  948. subdev_name = "isp";
  949. idx = <0>;
  950. path_type = "ISP_MI_PATH_SP2_BP";
  951. output {
  952. max_width = <1920>;
  953. max_height = <1088>;
  954. bit_per_pixel = <12>;
  955. frame_count = <3>;
  956. };
  957. };
  958. };
  959. };
  960. &video1{
  961. vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[2]
  962. channel0 {
  963. sensor0 {
  964. subdev_name = "vivcam";
  965. idx = <2>; //<2>=vivcam2 : gc5035
  966. csi_idx = <0>; //<0>=CSI2
  967. mode_idx = <3>;
  968. path_type = "SENSOR_1296x972_RAW10_LINER";
  969. };
  970. sensor1 {
  971. subdev_name = "vivcam";
  972. idx = <3>; //<3>=vivcam3 : gc02m1b
  973. csi_idx = <0>; //<0>=CSI2
  974. mode_idx = <0>;
  975. path_type = "SENSOR_1600x1200_RAW10_LINER";
  976. };
  977. dma {
  978. path_type = "VIPRE_CSI0_ISP0";
  979. };
  980. isp {
  981. subdev_name = "isp";
  982. idx = <0>;
  983. path_type = "ISP_MI_PATH_MP";
  984. output {
  985. max_width = <1920>;
  986. max_height = <1088>;
  987. bit_per_pixel = <12>;
  988. frame_count = <3>;
  989. };
  990. };
  991. dw {
  992. subdev_name = "dw";
  993. idx = <0>;
  994. path_type = "DW_DWE_VSE0";
  995. dw_dst_depth = <2>;
  996. };
  997. };
  998. channel1 {
  999. sensor0 {
  1000. subdev_name = "vivcam";
  1001. idx = <2>; //<2>=vivcam2 : gc5035
  1002. csi_idx = <0>; //<0>=CSI2
  1003. mode_idx = <3>;
  1004. path_type = "SENSOR_1296x972_RAW10_LINER";
  1005. };
  1006. sensor1 {
  1007. subdev_name = "vivcam";
  1008. idx = <3>; //<3>=vivcam3 : gc02m1b
  1009. csi_idx = <0>; //<0>=CSI2
  1010. mode_idx = <0>;
  1011. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1012. };
  1013. dma {
  1014. path_type = "VIPRE_CSI0_ISP0";
  1015. };
  1016. isp {
  1017. subdev_name = "isp";
  1018. idx = <0>;
  1019. path_type = "ISP_MI_PATH_MP";
  1020. output {
  1021. max_width = <1920>;
  1022. max_height = <1088>;
  1023. bit_per_pixel = <12>;
  1024. frame_count = <3>;
  1025. };
  1026. };
  1027. dw {
  1028. subdev_name = "dw";
  1029. idx = <0>;
  1030. path_type = "DW_DWE_VSE1";
  1031. dw_dst_depth = <2>;
  1032. };
  1033. };
  1034. channel2 {
  1035. sensor0 {
  1036. subdev_name = "vivcam";
  1037. idx = <2>; //<2>=vivcam2 : gc5035
  1038. csi_idx = <0>; //<0>=CSI2
  1039. mode_idx = <3>;
  1040. path_type = "SENSOR_1296x972_RAW10_LINER";
  1041. };
  1042. sensor1 {
  1043. subdev_name = "vivcam";
  1044. idx = <3>; //<3>=vivcam3 : gc02m1b
  1045. csi_idx = <0>; //<0>=CSI2
  1046. mode_idx = <0>;
  1047. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1048. };
  1049. dma {
  1050. path_type = "VIPRE_CSI0_ISP0";
  1051. };
  1052. isp {
  1053. subdev_name = "isp";
  1054. idx = <0>;
  1055. path_type = "ISP_MI_PATH_MP";
  1056. output {
  1057. max_width = <1920>;
  1058. max_height = <1088>;
  1059. bit_per_pixel = <12>;
  1060. frame_count = <3>;
  1061. };
  1062. };
  1063. dw {
  1064. subdev_name = "dw";
  1065. idx = <0>;
  1066. path_type = "DW_DWE_VSE2";
  1067. dw_dst_depth = <2>;
  1068. };
  1069. };
  1070. };
  1071. &video2{
  1072. vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
  1073. channel0 {
  1074. sensor0 {
  1075. subdev_name = "vivcam";
  1076. idx = <0>; //vivcam0 sc2310
  1077. csi_idx = <1>; //<1>=CSI2_B
  1078. mode_idx = <1>;
  1079. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1080. };
  1081. dma {
  1082. path_type = "VIPRE_CSI1_ISP1";
  1083. };
  1084. isp {
  1085. subdev_name = "isp";
  1086. idx = <1>;
  1087. path_type = "ISP_MI_PATH_MP";
  1088. output {
  1089. max_width = <1920>;
  1090. max_height = <1088>;
  1091. bit_per_pixel = <12>;
  1092. frame_count = <3>;
  1093. };
  1094. };
  1095. };
  1096. channel1 {
  1097. sensor0 {
  1098. subdev_name = "vivcam";
  1099. idx = <0>; //vivcam0 sc2310
  1100. csi_idx = <1>; //<1>=CSI2_B
  1101. mode_idx = <1>;
  1102. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1103. };
  1104. dma {
  1105. path_type = "VIPRE_CSI1_ISP1";
  1106. };
  1107. isp {
  1108. subdev_name = "isp";
  1109. idx = <1>;
  1110. path_type = "ISP_MI_PATH_SP";
  1111. output {
  1112. max_width = <1920>;
  1113. max_height = <1088>;
  1114. bit_per_pixel = <12>;
  1115. frame_count = <3>;
  1116. };
  1117. };
  1118. };
  1119. channel2 {
  1120. sensor0 {
  1121. subdev_name = "vivcam";
  1122. idx = <0>; //vivcam0 sc2310
  1123. csi_idx = <1>; //<1>=CSI2_B
  1124. mode_idx = <1>;
  1125. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1126. };
  1127. dma {
  1128. path_type = "VIPRE_CSI1_ISP1";
  1129. };
  1130. isp {
  1131. subdev_name = "isp";
  1132. idx = <1>;
  1133. path_type = "ISP_MI_PATH_SP2_BP";
  1134. output {
  1135. max_width = <1920>;
  1136. max_height = <1088>;
  1137. bit_per_pixel = <12>;
  1138. frame_count = <3>;
  1139. };
  1140. };
  1141. };
  1142. };
  1143. &video3{
  1144. vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
  1145. channel0 {
  1146. sensor0 {
  1147. subdev_name = "vivcam";
  1148. idx = <0>; //vivcam0 sc2310
  1149. csi_idx = <1>; //<1>=CSI2B
  1150. mode_idx = <1>;
  1151. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1152. };
  1153. dma {
  1154. path_type = "VIPRE_CSI1_ISP1";
  1155. };
  1156. isp {
  1157. subdev_name = "isp";
  1158. idx = <1>;
  1159. path_type = "ISP_MI_PATH_MP";
  1160. output {
  1161. max_width = <1920>;
  1162. max_height = <1088>;
  1163. bit_per_pixel = <12>;
  1164. frame_count = <3>;
  1165. };
  1166. };
  1167. dw {
  1168. subdev_name = "dw";
  1169. idx = <0>;
  1170. path_type = "DW_DWE_VSE0";
  1171. dw_dst_depth = <2>;
  1172. };
  1173. };
  1174. channel1 {
  1175. sensor0 {
  1176. subdev_name = "vivcam";
  1177. idx = <0>; //vivcam0 sc2310
  1178. csi_idx = <1>; //<1>=CSI2B
  1179. mode_idx = <1>;
  1180. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1181. };
  1182. dma {
  1183. path_type = "VIPRE_CSI1_ISP1";
  1184. };
  1185. isp {
  1186. subdev_name = "isp";
  1187. idx = <1>;
  1188. path_type = "ISP_MI_PATH_MP";
  1189. output {
  1190. max_width = <1920>;
  1191. max_height = <1088>;
  1192. bit_per_pixel = <12>;
  1193. frame_count = <3>;
  1194. };
  1195. };
  1196. dw {
  1197. subdev_name = "dw";
  1198. idx = <0>;
  1199. path_type = "DW_DWE_VSE1";
  1200. dw_dst_depth = <2>;
  1201. };
  1202. };
  1203. channel2 {
  1204. sensor0 {
  1205. subdev_name = "vivcam";
  1206. idx = <0>; //vivcam0 sc2310
  1207. csi_idx = <1>; //<1>=CSI2_B
  1208. mode_idx = <1>;
  1209. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1210. };
  1211. dma {
  1212. path_type = "VIPRE_CSI1_ISP1";
  1213. };
  1214. isp {
  1215. subdev_name = "isp";
  1216. idx = <1>;
  1217. path_type = "ISP_MI_PATH_MP";
  1218. output {
  1219. max_width = <1920>;
  1220. max_height = <1088>;
  1221. bit_per_pixel = <12>;
  1222. frame_count = <3>;
  1223. };
  1224. };
  1225. dw {
  1226. subdev_name = "dw";
  1227. idx = <0>;
  1228. path_type = "DW_DWE_VSE2";
  1229. dw_dst_depth = <2>;
  1230. };
  1231. };
  1232. };
  1233. &video4{
  1234. vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
  1235. channel0 {
  1236. sensor0 {
  1237. subdev_name = "vivcam";
  1238. idx = <0>; //vivcam0 sc2310
  1239. csi_idx = <1>; //<1>=CSI2_B
  1240. mode_idx = <1>;
  1241. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1242. };
  1243. dma {
  1244. path_type = "VIPRE_CSI1_ISP1";
  1245. };
  1246. isp {
  1247. subdev_name = "isp";
  1248. idx = <1>;
  1249. path_type = "ISP_MI_PATH_PP";
  1250. output {
  1251. max_width = <1920>;
  1252. max_height = <1088>;
  1253. bit_per_pixel = <12>;
  1254. frame_count = <3>;
  1255. };
  1256. };
  1257. dsp {
  1258. subdev_name = "dsp";
  1259. idx = <0>;
  1260. path_type = "DSP_PATH_ISP_RY";
  1261. output {
  1262. max_width = <1920>;
  1263. max_height = <1088>;
  1264. bit_per_pixel = <12>;
  1265. frame_count = <3>;
  1266. };
  1267. };
  1268. ry {
  1269. subdev_name = "ry";
  1270. idx = <0>;
  1271. path_type = "ISP_RY_MI_PATH_MP";
  1272. output {
  1273. max_width = <1920>;
  1274. max_height = <1088>;
  1275. bit_per_pixel = <12>;
  1276. frame_count = <3>;
  1277. };
  1278. };
  1279. };
  1280. channel1 {
  1281. sensor0 {
  1282. subdev_name = "vivcam";
  1283. idx = <0>; //vivcam0 sc2310
  1284. csi_idx = <1>; //<1>=CSI2_B
  1285. mode_idx = <1>;
  1286. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1287. };
  1288. dma {
  1289. path_type = "VIPRE_CSI1_ISP1";
  1290. };
  1291. isp {
  1292. subdev_name = "isp";
  1293. idx = <1>;
  1294. path_type = "ISP_MI_PATH_PP";
  1295. output {
  1296. max_width = <1920>;
  1297. max_height = <1088>;
  1298. bit_per_pixel = <12>;
  1299. frame_count = <3>;
  1300. };
  1301. };
  1302. dsp {
  1303. subdev_name = "dsp";
  1304. idx = <0>;
  1305. path_type = "DSP_PATH_ISP_RY";
  1306. output {
  1307. max_width = <1920>;
  1308. max_height = <1088>;
  1309. bit_per_pixel = <12>;
  1310. frame_count = <3>;
  1311. };
  1312. };
  1313. ry {
  1314. subdev_name = "ry";
  1315. idx = <0>;
  1316. path_type = "ISP_RY_MI_PATH_SP";
  1317. output {
  1318. max_width = <1920>;
  1319. max_height = <1088>;
  1320. bit_per_pixel = <12>;
  1321. frame_count = <3>;
  1322. };
  1323. };
  1324. };
  1325. channel2 {
  1326. sensor0 {
  1327. subdev_name = "vivcam";
  1328. idx = <0>; //vivcam0 sc2310
  1329. csi_idx = <1>; //<1>=CSI2_B
  1330. mode_idx = <1>;
  1331. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1332. };
  1333. dma {
  1334. path_type = "VIPRE_CSI1_ISP1";
  1335. };
  1336. isp {
  1337. subdev_name = "isp";
  1338. idx = <1>;
  1339. path_type = "ISP_MI_PATH_PP";
  1340. output {
  1341. max_width = <1920>;
  1342. max_height = <1088>;
  1343. bit_per_pixel = <12>;
  1344. frame_count = <3>;
  1345. };
  1346. };
  1347. dsp {
  1348. subdev_name = "dsp";
  1349. idx = <0>;
  1350. path_type = "DSP_PATH_ISP_RY";
  1351. output {
  1352. max_width = <1920>;
  1353. max_height = <1088>;
  1354. bit_per_pixel = <12>;
  1355. frame_count = <3>;
  1356. };
  1357. };
  1358. ry {
  1359. subdev_name = "ry";
  1360. idx = <0>;
  1361. path_type = "ISP_RY_MI_PATH_SP2_BP";
  1362. output {
  1363. max_width = <1920>;
  1364. max_height = <1088>;
  1365. bit_per_pixel = <12>;
  1366. frame_count = <3>;
  1367. };
  1368. };
  1369. };
  1370. };
  1371. &video5{
  1372. vi_mem_pool_region = <0>; // vi_mem: framebuffer, region[0]
  1373. channel0 {
  1374. sensor0 {
  1375. subdev_name = "vivcam";
  1376. idx = <0>; //vivcam0 sc2310
  1377. csi_idx = <1>; //<1>=CSI2_B
  1378. mode_idx = <1>;
  1379. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1380. };
  1381. dma {
  1382. path_type = "VIPRE_CSI1_ISP1";
  1383. };
  1384. isp {
  1385. subdev_name = "isp";
  1386. idx = <1>;
  1387. path_type = "ISP_MI_PATH_PP";
  1388. output {
  1389. max_width = <1920>;
  1390. max_height = <1088>;
  1391. bit_per_pixel = <12>;
  1392. frame_count = <3>;
  1393. };
  1394. };
  1395. dsp {
  1396. subdev_name = "dsp";
  1397. idx = <0>;
  1398. path_type = "DSP_PATH_ISP_RY";
  1399. output {
  1400. max_width = <1920>;
  1401. max_height = <1088>;
  1402. bit_per_pixel = <12>;
  1403. frame_count = <3>;
  1404. };
  1405. };
  1406. ry {
  1407. subdev_name = "ry";
  1408. idx = <0>;
  1409. path_type = "ISP_RY_MI_PATH_MP";
  1410. output {
  1411. max_width = <1920>;
  1412. max_height = <1088>;
  1413. bit_per_pixel = <12>;
  1414. frame_count = <3>;
  1415. };
  1416. };
  1417. dw {
  1418. subdev_name = "dw";
  1419. idx = <0>;
  1420. path_type = "DW_DWE_VSE0";
  1421. dw_dst_depth = <2>;
  1422. };
  1423. };
  1424. channel1 {
  1425. sensor0 {
  1426. subdev_name = "vivcam";
  1427. idx = <0>; //vivcam0 sc2310
  1428. csi_idx = <1>; //<1>=CSI2_B
  1429. mode_idx = <1>;
  1430. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1431. };
  1432. dma {
  1433. path_type = "VIPRE_CSI1_ISP1";
  1434. };
  1435. isp {
  1436. subdev_name = "isp";
  1437. idx = <1>;
  1438. path_type = "ISP_MI_PATH_PP";
  1439. output {
  1440. max_width = <1920>;
  1441. max_height = <1088>;
  1442. bit_per_pixel = <12>;
  1443. frame_count = <3>;
  1444. };
  1445. };
  1446. dsp {
  1447. subdev_name = "dsp";
  1448. idx = <0>;
  1449. path_type = "DSP_PATH_ISP_RY";
  1450. output {
  1451. max_width = <1920>;
  1452. max_height = <1088>;
  1453. bit_per_pixel = <12>;
  1454. frame_count = <3>;
  1455. };
  1456. };
  1457. ry {
  1458. subdev_name = "ry";
  1459. idx = <0>;
  1460. path_type = "ISP_RY_MI_PATH_MP";
  1461. output {
  1462. max_width = <1920>;
  1463. max_height = <1088>;
  1464. bit_per_pixel = <12>;
  1465. frame_count = <3>;
  1466. };
  1467. };
  1468. dw {
  1469. subdev_name = "dw";
  1470. idx = <0>;
  1471. path_type = "DW_DWE_VSE1";
  1472. dw_dst_depth = <2>;
  1473. };
  1474. };
  1475. channel2 {
  1476. sensor0 {
  1477. subdev_name = "vivcam";
  1478. idx = <0>; //vivcam0 sc2310
  1479. csi_idx = <1>; //<1>=CSI2_B
  1480. mode_idx = <1>;
  1481. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1482. };
  1483. dma {
  1484. path_type = "VIPRE_CSI1_ISP1";
  1485. };
  1486. isp {
  1487. subdev_name = "isp";
  1488. idx = <1>;
  1489. path_type = "ISP_MI_PATH_PP";
  1490. output {
  1491. max_width = <1920>;
  1492. max_height = <1088>;
  1493. bit_per_pixel = <12>;
  1494. frame_count = <3>;
  1495. };
  1496. };
  1497. dsp {
  1498. subdev_name = "dsp";
  1499. idx = <0>;
  1500. path_type = "DSP_PATH_ISP_RY";
  1501. output {
  1502. max_width = <1920>;
  1503. max_height = <1088>;
  1504. bit_per_pixel = <12>;
  1505. frame_count = <3>;
  1506. };
  1507. };
  1508. ry {
  1509. subdev_name = "ry";
  1510. idx = <0>;
  1511. path_type = "ISP_RY_MI_PATH_MP";
  1512. output {
  1513. max_width = <1920>;
  1514. max_height = <1088>;
  1515. bit_per_pixel = <12>;
  1516. frame_count = <3>;
  1517. };
  1518. };
  1519. dw {
  1520. subdev_name = "dw";
  1521. idx = <0>;
  1522. path_type = "DW_DWE_VSE2";
  1523. dw_dst_depth = <2>;
  1524. };
  1525. };
  1526. };
  1527. &video6{
  1528. vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
  1529. channel0 {
  1530. sensor0 {
  1531. subdev_name = "vivcam";
  1532. idx = <1>; // vivcam1 sc132gs
  1533. csi_idx = <2>; //<2>=CSI2X2_A
  1534. flash_led_idx = <0>;
  1535. mode_idx = <0>;
  1536. path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
  1537. };
  1538. dsp{
  1539. output {
  1540. max_width = <1080>;
  1541. max_height = <1280>;
  1542. bit_per_pixel = <16>;
  1543. frame_count = <3>;
  1544. };
  1545. };
  1546. };
  1547. channel1 {
  1548. sensor0 {
  1549. subdev_name = "vivcam";
  1550. idx = <1>; //vivcam1 sc132gs
  1551. csi_idx = <2>; //<2>=CSI2X2_A
  1552. flash_led_idx = <0>;
  1553. mode_idx = <0>;
  1554. path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
  1555. };
  1556. dsp{
  1557. output {
  1558. max_width = <1080>;
  1559. max_height = <1280>;
  1560. bit_per_pixel = <16>;
  1561. frame_count = <3>;
  1562. };
  1563. };
  1564. };
  1565. };
  1566. &video7{
  1567. channel0 {
  1568. sensor0 {
  1569. subdev_name = "vivcam";
  1570. idx = <2>; //<2>=vivcam2 : gc5035
  1571. csi_idx = <0>; //<0>=CSI2
  1572. mode_idx = <3>;
  1573. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  1574. };
  1575. sensor1 {
  1576. subdev_name = "vivcam";
  1577. idx = <3>; //<3>=vivcam3 : gc02m1b
  1578. csi_idx = <0>; //<0>=CSI2
  1579. mode_idx = <0>;
  1580. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1581. };
  1582. dma {
  1583. path_type = "VIPRE_CSI0_ISP0";
  1584. };
  1585. isp {
  1586. subdev_name = "isp";
  1587. idx = <0>;
  1588. path_type = "ISP_MI_PATH_PP";
  1589. output {
  1590. max_width = <1920>;
  1591. max_height = <1088>;
  1592. bit_per_pixel = <12>;
  1593. frame_count = <3>;
  1594. };
  1595. };
  1596. dsp {
  1597. subdev_name = "dsp";
  1598. idx = <1>;
  1599. path_type = "DSP_PATH_ISP_RY";
  1600. output {
  1601. max_width = <1920>;
  1602. max_height = <1088>;
  1603. bit_per_pixel = <12>;
  1604. frame_count = <3>;
  1605. };
  1606. };
  1607. ry {
  1608. subdev_name = "ry";
  1609. idx = <0>;
  1610. path_type = "ISP_RY_MI_PATH_MP";
  1611. output {
  1612. max_width = <1920>;
  1613. max_height = <1088>;
  1614. bit_per_pixel = <12>;
  1615. frame_count = <3>;
  1616. };
  1617. };
  1618. dw {
  1619. subdev_name = "dw";
  1620. idx = <0>;
  1621. path_type = "DW_DWE_VSE0";
  1622. dw_dst_depth = <2>;
  1623. };
  1624. };
  1625. channel1 {
  1626. sensor0 {
  1627. subdev_name = "vivcam";
  1628. idx = <2>; //<2>=vivcam2 : gc5035
  1629. csi_idx = <0>; //<0>=CSI2
  1630. mode_idx = <3>;
  1631. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  1632. };
  1633. sensor1 {
  1634. subdev_name = "vivcam";
  1635. idx = <3>; //<3>=vivcam3 : gc02m1b
  1636. csi_idx = <0>; //<0>=CSI2
  1637. mode_idx = <0>;
  1638. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1639. };
  1640. dma {
  1641. path_type = "VIPRE_CSI0_ISP0";
  1642. };
  1643. isp {
  1644. subdev_name = "isp";
  1645. idx = <0>;
  1646. path_type = "ISP_MI_PATH_PP";
  1647. output {
  1648. max_width = <1920>;
  1649. max_height = <1088>;
  1650. bit_per_pixel = <12>;
  1651. frame_count = <3>;
  1652. };
  1653. };
  1654. dsp {
  1655. subdev_name = "dsp";
  1656. idx = <1>;
  1657. path_type = "DSP_PATH_ISP_RY";
  1658. output {
  1659. max_width = <1920>;
  1660. max_height = <1088>;
  1661. bit_per_pixel = <12>;
  1662. frame_count = <3>;
  1663. };
  1664. };
  1665. ry {
  1666. subdev_name = "ry";
  1667. idx = <0>;
  1668. path_type = "ISP_RY_MI_PATH_MP";
  1669. output {
  1670. max_width = <1920>;
  1671. max_height = <1088>;
  1672. bit_per_pixel = <12>;
  1673. frame_count = <3>;
  1674. };
  1675. };
  1676. dw {
  1677. subdev_name = "dw";
  1678. idx = <0>;
  1679. path_type = "DW_DWE_VSE1";
  1680. dw_dst_depth = <2>;
  1681. };
  1682. };
  1683. channel2 {
  1684. sensor0 {
  1685. subdev_name = "vivcam";
  1686. idx = <2>; //<2>=vivcam2 : gc5035
  1687. csi_idx = <0>; //<0>=CSI2
  1688. mode_idx = <3>;
  1689. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  1690. };
  1691. sensor1 {
  1692. subdev_name = "vivcam";
  1693. idx = <3>; //<3>=vivcam3 : gc02m1b
  1694. csi_idx = <0>; //<0>=CSI2
  1695. mode_idx = <0>;
  1696. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1697. };
  1698. dma {
  1699. path_type = "VIPRE_CSI0_ISP0";
  1700. };
  1701. isp {
  1702. subdev_name = "isp";
  1703. idx = <0>;
  1704. path_type = "ISP_MI_PATH_PP";
  1705. output {
  1706. max_width = <1920>;
  1707. max_height = <1088>;
  1708. bit_per_pixel = <12>;
  1709. frame_count = <3>;
  1710. };
  1711. };
  1712. dsp {
  1713. subdev_name = "dsp";
  1714. idx = <1>;
  1715. path_type = "DSP_PATH_ISP_RY";
  1716. output {
  1717. max_width = <1920>;
  1718. max_height = <1088>;
  1719. bit_per_pixel = <12>;
  1720. frame_count = <3>;
  1721. };
  1722. };
  1723. ry {
  1724. subdev_name = "ry";
  1725. idx = <0>;
  1726. path_type = "ISP_RY_MI_PATH_MP";
  1727. output {
  1728. max_width = <1920>;
  1729. max_height = <1088>;
  1730. bit_per_pixel = <12>;
  1731. frame_count = <3>;
  1732. };
  1733. };
  1734. dw {
  1735. subdev_name = "dw";
  1736. idx = <0>;
  1737. path_type = "DW_DWE_VSE2";
  1738. dw_dst_depth = <2>;
  1739. };
  1740. };
  1741. };
  1742. &video8{
  1743. vi_mem_pool_region = <1>; // vi_mem: framebuffer, region[1]
  1744. channel0 {
  1745. sensor0 {
  1746. subdev_name = "vivcam";
  1747. idx = <2>; //<2>=vivcam2 : gc5035
  1748. csi_idx = <0>; //<0>=CSI2
  1749. mode_idx = <3>;
  1750. path_type = "SENSOR_1296x972_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  1751. };
  1752. sensor1 {
  1753. subdev_name = "vivcam";
  1754. idx = <3>; //<3>=vivcam3 : gc02m1b
  1755. csi_idx = <0>; //<0>=CSI2
  1756. mode_idx = <0>;
  1757. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1758. };
  1759. dma {
  1760. path_type = "VIPRE_CSI0_DSP";
  1761. };
  1762. dsp {
  1763. subdev_name = "dsp";
  1764. idx = <0>;
  1765. path_type = "DSP_PATH_VIPRE_DDR";
  1766. output {
  1767. max_width = <1920>;
  1768. max_height = <1088>;
  1769. bit_per_pixel = <12>;
  1770. frame_count = <3>;
  1771. };
  1772. };
  1773. };
  1774. };
  1775. &video9{
  1776. channel0 {
  1777. sensor0 {
  1778. subdev_name = "vivcam";
  1779. idx = <1>; //vivcam1 sc132gs
  1780. csi_idx = <2>; //<2>=CSI2X2_A
  1781. mode_idx = <0>;
  1782. path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
  1783. };
  1784. dsp{
  1785. output {
  1786. max_width = <1080>;
  1787. max_height = <1280>;
  1788. bit_per_pixel = <16>;
  1789. frame_count = <3>;
  1790. };
  1791. };
  1792. };
  1793. };
  1794. &video10{ // TUNINGTOOL
  1795. channel0 {
  1796. sensor0 {
  1797. subdev_name = "vivcam";
  1798. idx = <2>; //<2>=vivcam2 : gc5035
  1799. csi_idx = <0>; //<0>=CSI2
  1800. mode_idx = <1>;
  1801. path_type = "SENSOR_1080P_RAW10_LINER"; //SENSOR_VGA_RAW10_LINER//
  1802. skip_init = <1>;
  1803. };
  1804. sensor1 {
  1805. subdev_name = "vivcam";
  1806. idx = <3>; //<3>=vivcam3 : gc02m1b
  1807. csi_idx = <0>; //<0>=CSI2
  1808. mode_idx = <0>;
  1809. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1810. skip_init = <1>;
  1811. };
  1812. dma {
  1813. path_type = "VIPRE_CSI0_ISP0";
  1814. };
  1815. };
  1816. };
  1817. &video11{
  1818. channel0 {
  1819. channel_id = <0>;
  1820. status = "okay";
  1821. sensor0 {
  1822. subdev_name = "vivcam";
  1823. idx = <1>; //sc132gs
  1824. csi_idx = <2>; //<2>=CSI2X2_A
  1825. flash_led_idx = <0>;
  1826. mode_idx = <0>;
  1827. path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
  1828. };
  1829. isp {
  1830. subdev_name = "isp";
  1831. idx = <0>;
  1832. path_type = "ISP_MI_PATH_MP";
  1833. output {
  1834. max_width = <1920>;
  1835. max_height = <1088>;
  1836. bit_per_pixel = <12>;
  1837. frame_count = <3>;
  1838. };
  1839. };
  1840. };
  1841. };
  1842. &video12{ // TUNINGTOOL
  1843. channel0 { // CSI2
  1844. sensor0 {
  1845. subdev_name = "vivcam";
  1846. idx = <0>; //sc2310
  1847. csi_idx = <1>; //<1>=CSI2_B
  1848. mode_idx = <1>;
  1849. path_type = "SENSOR_1920X1088_30FPS_RAW12_LINER";
  1850. skip_init = <1>;
  1851. };
  1852. sensor1 {
  1853. subdev_name = "vivcam";
  1854. idx = <6>; //gc02m1b
  1855. csi_idx = <1>; //<1>=CSI2_B
  1856. mode_idx = <0>;
  1857. path_type = "SENSOR_1600x1200_RAW10_LINER";
  1858. skip_init = <1>;
  1859. };
  1860. };
  1861. dma {
  1862. path_type = "VIPRE_CSI1_ISP0";
  1863. };
  1864. };
  1865. &video13{
  1866. status = "okay";
  1867. //vi_mem_pool_region = <0>;
  1868. channel0 {
  1869. channel_id = <0>;
  1870. status = "okay";
  1871. sensor0 {
  1872. subdev_name = "vivcam";
  1873. idx = <0>; //sc2310
  1874. csi_idx = <1>; //<1>=CSI2_B
  1875. mode_idx = <1>;
  1876. path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
  1877. };
  1878. dma {
  1879. subdev_name = "vipre";
  1880. idx = <0>;
  1881. path_type = "VIPRE_CSI0_ISP0";
  1882. };
  1883. isp {
  1884. subdev_name = "isp";
  1885. idx = <0>;
  1886. path_type = "ISP_MI_MCM_WR0";
  1887. output {
  1888. max_width = <1920>;
  1889. max_height = <1088>;
  1890. bit_per_pixel = <16>;
  1891. frame_count = <3>;
  1892. };
  1893. };
  1894. };
  1895. };
  1896. &video14{
  1897. vi_mem_pool_region = <2>; // vi_mem: framebuffer, region[0]
  1898. status = "okay";
  1899. channel0 {
  1900. channel_id = <0>;
  1901. status = "okay";
  1902. sensor0 {
  1903. subdev_name = "vivcam";
  1904. idx = <1>; //sc132gs
  1905. csi_idx = <2>; //<2>=CSI2X2_A
  1906. flash_led_idx = <0>;
  1907. mode_idx = <0>;
  1908. path_type = "SENSOR_1080X1280_30FPS_RAW10_LINER";
  1909. };
  1910. dma {
  1911. subdev_name = "vipre";
  1912. idx = <0>;
  1913. path_type = "VIPRE_CSI2_ISP1";
  1914. };
  1915. isp {
  1916. subdev_name = "isp";
  1917. idx = <1>;
  1918. path_type = "ISP_MI_MCM_WR0";
  1919. output {
  1920. max_width = <1080>;
  1921. max_height = <1280>;
  1922. bit_per_pixel = <16>;
  1923. frame_count = <3>;
  1924. };
  1925. };
  1926. };
  1927. };
  1928. &video15{
  1929. status = "okay";
  1930. //vi_mem_pool_region = <0>;
  1931. channel0 {
  1932. channel_id = <0>;
  1933. status = "okay";
  1934. sensor0 {
  1935. subdev_name = "vivcam";
  1936. idx = <0>; //<0>=vivcam0 :2310
  1937. csi_idx = <1>; //<1>=CSI2_B
  1938. flash_led_idx = <0>;
  1939. mode_idx = <1>;
  1940. path_type = "SENSOR_1920X1088_26FPS_RAW12_LINER";
  1941. };
  1942. dma {
  1943. subdev_name = "vipre";
  1944. idx = <0>;
  1945. path_type = "VIPRE_CSI0_DDR";
  1946. };
  1947. };
  1948. };
  1949. &trng {
  1950. status = "disabled";
  1951. };
  1952. &eip_28 {
  1953. status = "okay";
  1954. };
  1955. &vdec {
  1956. status = "okay";
  1957. };
  1958. &venc {
  1959. status = "okay";
  1960. };
  1961. &isp_venc_shake {
  1962. status = "okay";
  1963. };
  1964. &vidmem {
  1965. status = "okay";
  1966. memory-region = <&vi_mem>;
  1967. };
  1968. &gpu {
  1969. status = "okay";
  1970. };
  1971. &npu {
  1972. vha_clk_rate = <1000000000>;
  1973. status = "okay";
  1974. };
  1975. &fce {
  1976. memory-region = <&facelib_mem>;
  1977. status = "okay";
  1978. };
  1979. &dpu_enc0 {
  1980. status = "okay";
  1981. ports {
  1982. /* output */
  1983. port@1 {
  1984. reg = <1>;
  1985. enc0_out: endpoint {
  1986. remote-endpoint = <&dsi0_in>;
  1987. };
  1988. };
  1989. };
  1990. };
  1991. &dpu_enc1 {
  1992. ports {
  1993. /delete-node/ port@0;
  1994. };
  1995. };
  1996. &dpu {
  1997. status = "okay";
  1998. };
  1999. &dsi0 {
  2000. status = "okay";
  2001. };
  2002. &dhost_0 {
  2003. ports {
  2004. #address-cells = <1>;
  2005. #size-cells = <0>;
  2006. port@0 {
  2007. reg = <0>;
  2008. dsi0_in: endpoint {
  2009. remote-endpoint = <&enc0_out>;
  2010. };
  2011. };
  2012. port@1 {
  2013. reg = <1>;
  2014. dsi0_out: endpoint {
  2015. remote-endpoint = <&panel0_in>;
  2016. };
  2017. };
  2018. };
  2019. panel0@0 {
  2020. compatible = "i2c_dsi,ili9881d";
  2021. reg = <0>;
  2022. mcu_auto_reset_enable = <0>;
  2023. tp_point_rotate = <0>;
  2024. port {
  2025. panel0_in: endpoint {
  2026. remote-endpoint = <&dsi0_out>;
  2027. };
  2028. };
  2029. };
  2030. };
  2031. &disp1_out {
  2032. remote-endpoint = <&hdmi_tx_in>;
  2033. };
  2034. &hdmi_tx {
  2035. status = "okay";
  2036. port@0 {
  2037. /* input */
  2038. hdmi_tx_in: endpoint {
  2039. remote-endpoint = <&disp1_out>;
  2040. };
  2041. };
  2042. };
  2043. &lightsound {
  2044. status = "okay";
  2045. simple-audio-card,dai-link@0 { /* I2S - AUDIO SYS CODEC 8156*/
  2046. reg = <0>;
  2047. format = "i2s";
  2048. cpu {
  2049. sound-dai = <&i2s1 0>;
  2050. };
  2051. codec {
  2052. sound-dai = <&es8156_audio_codec>;
  2053. };
  2054. };
  2055. simple-audio-card,dai-link@1 { /* I2S - AUDIO SYS CODEC 7210*/
  2056. reg = <1>;
  2057. format = "i2s";
  2058. cpu {
  2059. sound-dai = <&i2s3 0>;
  2060. };
  2061. codec {
  2062. sound-dai = <&es7210_audio_codec>;
  2063. };
  2064. };
  2065. simple-audio-card,dai-link@2 { /* I2S - HDMI */
  2066. reg = <2>;
  2067. format = "i2s";
  2068. cpu {
  2069. sound-dai = <&light_i2s 1>;
  2070. };
  2071. codec {
  2072. sound-dai = <&dummy_codec 2>;
  2073. };
  2074. };
  2075. };
  2076. &light_i2s {
  2077. status = "okay";
  2078. };
  2079. &i2s0 {
  2080. status = "okay";
  2081. };
  2082. &i2s1 {
  2083. status = "okay";
  2084. };
  2085. &i2s3 {
  2086. status = "okay";
  2087. };
  2088. &cpus {
  2089. c910_0: cpu@0 {
  2090. operating-points = <
  2091. /* kHz uV */
  2092. 300000 650000
  2093. 800000 700000
  2094. 1500000 800000
  2095. >;
  2096. light,dvddm-operating-points = <
  2097. /* kHz uV */
  2098. 300000 800000
  2099. 800000 800000
  2100. 1500000 800000
  2101. >;
  2102. };
  2103. c910_1: cpu@1 {
  2104. operating-points = <
  2105. /* kHz uV */
  2106. 300000 650000
  2107. 800000 700000
  2108. 1500000 800000
  2109. >;
  2110. light,dvddm-operating-points = <
  2111. /* kHz uV */
  2112. 300000 800000
  2113. 800000 800000
  2114. 1500000 800000
  2115. >;
  2116. };
  2117. c910_2: cpu@2 {
  2118. operating-points = <
  2119. /* kHz uV */
  2120. 300000 650000
  2121. 800000 700000
  2122. 1500000 800000
  2123. >;
  2124. light,dvddm-operating-points = <
  2125. /* kHz uV */
  2126. 300000 800000
  2127. 800000 800000
  2128. 1500000 800000
  2129. >;
  2130. };
  2131. c910_3: cpu@3 {
  2132. operating-points = <
  2133. /* kHz uV */
  2134. 300000 650000
  2135. 800000 700000
  2136. 1500000 800000
  2137. >;
  2138. light,dvddm-operating-points = <
  2139. /* kHz uV */
  2140. 300000 800000
  2141. 800000 800000
  2142. 1500000 800000
  2143. >;
  2144. };
  2145. };