spinlock.h 2.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * 'Generic' ticket-lock implementation.
  4. *
  5. * It relies on atomic_fetch_add() having well defined forward progress
  6. * guarantees under contention. If your architecture cannot provide this, stick
  7. * to a test-and-set lock.
  8. *
  9. * It also relies on atomic_fetch_add() being safe vs smp_store_release() on a
  10. * sub-word of the value. This is generally true for anything LL/SC although
  11. * you'd be hard pressed to find anything useful in architecture specifications
  12. * about this. If your architecture cannot do this you might be better off with
  13. * a test-and-set.
  14. *
  15. * It further assumes atomic_*_release() + atomic_*_acquire() is RCpc and hence
  16. * uses atomic_fetch_add() which is RCsc to create an RCsc hot path, along with
  17. * a full fence after the spin to upgrade the otherwise-RCpc
  18. * atomic_cond_read_acquire().
  19. *
  20. * The implementation uses smp_cond_load_acquire() to spin, so if the
  21. * architecture has WFE like instructions to sleep instead of poll for word
  22. * modifications be sure to implement that (see ARM64 for example).
  23. *
  24. */
  25. #ifndef __ASM_GENERIC_SPINLOCK_H
  26. #define __ASM_GENERIC_SPINLOCK_H
  27. #include <linux/atomic.h>
  28. #include <asm/spinlock_types.h>
  29. static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
  30. {
  31. u32 val = atomic_fetch_add(1<<16, lock);
  32. u16 ticket = val >> 16;
  33. if (ticket == (u16)val)
  34. return;
  35. /*
  36. * atomic_cond_read_acquire() is RCpc, but rather than defining a
  37. * custom cond_read_rcsc() here we just emit a full fence. We only
  38. * need the prior reads before subsequent writes ordering from
  39. * smb_mb(), but as atomic_cond_read_acquire() just emits reads and we
  40. * have no outstanding writes due to the atomic_fetch_add() the extra
  41. * orderings are free.
  42. */
  43. atomic_cond_read_acquire(lock, ticket == (u16)VAL);
  44. smp_mb();
  45. }
  46. static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock)
  47. {
  48. u32 old = atomic_read(lock);
  49. if ((old >> 16) != (old & 0xffff))
  50. return false;
  51. return atomic_try_cmpxchg(lock, &old, old + (1<<16)); /* SC, for RCsc */
  52. }
  53. static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
  54. {
  55. u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
  56. u32 val = atomic_read(lock);
  57. smp_store_release(ptr, (u16)val + 1);
  58. }
  59. static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock)
  60. {
  61. u32 val = atomic_read(lock);
  62. return ((val >> 16) != (val & 0xffff));
  63. }
  64. static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock)
  65. {
  66. u32 val = atomic_read(lock);
  67. return (s16)((val >> 16) - (val & 0xffff)) > 1;
  68. }
  69. static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
  70. {
  71. return !arch_spin_is_locked(&lock);
  72. }
  73. #include <asm/qrwlock.h>
  74. #endif /* __ASM_GENERIC_SPINLOCK_H */