i2c-designware-master.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Synopsys DesignWare I2C adapter driver (master only).
  4. *
  5. * Based on the TI DAVINCI I2C adapter driver.
  6. *
  7. * Copyright (C) 2006 Texas Instruments.
  8. * Copyright (C) 2007 MontaVista Software Inc.
  9. * Copyright (C) 2009 Provigent Ltd.
  10. */
  11. #include <linux/delay.h>
  12. #include <linux/err.h>
  13. #include <linux/errno.h>
  14. #include <linux/export.h>
  15. #include <linux/gpio/consumer.h>
  16. #include <linux/i2c.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/io.h>
  19. #include <linux/module.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/regmap.h>
  22. #include <linux/reset.h>
  23. #include "i2c-designware-core.h"
  24. static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
  25. {
  26. /* Configure Tx/Rx FIFO threshold levels */
  27. regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2);
  28. regmap_write(dev->map, DW_IC_RX_TL, 0);
  29. /* Configure the I2C master */
  30. regmap_write(dev->map, DW_IC_CON, dev->master_cfg);
  31. }
  32. static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
  33. {
  34. const char *mode_str, *fp_str = "";
  35. u32 comp_param1;
  36. u32 sda_falling_time, scl_falling_time;
  37. struct i2c_timings *t = &dev->timings;
  38. u32 ic_clk;
  39. int ret;
  40. ret = i2c_dw_acquire_lock(dev);
  41. if (ret)
  42. return ret;
  43. ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1);
  44. i2c_dw_release_lock(dev);
  45. if (ret)
  46. return ret;
  47. /* Set standard and fast speed dividers for high/low periods */
  48. sda_falling_time = t->sda_fall_ns ?: 300; /* ns */
  49. scl_falling_time = t->scl_fall_ns ?: 300; /* ns */
  50. /* Calculate SCL timing parameters for standard mode if not set */
  51. if (!dev->ss_hcnt || !dev->ss_lcnt) {
  52. ic_clk = i2c_dw_clk_rate(dev);
  53. dev->ss_hcnt =
  54. i2c_dw_scl_hcnt(ic_clk,
  55. 4000, /* tHD;STA = tHIGH = 4.0 us */
  56. sda_falling_time,
  57. 0, /* 0: DW default, 1: Ideal */
  58. 0); /* No offset */
  59. dev->ss_lcnt =
  60. i2c_dw_scl_lcnt(ic_clk,
  61. 4700, /* tLOW = 4.7 us */
  62. scl_falling_time,
  63. 0); /* No offset */
  64. }
  65. dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n",
  66. dev->ss_hcnt, dev->ss_lcnt);
  67. /*
  68. * Set SCL timing parameters for fast mode or fast mode plus. Only
  69. * difference is the timing parameter values since the registers are
  70. * the same.
  71. */
  72. if (t->bus_freq_hz == 1000000) {
  73. /*
  74. * Check are Fast Mode Plus parameters available. Calculate
  75. * SCL timing parameters for Fast Mode Plus if not set.
  76. */
  77. if (dev->fp_hcnt && dev->fp_lcnt) {
  78. dev->fs_hcnt = dev->fp_hcnt;
  79. dev->fs_lcnt = dev->fp_lcnt;
  80. } else {
  81. ic_clk = i2c_dw_clk_rate(dev);
  82. dev->fs_hcnt =
  83. i2c_dw_scl_hcnt(ic_clk,
  84. 260, /* tHIGH = 260 ns */
  85. sda_falling_time,
  86. 0, /* DW default */
  87. 0); /* No offset */
  88. dev->fs_lcnt =
  89. i2c_dw_scl_lcnt(ic_clk,
  90. 500, /* tLOW = 500 ns */
  91. scl_falling_time,
  92. 0); /* No offset */
  93. }
  94. fp_str = " Plus";
  95. }
  96. /*
  97. * Calculate SCL timing parameters for fast mode if not set. They are
  98. * needed also in high speed mode.
  99. */
  100. if (!dev->fs_hcnt || !dev->fs_lcnt) {
  101. ic_clk = i2c_dw_clk_rate(dev);
  102. dev->fs_hcnt =
  103. i2c_dw_scl_hcnt(ic_clk,
  104. 600, /* tHD;STA = tHIGH = 0.6 us */
  105. sda_falling_time,
  106. 0, /* 0: DW default, 1: Ideal */
  107. 0); /* No offset */
  108. dev->fs_lcnt =
  109. i2c_dw_scl_lcnt(ic_clk,
  110. 1300, /* tLOW = 1.3 us */
  111. scl_falling_time,
  112. 0); /* No offset */
  113. }
  114. dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n",
  115. fp_str, dev->fs_hcnt, dev->fs_lcnt);
  116. /* Check is high speed possible and fall back to fast mode if not */
  117. if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
  118. DW_IC_CON_SPEED_HIGH) {
  119. if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
  120. != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
  121. dev_err(dev->dev, "High Speed not supported!\n");
  122. t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
  123. dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
  124. dev->master_cfg |= DW_IC_CON_SPEED_FAST;
  125. dev->hs_hcnt = 0;
  126. dev->hs_lcnt = 0;
  127. } else if (!dev->hs_hcnt || !dev->hs_lcnt) {
  128. ic_clk = i2c_dw_clk_rate(dev);
  129. dev->hs_hcnt =
  130. i2c_dw_scl_hcnt(ic_clk,
  131. 160, /* tHIGH = 160 ns */
  132. sda_falling_time,
  133. 0, /* DW default */
  134. 0); /* No offset */
  135. dev->hs_lcnt =
  136. i2c_dw_scl_lcnt(ic_clk,
  137. 320, /* tLOW = 320 ns */
  138. scl_falling_time,
  139. 0); /* No offset */
  140. }
  141. dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
  142. dev->hs_hcnt, dev->hs_lcnt);
  143. }
  144. ret = i2c_dw_set_sda_hold(dev);
  145. if (ret)
  146. goto out;
  147. switch (dev->master_cfg & DW_IC_CON_SPEED_MASK) {
  148. case DW_IC_CON_SPEED_STD:
  149. mode_str = "Standard Mode";
  150. break;
  151. case DW_IC_CON_SPEED_HIGH:
  152. mode_str = "High Speed Mode";
  153. break;
  154. default:
  155. mode_str = "Fast Mode";
  156. }
  157. dev_dbg(dev->dev, "Bus speed: %s%s\n", mode_str, fp_str);
  158. out:
  159. return ret;
  160. }
  161. /**
  162. * i2c_dw_init() - Initialize the designware I2C master hardware
  163. * @dev: device private data
  164. *
  165. * This functions configures and enables the I2C master.
  166. * This function is called during I2C init function, and in case of timeout at
  167. * run time.
  168. */
  169. static int i2c_dw_init_master(struct dw_i2c_dev *dev)
  170. {
  171. int ret;
  172. ret = i2c_dw_acquire_lock(dev);
  173. if (ret)
  174. return ret;
  175. /* Disable the adapter */
  176. __i2c_dw_disable(dev);
  177. /* Write standard speed timing parameters */
  178. regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
  179. regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
  180. /* Write fast mode/fast mode plus timing parameters */
  181. regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
  182. regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
  183. /* Write high speed timing parameters if supported */
  184. if (dev->hs_hcnt && dev->hs_lcnt) {
  185. regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);
  186. regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt);
  187. }
  188. /* Write SDA hold time if supported */
  189. if (dev->sda_hold_time)
  190. regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
  191. i2c_dw_configure_fifo_master(dev);
  192. i2c_dw_release_lock(dev);
  193. return 0;
  194. }
  195. static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
  196. {
  197. struct i2c_msg *msgs = dev->msgs;
  198. u32 ic_con = 0, ic_tar = 0;
  199. u32 dummy;
  200. /* Disable the adapter */
  201. __i2c_dw_disable(dev);
  202. /* If the slave address is ten bit address, enable 10BITADDR */
  203. if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
  204. ic_con = DW_IC_CON_10BITADDR_MASTER;
  205. /*
  206. * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
  207. * mode has to be enabled via bit 12 of IC_TAR register.
  208. * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
  209. * detected from registers.
  210. */
  211. ic_tar = DW_IC_TAR_10BITADDR_MASTER;
  212. }
  213. regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER,
  214. ic_con);
  215. /*
  216. * Set the slave (target) address and enable 10-bit addressing mode
  217. * if applicable.
  218. */
  219. regmap_write(dev->map, DW_IC_TAR,
  220. msgs[dev->msg_write_idx].addr | ic_tar);
  221. /* Enforce disabled interrupts (due to HW issues) */
  222. i2c_dw_disable_int(dev);
  223. /* Enable the adapter */
  224. __i2c_dw_enable(dev);
  225. /* Dummy read to avoid the register getting stuck on Bay Trail */
  226. regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy);
  227. /* Clear and enable interrupts */
  228. regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
  229. regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK);
  230. }
  231. /*
  232. * Initiate (and continue) low level master read/write transaction.
  233. * This function is only called from i2c_dw_isr, and pumping i2c_msg
  234. * messages into the tx buffer. Even if the size of i2c_msg data is
  235. * longer than the size of the tx buffer, it handles everything.
  236. */
  237. static void
  238. i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
  239. {
  240. struct i2c_msg *msgs = dev->msgs;
  241. u32 intr_mask;
  242. int tx_limit, rx_limit;
  243. u32 addr = msgs[dev->msg_write_idx].addr;
  244. u32 buf_len = dev->tx_buf_len;
  245. u8 *buf = dev->tx_buf;
  246. bool need_restart = false;
  247. unsigned int flr;
  248. intr_mask = DW_IC_INTR_MASTER_MASK;
  249. for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
  250. u32 flags = msgs[dev->msg_write_idx].flags;
  251. /*
  252. * If target address has changed, we need to
  253. * reprogram the target address in the I2C
  254. * adapter when we are done with this transfer.
  255. */
  256. if (msgs[dev->msg_write_idx].addr != addr) {
  257. dev_err(dev->dev,
  258. "%s: invalid target address\n", __func__);
  259. dev->msg_err = -EINVAL;
  260. break;
  261. }
  262. if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
  263. /* new i2c_msg */
  264. buf = msgs[dev->msg_write_idx].buf;
  265. buf_len = msgs[dev->msg_write_idx].len;
  266. /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
  267. * IC_RESTART_EN are set, we must manually
  268. * set restart bit between messages.
  269. */
  270. if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
  271. (dev->msg_write_idx > 0))
  272. need_restart = true;
  273. }
  274. regmap_read(dev->map, DW_IC_TXFLR, &flr);
  275. tx_limit = dev->tx_fifo_depth - flr;
  276. regmap_read(dev->map, DW_IC_RXFLR, &flr);
  277. rx_limit = dev->rx_fifo_depth - flr;
  278. while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
  279. u32 cmd = 0;
  280. /*
  281. * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
  282. * manually set the stop bit. However, it cannot be
  283. * detected from the registers so we set it always
  284. * when writing/reading the last byte.
  285. */
  286. /*
  287. * i2c-core always sets the buffer length of
  288. * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will
  289. * be adjusted when receiving the first byte.
  290. * Thus we can't stop the transaction here.
  291. */
  292. if (dev->msg_write_idx == dev->msgs_num - 1 &&
  293. buf_len == 1 && !(flags & I2C_M_RECV_LEN))
  294. cmd |= BIT(9);
  295. if (need_restart) {
  296. cmd |= BIT(10);
  297. need_restart = false;
  298. }
  299. if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
  300. /* Avoid rx buffer overrun */
  301. if (dev->rx_outstanding >= dev->rx_fifo_depth)
  302. break;
  303. regmap_write(dev->map, DW_IC_DATA_CMD,
  304. cmd | 0x100);
  305. rx_limit--;
  306. dev->rx_outstanding++;
  307. } else {
  308. regmap_write(dev->map, DW_IC_DATA_CMD,
  309. cmd | *buf++);
  310. }
  311. tx_limit--; buf_len--;
  312. }
  313. dev->tx_buf = buf;
  314. dev->tx_buf_len = buf_len;
  315. /*
  316. * Because we don't know the buffer length in the
  317. * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop
  318. * the transaction here.
  319. */
  320. if (buf_len > 0 || flags & I2C_M_RECV_LEN) {
  321. /* more bytes to be written */
  322. dev->status |= STATUS_WRITE_IN_PROGRESS;
  323. break;
  324. } else
  325. dev->status &= ~STATUS_WRITE_IN_PROGRESS;
  326. }
  327. /*
  328. * If i2c_msg index search is completed, we don't need TX_EMPTY
  329. * interrupt any more.
  330. */
  331. if (dev->msg_write_idx == dev->msgs_num)
  332. intr_mask &= ~DW_IC_INTR_TX_EMPTY;
  333. if (dev->msg_err)
  334. intr_mask = 0;
  335. regmap_write(dev->map, DW_IC_INTR_MASK, intr_mask);
  336. }
  337. static u8
  338. i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
  339. {
  340. struct i2c_msg *msgs = dev->msgs;
  341. u32 flags = msgs[dev->msg_read_idx].flags;
  342. /*
  343. * Adjust the buffer length and mask the flag
  344. * after receiving the first byte.
  345. */
  346. len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
  347. dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
  348. msgs[dev->msg_read_idx].len = len;
  349. msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
  350. return len;
  351. }
  352. static void
  353. i2c_dw_read(struct dw_i2c_dev *dev)
  354. {
  355. struct i2c_msg *msgs = dev->msgs;
  356. unsigned int rx_valid;
  357. for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
  358. u32 len, tmp;
  359. u8 *buf;
  360. if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
  361. continue;
  362. if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
  363. len = msgs[dev->msg_read_idx].len;
  364. buf = msgs[dev->msg_read_idx].buf;
  365. } else {
  366. len = dev->rx_buf_len;
  367. buf = dev->rx_buf;
  368. }
  369. regmap_read(dev->map, DW_IC_RXFLR, &rx_valid);
  370. for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
  371. u32 flags = msgs[dev->msg_read_idx].flags;
  372. regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
  373. /* Ensure length byte is a valid value */
  374. if (flags & I2C_M_RECV_LEN &&
  375. tmp <= I2C_SMBUS_BLOCK_MAX && tmp > 0) {
  376. len = i2c_dw_recv_len(dev, tmp);
  377. }
  378. *buf++ = tmp;
  379. dev->rx_outstanding--;
  380. }
  381. if (len > 0) {
  382. dev->status |= STATUS_READ_IN_PROGRESS;
  383. dev->rx_buf_len = len;
  384. dev->rx_buf = buf;
  385. return;
  386. } else
  387. dev->status &= ~STATUS_READ_IN_PROGRESS;
  388. }
  389. }
  390. /*
  391. * Prepare controller for a transaction and call i2c_dw_xfer_msg.
  392. */
  393. static int
  394. i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
  395. {
  396. struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
  397. int ret;
  398. dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
  399. pm_runtime_get_sync(dev->dev);
  400. if (dev_WARN_ONCE(dev->dev, dev->suspended, "Transfer while suspended\n")) {
  401. ret = -ESHUTDOWN;
  402. goto done_nolock;
  403. }
  404. reinit_completion(&dev->cmd_complete);
  405. dev->msgs = msgs;
  406. dev->msgs_num = num;
  407. dev->cmd_err = 0;
  408. dev->msg_write_idx = 0;
  409. dev->msg_read_idx = 0;
  410. dev->msg_err = 0;
  411. dev->status = STATUS_IDLE;
  412. dev->abort_source = 0;
  413. dev->rx_outstanding = 0;
  414. ret = i2c_dw_acquire_lock(dev);
  415. if (ret)
  416. goto done_nolock;
  417. ret = i2c_dw_wait_bus_not_busy(dev);
  418. if (ret < 0)
  419. goto done;
  420. /* Start the transfers */
  421. i2c_dw_xfer_init(dev);
  422. /* Wait for tx to complete */
  423. if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
  424. dev_err(dev->dev, "controller timed out\n");
  425. /* i2c_dw_init implicitly disables the adapter */
  426. i2c_recover_bus(&dev->adapter);
  427. i2c_dw_init_master(dev);
  428. ret = -ETIMEDOUT;
  429. goto done;
  430. }
  431. /*
  432. * We must disable the adapter before returning and signaling the end
  433. * of the current transfer. Otherwise the hardware might continue
  434. * generating interrupts which in turn causes a race condition with
  435. * the following transfer. Needs some more investigation if the
  436. * additional interrupts are a hardware bug or this driver doesn't
  437. * handle them correctly yet.
  438. */
  439. __i2c_dw_disable_nowait(dev);
  440. if (dev->msg_err) {
  441. ret = dev->msg_err;
  442. goto done;
  443. }
  444. /* No error */
  445. if (likely(!dev->cmd_err && !dev->status)) {
  446. ret = num;
  447. goto done;
  448. }
  449. /* We have an error */
  450. if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
  451. ret = i2c_dw_handle_tx_abort(dev);
  452. goto done;
  453. }
  454. if (dev->status)
  455. dev_err(dev->dev,
  456. "transfer terminated early - interrupt latency too high?\n");
  457. ret = -EIO;
  458. done:
  459. i2c_dw_release_lock(dev);
  460. done_nolock:
  461. pm_runtime_mark_last_busy(dev->dev);
  462. pm_runtime_put_autosuspend(dev->dev);
  463. return ret;
  464. }
  465. static const struct i2c_algorithm i2c_dw_algo = {
  466. .master_xfer = i2c_dw_xfer,
  467. .functionality = i2c_dw_func,
  468. };
  469. static const struct i2c_adapter_quirks i2c_dw_quirks = {
  470. .flags = I2C_AQ_NO_ZERO_LEN,
  471. };
  472. static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
  473. {
  474. u32 stat, dummy;
  475. /*
  476. * The IC_INTR_STAT register just indicates "enabled" interrupts.
  477. * The unmasked raw version of interrupt status bits is available
  478. * in the IC_RAW_INTR_STAT register.
  479. *
  480. * That is,
  481. * stat = readl(IC_INTR_STAT);
  482. * equals to,
  483. * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK);
  484. *
  485. * The raw version might be useful for debugging purposes.
  486. */
  487. regmap_read(dev->map, DW_IC_INTR_STAT, &stat);
  488. /*
  489. * Do not use the IC_CLR_INTR register to clear interrupts, or
  490. * you'll miss some interrupts, triggered during the period from
  491. * readl(IC_INTR_STAT) to readl(IC_CLR_INTR).
  492. *
  493. * Instead, use the separately-prepared IC_CLR_* registers.
  494. */
  495. if (stat & DW_IC_INTR_RX_UNDER)
  496. regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);
  497. if (stat & DW_IC_INTR_RX_OVER)
  498. regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);
  499. if (stat & DW_IC_INTR_TX_OVER)
  500. regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);
  501. if (stat & DW_IC_INTR_RD_REQ)
  502. regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy);
  503. if (stat & DW_IC_INTR_TX_ABRT) {
  504. /*
  505. * The IC_TX_ABRT_SOURCE register is cleared whenever
  506. * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
  507. */
  508. regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source);
  509. regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
  510. }
  511. if (stat & DW_IC_INTR_RX_DONE)
  512. regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);
  513. if (stat & DW_IC_INTR_ACTIVITY)
  514. regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);
  515. if (stat & DW_IC_INTR_STOP_DET)
  516. regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);
  517. if (stat & DW_IC_INTR_START_DET)
  518. regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);
  519. if (stat & DW_IC_INTR_GEN_CALL)
  520. regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);
  521. return stat;
  522. }
  523. /*
  524. * Interrupt service routine. This gets called whenever an I2C master interrupt
  525. * occurs.
  526. */
  527. static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
  528. {
  529. u32 stat, status;
  530. stat = i2c_dw_read_clear_intrbits(dev);
  531. if (stat & DW_IC_INTR_TX_ABRT) {
  532. dev->cmd_err |= DW_IC_ERR_TX_ABRT;
  533. dev->status = STATUS_IDLE;
  534. /*
  535. * Anytime TX_ABRT is set, the contents of the tx/rx
  536. * buffers are flushed. Make sure to skip them.
  537. */
  538. regmap_write(dev->map, DW_IC_INTR_MASK, 0);
  539. goto tx_aborted;
  540. }
  541. if (stat & DW_IC_INTR_RX_FULL)
  542. i2c_dw_read(dev);
  543. if (stat & DW_IC_INTR_TX_EMPTY)
  544. i2c_dw_xfer_msg(dev);
  545. /*
  546. * No need to modify or disable the interrupt mask here.
  547. * i2c_dw_xfer_msg() will take care of it according to
  548. * the current transmit status.
  549. */
  550. tx_aborted:
  551. regmap_read(dev->map, DW_IC_STATUS, &status);
  552. if ((stat & DW_IC_INTR_TX_ABRT) || dev->msg_err ||
  553. ((status & DW_IC_STATUS_TFE) &&
  554. (!(status & DW_IC_STATUS_RFNE)) &&
  555. (!(status & DW_IC_STATUS_MASTER_ACTIVITY))))
  556. complete(&dev->cmd_complete);
  557. else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
  558. /* Workaround to trigger pending interrupt */
  559. regmap_read(dev->map, DW_IC_INTR_MASK, &stat);
  560. i2c_dw_disable_int(dev);
  561. regmap_write(dev->map, DW_IC_INTR_MASK, stat);
  562. }
  563. return 0;
  564. }
  565. static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
  566. {
  567. struct dw_i2c_dev *dev = dev_id;
  568. u32 stat, enabled;
  569. regmap_read(dev->map, DW_IC_ENABLE, &enabled);
  570. regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat);
  571. dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
  572. if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
  573. return IRQ_NONE;
  574. i2c_dw_irq_handler_master(dev);
  575. return IRQ_HANDLED;
  576. }
  577. void i2c_dw_configure_master(struct dw_i2c_dev *dev)
  578. {
  579. struct i2c_timings *t = &dev->timings;
  580. dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY;
  581. dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
  582. DW_IC_CON_RESTART_EN;
  583. dev->mode = DW_IC_MASTER;
  584. switch (t->bus_freq_hz) {
  585. case I2C_MAX_STANDARD_MODE_FREQ:
  586. dev->master_cfg |= DW_IC_CON_SPEED_STD;
  587. break;
  588. case I2C_MAX_HIGH_SPEED_MODE_FREQ:
  589. dev->master_cfg |= DW_IC_CON_SPEED_HIGH;
  590. break;
  591. default:
  592. dev->master_cfg |= DW_IC_CON_SPEED_FAST;
  593. }
  594. }
  595. EXPORT_SYMBOL_GPL(i2c_dw_configure_master);
  596. static void i2c_dw_prepare_recovery(struct i2c_adapter *adap)
  597. {
  598. struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
  599. i2c_dw_disable(dev);
  600. reset_control_assert(dev->rst);
  601. i2c_dw_prepare_clk(dev, false);
  602. }
  603. static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap)
  604. {
  605. struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
  606. i2c_dw_prepare_clk(dev, true);
  607. reset_control_deassert(dev->rst);
  608. i2c_dw_init_master(dev);
  609. }
  610. static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
  611. {
  612. struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
  613. struct i2c_adapter *adap = &dev->adapter;
  614. struct gpio_desc *gpio;
  615. gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH);
  616. if (IS_ERR_OR_NULL(gpio))
  617. return PTR_ERR_OR_ZERO(gpio);
  618. rinfo->scl_gpiod = gpio;
  619. gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN);
  620. if (IS_ERR(gpio))
  621. return PTR_ERR(gpio);
  622. rinfo->sda_gpiod = gpio;
  623. rinfo->recover_bus = i2c_generic_scl_recovery;
  624. rinfo->prepare_recovery = i2c_dw_prepare_recovery;
  625. rinfo->unprepare_recovery = i2c_dw_unprepare_recovery;
  626. adap->bus_recovery_info = rinfo;
  627. dev_info(dev->dev, "running with gpio recovery mode! scl%s",
  628. rinfo->sda_gpiod ? ",sda" : "");
  629. return 0;
  630. }
  631. int i2c_dw_probe_master(struct dw_i2c_dev *dev)
  632. {
  633. struct i2c_adapter *adap = &dev->adapter;
  634. unsigned long irq_flags;
  635. int ret;
  636. init_completion(&dev->cmd_complete);
  637. dev->init = i2c_dw_init_master;
  638. dev->disable = i2c_dw_disable;
  639. dev->disable_int = i2c_dw_disable_int;
  640. ret = i2c_dw_init_regmap(dev);
  641. if (ret)
  642. return ret;
  643. ret = i2c_dw_set_timings_master(dev);
  644. if (ret)
  645. return ret;
  646. ret = i2c_dw_set_fifo_size(dev);
  647. if (ret)
  648. return ret;
  649. ret = dev->init(dev);
  650. if (ret)
  651. return ret;
  652. snprintf(adap->name, sizeof(adap->name),
  653. "Synopsys DesignWare I2C adapter");
  654. adap->retries = 3;
  655. adap->algo = &i2c_dw_algo;
  656. adap->quirks = &i2c_dw_quirks;
  657. adap->dev.parent = dev->dev;
  658. i2c_set_adapdata(adap, dev);
  659. if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
  660. irq_flags = IRQF_NO_SUSPEND;
  661. } else {
  662. irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
  663. }
  664. i2c_dw_disable_int(dev);
  665. ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
  666. dev_name(dev->dev), dev);
  667. if (ret) {
  668. dev_err(dev->dev, "failure requesting irq %i: %d\n",
  669. dev->irq, ret);
  670. return ret;
  671. }
  672. ret = i2c_dw_init_recovery_info(dev);
  673. if (ret)
  674. return ret;
  675. /*
  676. * Increment PM usage count during adapter registration in order to
  677. * avoid possible spurious runtime suspend when adapter device is
  678. * registered to the device core and immediate resume in case bus has
  679. * registered I2C slaves that do I2C transfers in their probe.
  680. */
  681. pm_runtime_get_noresume(dev->dev);
  682. ret = i2c_add_numbered_adapter(adap);
  683. if (ret)
  684. dev_err(dev->dev, "failure adding adapter: %d\n", ret);
  685. pm_runtime_put_noidle(dev->dev);
  686. return ret;
  687. }
  688. EXPORT_SYMBOL_GPL(i2c_dw_probe_master);
  689. MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
  690. MODULE_LICENSE("GPL");