light-mpw-cpufreq.c 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2021 Alibaba Group Holding Limited.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/cpu.h>
  7. #include <linux/cpufreq.h>
  8. #include <linux/delay.h>
  9. #include <linux/err.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_address.h>
  13. #include <linux/pm_opp.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/reboot.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/suspend.h>
  18. #include <linux/clk-provider.h>
  19. #include <linux/smp.h>
  20. static DEFINE_MUTEX(cpufreq_lock);
  21. bool cpufreq_denied = false;
  22. struct regulator *dvdd_cpu_reg;
  23. struct regulator *dvddm_cpu_reg;
  24. enum LIGHT_MPW_CPUFREQ_CLKS {
  25. LIGHT_C910_CCLK,
  26. LIGHT_C910_CCLK_I0,
  27. LIGHT_CPU_PLL1_FOUTPOSTDIV,
  28. LIGHT_CPU_PLL0_FOUTPOSTDIV,
  29. };
  30. #define LIGHT_MPW_CPUFREQ_CLK_NUM 4
  31. #define LIGHT_CPUFREQ_THRE 1500000
  32. #define LIGHT_C910_BUS_CLK_SYNC BIT(11)
  33. #define LIGHT_C910_BUS_CLK_RATIO_MASK 0x700
  34. #define LIGHT_C910_BUS_CLK_DIV_RATIO_2 0x100
  35. #define LIGHT_C910_BUS_CLK_DIV_RATIO_3 0x200
  36. static int num_clks;
  37. static struct clk_bulk_data clks[] = {
  38. { .id = "c910_cclk" },
  39. { .id = "c910_cclk_i0" },
  40. { .id = "cpu_pll1_foutpostdiv" },
  41. { .id = "cpu_pll0_foutpostdiv" },
  42. };
  43. static struct device *cpu_dev;
  44. static struct cpufreq_frequency_table *freq_table;
  45. static unsigned int max_freq;
  46. static unsigned int transition_latency;
  47. static void __iomem *ap_sys_reg;
  48. static bool light_dvfs_sv = false;
  49. static u32 *light_dvddm_volt;
  50. static u32 soc_opp_count = 0;
  51. static int light_set_target(struct cpufreq_policy *policy, unsigned int index)
  52. {
  53. struct dev_pm_opp *opp;
  54. unsigned long freq_hz;
  55. int volt, volt_old;
  56. unsigned int old_freq, new_freq;
  57. int ret;
  58. u32 val;
  59. u32 re_modify_bus_freq = 0;
  60. mutex_lock(&cpufreq_lock);
  61. if (cpufreq_denied) {
  62. dev_emerg(cpu_dev, "Denied to set cpu frequency temporarily on reboot\n");
  63. mutex_unlock(&cpufreq_lock);
  64. return 0;
  65. }
  66. new_freq = freq_table[index].frequency;
  67. freq_hz = new_freq * 1000;
  68. old_freq = policy->cur;
  69. opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
  70. if (IS_ERR(opp)) {
  71. dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
  72. mutex_unlock(&cpufreq_lock);
  73. return PTR_ERR(opp);
  74. }
  75. volt = dev_pm_opp_get_voltage(opp);
  76. dev_pm_opp_put(opp);
  77. volt_old = regulator_get_voltage(dvdd_cpu_reg);
  78. if (volt_old < 0) {
  79. dev_err(cpu_dev, "failed to get cpu voltage\n");
  80. mutex_unlock(&cpufreq_lock);
  81. return volt_old;
  82. }
  83. dev_dbg(cpu_dev, "%u MHz, %d mV --> %u MHz, %d mV\n",
  84. old_freq / 1000, volt_old / 1000,
  85. new_freq / 1000, volt / 1000);
  86. /* change AXI bus clock ratio to match: BUS_CLK = CPU_CCLK/ratio <= 750MHz */
  87. val = readl(ap_sys_reg);
  88. if (new_freq > LIGHT_CPUFREQ_THRE) {
  89. val &= ~LIGHT_C910_BUS_CLK_RATIO_MASK;
  90. val |= LIGHT_C910_BUS_CLK_DIV_RATIO_3;
  91. } else {
  92. val &= ~LIGHT_C910_BUS_CLK_RATIO_MASK;
  93. if (old_freq > LIGHT_CPUFREQ_THRE) {
  94. re_modify_bus_freq = 1;
  95. val |= LIGHT_C910_BUS_CLK_DIV_RATIO_3;
  96. }else
  97. val |= LIGHT_C910_BUS_CLK_DIV_RATIO_2;
  98. }
  99. writel(val, ap_sys_reg);
  100. val &= ~LIGHT_C910_BUS_CLK_SYNC;
  101. writel(val, ap_sys_reg);
  102. udelay(1);
  103. val |= LIGHT_C910_BUS_CLK_SYNC;
  104. writel(val, ap_sys_reg);
  105. udelay(1);
  106. /* scaling up? scale voltage before frequency */
  107. if (new_freq > old_freq && !light_dvfs_sv) {
  108. ret = regulator_set_voltage_tol(dvddm_cpu_reg, light_dvddm_volt[index], 0);
  109. if (ret) {
  110. dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
  111. mutex_unlock(&cpufreq_lock);
  112. return ret;
  113. }
  114. ret = regulator_set_voltage_tol(dvdd_cpu_reg, volt, 0);
  115. if (ret) {
  116. dev_err(cpu_dev,
  117. "failed to scale vddarm up: %d\n", ret);
  118. mutex_unlock(&cpufreq_lock);
  119. return ret;
  120. }
  121. }
  122. if (!strcmp(__clk_get_name(clk_get_parent(clks[LIGHT_C910_CCLK].clk)),
  123. __clk_get_name(clks[LIGHT_C910_CCLK_I0].clk))) {
  124. clk_prepare_enable(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk);
  125. clk_set_rate(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk, new_freq * 1000);
  126. ret = clk_set_parent(clks[LIGHT_C910_CCLK].clk, clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk);
  127. udelay(1);
  128. clk_disable_unprepare(clks[LIGHT_CPU_PLL0_FOUTPOSTDIV].clk);
  129. } else {
  130. clk_prepare_enable(clks[LIGHT_CPU_PLL0_FOUTPOSTDIV].clk);
  131. clk_set_rate(clks[LIGHT_CPU_PLL0_FOUTPOSTDIV].clk, new_freq * 1000);
  132. ret = clk_set_parent(clks[LIGHT_C910_CCLK].clk, clks[LIGHT_C910_CCLK_I0].clk);
  133. udelay(1);
  134. clk_disable_unprepare(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk);
  135. }
  136. /*add delay for clk-switch*/
  137. udelay(1);
  138. /* Ensure the c910_cclk clock divider is what we expect */
  139. ret = clk_set_rate(clks[LIGHT_C910_CCLK].clk, new_freq * 1000);
  140. if (ret) {
  141. int ret1;
  142. dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
  143. ret1 = regulator_set_voltage_tol(dvdd_cpu_reg, volt_old, 0);
  144. if (ret1)
  145. dev_err(cpu_dev, "failed to restore dvdd_cpu voltage: %d\n", ret1);
  146. mutex_unlock(&cpufreq_lock);
  147. return ret;
  148. }
  149. /* scaling down? scale voltage after frequency */
  150. if (new_freq < old_freq && !light_dvfs_sv) {
  151. ret = regulator_set_voltage_tol(dvddm_cpu_reg, light_dvddm_volt[index], 0);
  152. if (ret)
  153. dev_err(cpu_dev, "failed to scale dvddm down: %d\n", ret);
  154. ret = regulator_set_voltage_tol(dvdd_cpu_reg, volt, 0);
  155. if (ret)
  156. dev_err(cpu_dev, "failed to scale dvdd_cpu down: %d\n", ret);
  157. }
  158. val = readl(ap_sys_reg);
  159. if (re_modify_bus_freq) {
  160. val &= ~LIGHT_C910_BUS_CLK_RATIO_MASK;
  161. val |= LIGHT_C910_BUS_CLK_DIV_RATIO_2;
  162. writel(val, ap_sys_reg);
  163. val &= ~LIGHT_C910_BUS_CLK_SYNC;
  164. writel(val, ap_sys_reg);
  165. udelay(1);
  166. val |= LIGHT_C910_BUS_CLK_SYNC;
  167. writel(val, ap_sys_reg);
  168. udelay(1);
  169. }
  170. mutex_unlock(&cpufreq_lock);
  171. return 0;
  172. }
  173. static int light_cpufreq_init(struct cpufreq_policy *policy)
  174. {
  175. policy->clk = clks[LIGHT_C910_CCLK].clk;
  176. policy->cur = clk_get_rate(policy->clk) / 1000;
  177. cpufreq_generic_init(policy, freq_table, transition_latency);
  178. policy->suspend_freq = max_freq;
  179. dev_pm_opp_of_register_em(cpu_dev, policy->cpus);
  180. return 0;
  181. }
  182. static int light_cpufreq_reboot_notifier(struct notifier_block *this,
  183. unsigned long event, void *ptr)
  184. {
  185. mutex_lock(&cpufreq_lock);
  186. cpufreq_denied = true;
  187. mutex_unlock(&cpufreq_lock);
  188. return NOTIFY_DONE;
  189. }
  190. static struct notifier_block cpufreq_reboot_notifier = {
  191. .notifier_call = light_cpufreq_reboot_notifier,
  192. };
  193. static struct cpufreq_driver light_cpufreq_driver = {
  194. .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
  195. CPUFREQ_IS_COOLING_DEV,
  196. .verify = cpufreq_generic_frequency_table_verify,
  197. .target_index = light_set_target,
  198. .get = cpufreq_generic_get,
  199. .init = light_cpufreq_init,
  200. .name = "light-cpufreq",
  201. .attr = cpufreq_generic_attr,
  202. .suspend = cpufreq_generic_suspend,
  203. };
  204. static int light_cpufreq_pm_notify(struct notifier_block *nb,
  205. unsigned long event, void *dummy)
  206. {
  207. switch (event) {
  208. case PM_SUSPEND_PREPARE:
  209. /* TBD */
  210. break;
  211. case PM_POST_SUSPEND:
  212. /* TBD */
  213. break;
  214. default:
  215. break;
  216. }
  217. return NOTIFY_OK;
  218. }
  219. static struct notifier_block light_cpufreq_pm_notifier = {
  220. .notifier_call = light_cpufreq_pm_notify,
  221. };
  222. /*
  223. * Set CPU PLL1's frequency as minimum on panic
  224. */
  225. static int panic_cpufreq_notifier_call(struct notifier_block *nb,
  226. unsigned long action, void *data)
  227. {
  228. int cpu = smp_processor_id();
  229. struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
  230. u32 val = readl(ap_sys_reg);
  231. pr_info("enter panic_cpufreq_notifier_call\n");
  232. /*
  233. * set CPU PLL1's frequency as minimum to compatible voltage
  234. * becarefull if the PLL1 is serving the cpu core, swith to PLL0 first
  235. */
  236. if (strcmp(__clk_get_name(clk_get_parent(clks[LIGHT_C910_CCLK].clk)),
  237. __clk_get_name(clks[LIGHT_C910_CCLK_I0].clk))) {
  238. pr_debug("[%s,%d]\n", __func__, __LINE__);
  239. clk_prepare_enable(clks[LIGHT_CPU_PLL0_FOUTPOSTDIV].clk);
  240. clk_set_rate(clks[LIGHT_CPU_PLL0_FOUTPOSTDIV].clk, policy->min * 1000);
  241. udelay(1);
  242. clk_set_parent(clks[LIGHT_C910_CCLK].clk, clks[LIGHT_C910_CCLK_I0].clk);
  243. pr_debug("[%s,%d]\n", __func__, __LINE__);
  244. }
  245. pr_debug("[%s,%d]\n", __func__, __LINE__);
  246. /*
  247. * since the clk driver will use PLL1 as the default clock source,
  248. * in order to compatible voltage which is unpredictable we should
  249. * set the CPU PLL1's frequency as minimum in advance, otherwise the
  250. * system may crash in crash kernel stage.
  251. */
  252. clk_prepare_enable(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk);
  253. clk_set_rate(clks[LIGHT_CPU_PLL1_FOUTPOSTDIV].clk, policy->min * 1000);
  254. udelay(1);
  255. pr_info("finish to execute cpufreq notifier callback on panic\n");
  256. return 0;
  257. }
  258. static struct notifier_block panic_cpufreq_notifier = {
  259. .notifier_call = panic_cpufreq_notifier_call,
  260. };
  261. static int light_cpufreq_probe(struct platform_device *pdev)
  262. {
  263. struct device_node *np;
  264. int num, ret;
  265. const struct property *prop;
  266. const __be32 *val;
  267. u32 nr, i, j;
  268. np = of_find_compatible_node(NULL, NULL, "thead,light_sys_reg");
  269. if (!np)
  270. return -ENOENT;
  271. ap_sys_reg = of_iomap(np, 0);
  272. WARN_ON(!ap_sys_reg);
  273. cpu_dev = get_cpu_device(0);
  274. if (!cpu_dev) {
  275. pr_err("failed to get cpu0 device\n");
  276. return -ENODEV;
  277. }
  278. np = of_node_get(cpu_dev->of_node);
  279. if (!np) {
  280. dev_err(cpu_dev, "failed to find cpu0 node\n");
  281. return -ENOENT;
  282. }
  283. num_clks = LIGHT_MPW_CPUFREQ_CLK_NUM;
  284. ret = clk_bulk_get(cpu_dev, num_clks, clks);
  285. if (ret)
  286. goto put_node;
  287. dvdd_cpu_reg = regulator_get(cpu_dev, "dvdd");
  288. dvddm_cpu_reg = regulator_get(cpu_dev, "dvddm");
  289. if (PTR_ERR(dvdd_cpu_reg) == -EPROBE_DEFER ||
  290. PTR_ERR(dvddm_cpu_reg) == -EPROBE_DEFER) {
  291. ret = -EPROBE_DEFER;
  292. dev_dbg(cpu_dev, "regulators not ready, defer\n");
  293. goto put_reg;
  294. }
  295. if (IS_ERR(dvdd_cpu_reg) || IS_ERR(dvddm_cpu_reg)) {
  296. dev_err(cpu_dev, "failed to get regulators\n");
  297. ret = -ENOENT;
  298. goto put_reg;
  299. }
  300. ret = dev_pm_opp_of_add_table(cpu_dev);
  301. if (ret < 0) {
  302. dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
  303. goto put_reg;
  304. }
  305. num = dev_pm_opp_get_opp_count(cpu_dev);
  306. if (num < 0) {
  307. ret = num;
  308. dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
  309. goto out_free_opp;
  310. }
  311. ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
  312. if (ret) {
  313. dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
  314. goto out_free_opp;
  315. }
  316. /* Make light_dvddm_volt array's size same as dvdd opp number */
  317. light_dvddm_volt = devm_kcalloc(cpu_dev, num, sizeof(*light_dvddm_volt),
  318. GFP_KERNEL);
  319. if (light_dvddm_volt == NULL) {
  320. ret = -ENOMEM;
  321. goto free_freq_table;
  322. }
  323. if (of_get_property(np, "dvfs_sv", NULL))
  324. light_dvfs_sv = true;
  325. else
  326. light_dvfs_sv = false;
  327. prop = of_find_property(np, "light,dvddm-operating-points", NULL);
  328. if (!prop || !prop->value)
  329. goto soc_opp_out;
  330. nr = prop->length / sizeof(u32);
  331. if (nr % 2 || (nr / 2) < num)
  332. goto soc_opp_out;
  333. for (j = 0; j < num; j++) {
  334. val = prop->value;
  335. for (i = 0; i < nr / 2; i++) {
  336. unsigned long freq = be32_to_cpup(val++);
  337. unsigned long volt = be32_to_cpup(val++);
  338. if (freq_table[j].frequency == freq) {
  339. light_dvddm_volt[soc_opp_count++] = volt;
  340. break;
  341. }
  342. }
  343. }
  344. soc_opp_out:
  345. if (soc_opp_count != num)
  346. dev_warn(cpu_dev, "Not find valid light,dvddm-operating-points property\n");
  347. if (of_property_read_u32(np, "clock-latency", &transition_latency))
  348. transition_latency = CPUFREQ_ETERNAL;
  349. max_freq = freq_table[--num].frequency;
  350. ret = cpufreq_register_driver(&light_cpufreq_driver);
  351. if (ret) {
  352. dev_err(cpu_dev, "failed register driver: %d\n", ret);
  353. goto free_freq_table;
  354. }
  355. register_pm_notifier(&light_cpufreq_pm_notifier);
  356. of_node_put(np);
  357. ret = atomic_notifier_chain_register(&panic_notifier_list,
  358. &panic_cpufreq_notifier);
  359. if (ret) {
  360. pr_err("unable to register notifier(%d)\n", ret);
  361. goto free_freq_table;
  362. }
  363. register_reboot_notifier(&cpufreq_reboot_notifier);
  364. dev_info(cpu_dev, "finish to register cpufreq driver\n");
  365. return 0;
  366. free_freq_table:
  367. dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
  368. out_free_opp:
  369. dev_pm_opp_of_remove_table(cpu_dev);
  370. put_reg:
  371. if (!IS_ERR(dvdd_cpu_reg))
  372. regulator_put(dvdd_cpu_reg);
  373. if (!IS_ERR(dvddm_cpu_reg))
  374. regulator_put(dvddm_cpu_reg);
  375. clk_bulk_put(num_clks, clks);
  376. put_node:
  377. of_node_put(np);
  378. return ret;
  379. }
  380. static int light_cpufreq_remove(struct platform_device *pdev)
  381. {
  382. cpufreq_unregister_driver(&light_cpufreq_driver);
  383. dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
  384. dev_pm_opp_of_remove_table(cpu_dev);
  385. regulator_put(dvdd_cpu_reg);
  386. regulator_put(dvddm_cpu_reg);
  387. clk_bulk_put(num_clks, clks);
  388. return 0;
  389. }
  390. static const struct of_device_id light_cpufreq_match[] = {
  391. { .compatible = "thead,light-mpw-cpufreq" },
  392. {},
  393. };
  394. static struct platform_driver light_cpufreq_platdrv = {
  395. .driver = {
  396. .name = "thead,light-mpw-cpufreq",
  397. .of_match_table = light_cpufreq_match,
  398. },
  399. .probe = light_cpufreq_probe,
  400. .remove = light_cpufreq_remove,
  401. };
  402. module_platform_driver(light_cpufreq_platdrv);
  403. MODULE_ALIAS("platform:light-cpufreq");
  404. MODULE_AUTHOR("fugang.duan <duanfugang.dfg@linux.alibaba.com>");
  405. MODULE_DESCRIPTION("Thead Light cpufreq driver");
  406. MODULE_LICENSE("GPL v2");