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@@ -0,0 +1,573 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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+/*
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+ * Copyright (C) 2017-2018, Intel Corporation
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+ */
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+
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+#ifndef __INTEL_SMC_H
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+#define __INTEL_SMC_H
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+
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+#include <linux/arm-smccc.h>
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+#include <linux/bitops.h>
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+
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+/*
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+ * This file defines the Secure Monitor Call (SMC) message protocol used for
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+ * service layer driver in normal world (EL1) to communicate with secure
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+ * monitor software in Secure Monitor Exception Level 3 (EL3).
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+ *
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+ * This file is shared with secure firmware (FW) which is out of u-boot tree.
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+ *
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+ * An ARM SMC instruction takes a function identifier and up to 6 64-bit
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+ * register values as arguments, and can return up to 4 64-bit register
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+ * values. The operation of the secure monitor is determined by the parameter
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+ * values passed in through registers.
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+
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+ * EL1 and EL3 communicates pointer as physical address rather than the
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+ * virtual address.
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+ */
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+
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+/*
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+ * Functions specified by ARM SMC Calling convention:
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+ *
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+ * FAST call executes atomic operations, returns when the requested operation
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+ * has completed.
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+ * STD call starts a operation which can be preempted by a non-secure
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+ * interrupt. The call can return before the requested operation has
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+ * completed.
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+ *
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+ * a0..a7 is used as register names in the descriptions below, on arm32
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+ * that translates to r0..r7 and on arm64 to w0..w7.
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+ */
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+
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+#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \
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+ ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \
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+ ARM_SMCCC_OWNER_SIP, (func_num))
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+
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+#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \
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+ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \
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+ ARM_SMCCC_OWNER_SIP, (func_num))
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+
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+/*
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+ * Return values in INTEL_SIP_SMC_* call
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+ *
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+ * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION:
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+ * Secure monitor software doesn't recognize the request.
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+ *
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+ * INTEL_SIP_SMC_STATUS_OK:
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+ * SMC call completed successfully,
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+ * In case of FPGA configuration write operation, it means secure monitor
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+ * software can accept the next chunk of FPGA configuration data.
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+ *
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+ * INTEL_SIP_SMC_STATUS_BUSY:
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+ * In case of FPGA configuration write operation, it means secure monitor
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+ * software is still processing previous data & can't accept the next chunk
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+ * of data. Service driver needs to issue
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+ * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the
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+ * completed block(s).
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+ *
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+ * INTEL_SIP_SMC_STATUS_ERROR:
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+ * There is error during the SMC call process.
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+ *
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+ * INTEL_SIP_SMC_REG_ERROR:
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+ * There is error during a read or write operation of the protected
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+ * registers.
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+ */
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+#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF
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+#define INTEL_SIP_SMC_STATUS_OK 0x0
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+#define INTEL_SIP_SMC_STATUS_BUSY 0x1
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+#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
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+#define INTEL_SIP_SMC_STATUS_ERROR 0x4
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+#define INTEL_SIP_SMC_REG_ERROR 0x5
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+#define INTEL_SIP_SMC_RSU_ERROR 0x7
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+
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+/*
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+ * Request INTEL_SIP_SMC_FPGA_CONFIG_START
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+ *
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+ * Sync call used by service driver at EL1 to request the FPGA in EL3 to
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+ * be prepare to receive a new configuration.
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+ *
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+ * Call register usage:
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+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_START.
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+ * a1: flag for full or partial configuration
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+ * 0 full reconfiguration.
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+ * 1 partial reconfiguration.
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+ * a2-7: not used.
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+ *
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+ * Return status:
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+ * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR.
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+ * a1-3: not used.
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+ */
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+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1
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+#define INTEL_SIP_SMC_FPGA_CONFIG_START \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START)
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+
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+/*
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+ * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE
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+ *
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+ * Async call used by service driver at EL1 to provide FPGA configuration data
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+ * to secure world.
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+ *
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+ * Call register usage:
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+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE.
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+ * a1: 64bit physical address of the configuration data memory block
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+ * a2: Size of configuration data block.
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+ * a3-7: not used.
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+ *
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+ * Return status:
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+ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY,
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+ * INTEL_SIP_SMC_STATUS_REJECTED or INTEL_SIP_SMC_STATUS_ERROR.
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+ * a1: 64bit physical address of 1st completed memory block if any completed
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+ * block, otherwise zero value.
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+ * a2: 64bit physical address of 2nd completed memory block if any completed
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+ * block, otherwise zero value.
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+ * a3: 64bit physical address of 3rd completed memory block if any completed
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+ * block, otherwise zero value.
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+ */
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+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE 2
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+#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE \
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+ INTEL_SIP_SMC_STD_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE)
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+
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+/*
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+ * Request INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE
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+ *
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+ * Sync call used by service driver at EL1 to track the completed write
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+ * transactions. This request is called after INTEL_SIP_SMC_FPGA_CONFIG_WRITE
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+ * call returns INTEL_SIP_SMC_STATUS_BUSY.
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+ *
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+ * Call register usage:
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+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE.
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+ * a1-7: not used.
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+ *
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+ * Return status:
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+ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or
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+ * INTEL_SIP_SMC_STATUS_ERROR.
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+ * a1: 64bit physical address of 1st completed memory block.
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+ * a2: 64bit physical address of 2nd completed memory block if
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+ * any completed block, otherwise zero value.
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+ * a3: 64bit physical address of 3rd completed memory block if
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+ * any completed block, otherwise zero value.
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+ */
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+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE 3
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+#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE \
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+INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
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+
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+/*
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+ * Request INTEL_SIP_SMC_FPGA_CONFIG_ISDONE
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+ *
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+ * Sync call used by service driver at EL1 to inform secure world that all
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+ * data are sent, to check whether or not the secure world had completed
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+ * the FPGA configuration process.
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+ *
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+ * Call register usage:
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+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_ISDONE.
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+ * a1-7: not used.
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+ *
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+ * Return status:
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+ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or
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+ * INTEL_SIP_SMC_STATUS_ERROR.
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+ * a1-3: not used.
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+ */
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+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4
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+#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE)
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+
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+/*
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+ * Request INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM
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+ *
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+ * Sync call used by service driver at EL1 to query the physical address of
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+ * memory block reserved by secure monitor software.
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+ *
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+ * Call register usage:
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+ * a0:INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM.
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+ * a1-7: not used.
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+ *
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+ * Return status:
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+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
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+ * a1: start of physical address of reserved memory block.
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+ * a2: size of reserved memory block.
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+ * a3: not used.
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+ */
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+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM 5
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+#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM)
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+
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+/*
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+ * Request INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK
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+ *
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+ * For SMC loop-back mode only, used for internal integration, debugging
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+ * or troubleshooting.
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+ *
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+ * Call register usage:
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+ * a0: INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK.
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+ * a1-7: not used.
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+ *
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+ * Return status:
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+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
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+ * a1-3: not used.
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+ */
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+#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK 6
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+#define INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK)
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+
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+/*
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+ * Request INTEL_SIP_SMC_REG_READ
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+ *
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+ * Read a protected register using SMCCC
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+ *
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+ * Call register usage:
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+ * a0: INTEL_SIP_SMC_REG_READ.
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+ * a1: register address.
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+ * a2-7: not used.
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+ *
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+ * Return status:
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+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
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+ * a1: Value in the register
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+ * a2-3: not used.
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+ */
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+#define INTEL_SIP_SMC_FUNCID_REG_READ 7
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+#define INTEL_SIP_SMC_REG_READ \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ)
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+
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+/*
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+ * Request INTEL_SIP_SMC_REG_WRITE
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+ *
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+ * Write a protected register using SMCCC
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+ *
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+ * Call register usage:
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+ * a0: INTEL_SIP_SMC_REG_WRITE.
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+ * a1: register address
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+ * a2: value to program into register.
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+ * a3-7: not used.
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+ *
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+ * Return status:
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+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
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+ * a1-3: not used.
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+ */
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+#define INTEL_SIP_SMC_FUNCID_REG_WRITE 8
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+#define INTEL_SIP_SMC_REG_WRITE \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE)
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+
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+/*
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+ * Request INTEL_SIP_SMC_FUNCID_REG_UPDATE
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+ *
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+ * Update one or more bits in a protected register using a
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+ * read-modify-write operation.
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+ *
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+ * Call register usage:
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+ * a0: INTEL_SIP_SMC_REG_UPDATE.
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+ * a1: register address
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+ * a2: Write Mask.
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+ * a3: Value to write.
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+ * a4-7: not used.
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+ *
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+ * Return status:
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+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
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+ * a1-3: Not used.
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+ */
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+#define INTEL_SIP_SMC_FUNCID_REG_UPDATE 9
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+#define INTEL_SIP_SMC_REG_UPDATE \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_UPDATE)
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+
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+/*
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+* Request INTEL_SIP_SMC_RSU_STATUS
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+*
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+* Sync call used by service driver at EL1 to query the RSU status
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+*
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+* Call register usage:
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+* a0 INTEL_SIP_SMC_RSU_STATUS
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+* a1-7 not used
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+*
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+* Return status
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+* a0: Current Image
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+* a1: Last Failing Image
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+* a2: Version [width 32 bit] | State [width 32 bit]
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+* a3: Error details [width 32 bit] | Error location [width 32 bit]
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+*
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+* Or
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+*
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+* a0: INTEL_SIP_SMC_RSU_ERROR
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+*/
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+#define INTEL_SIP_SMC_FUNCID_RSU_STATUS 11
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+#define INTEL_SIP_SMC_RSU_STATUS \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_STATUS)
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+
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+/*
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+* Request INTEL_SIP_SMC_RSU_UPDATE
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+*
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+* Sync call used by service driver at EL1 to tell you next reboot is RSU_UPDATE
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+*
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+* Call register usage:
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+* a0 INTEL_SIP_SMC_RSU_UPDATE
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+* a1 64bit physical address of the configuration data memory in flash
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+* a2-7 not used
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+*
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+* Return status
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+ * a0 INTEL_SIP_SMC_STATUS_OK
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+*/
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+#define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12
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+#define INTEL_SIP_SMC_RSU_UPDATE \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE)
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+
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+/*
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+ * Request INTEL_SIP_SMC_ECC_DBE
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+ *
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+ * Sync call used by service driver at EL1 alert EL3 that a Double Bit
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+ * ECC error has occurred.
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+ *
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+ * Call register usage:
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+ * a0 INTEL_SIP_SMC_ECC_DBE
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+ * a1 SysManager Double Bit Error value
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+ * a2-7 not used
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+ *
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+ * Return status
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+ * a0 INTEL_SIP_SMC_STATUS_OK
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+ */
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+#define INTEL_SIP_SMC_FUNCID_ECC_DBE 13
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+#define INTEL_SIP_SMC_ECC_DBE \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_ECC_DBE)
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+
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+/*
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+* Request INTEL_SIP_SMC_RSU_NOTIFY
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+*
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+* Sync call used by service driver at EL1 to report HPS software execution stage
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+*
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+* Call register usage:
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+* a0 INTEL_SIP_SMC_RSU_NOTIFY
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+* a1 32bit HPS software execution stage
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+* a2-7 not used
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+*
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+* Return status
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+ * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
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+*/
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+#define INTEL_SIP_SMC_FUNCID_RSU_NOTIFY 14
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+#define INTEL_SIP_SMC_RSU_NOTIFY \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_NOTIFY)
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+
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+/*
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+ * Request INTEL_SIP_SMC_RSU_RETRY_COUNTER
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+ *
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+ * Sync call used by service driver at EL1 to query the RSU retry counter
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+ *
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+ * Call register usage:
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+ * a0 INTEL_SIP_SMC_RSU_RETRY_COUNTER
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+ * a1-7 not used
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+ *
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+ * Return status
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+ * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_RSU_ERROR.
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+ * a1 retry counter
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+*/
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+#define INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER 15
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+#define INTEL_SIP_SMC_RSU_RETRY_COUNTER \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER)
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+
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+/*
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+ * Request INTEL_SIP_SMC_RSU_DCMF_VERSION
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+ *
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+ * Sync call used by service driver at EL1 to query DCMF version
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+ *
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+ * Call register usage:
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+ * a0 INTEL_SIP_SMC_RSU_DCMF_VERSION
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+ * a1-7 not used
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+ *
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+ * Return status
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+ * a0 INTEL_SIP_SMC_STATUS_OK
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+ * a1 dcmf1 version | dcmf0 version
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+ * a2 dcmf3 version | dcmf2 version
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+ *
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+ * Or
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+ *
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+ * a0 INTEL_SIP_SMC_RSU_ERROR
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+ */
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+#define INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION 16
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+#define INTEL_SIP_SMC_RSU_DCMF_VERSION \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION)
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+
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+/*
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+ * Request INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION
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+ *
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+ * Sync call used by SSBL (EL2) to copy DCMF version to ATF memory
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+ *
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+ * Call register usage:
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+ * a0 INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION
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+ * a1 dcmf1 version | dcmf0 version
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+ * a2 dcmf3 version | dcmf2 version
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+ *
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+ * Return status
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+ * a0 INTEL_SIP_SMC_STATUS_OK
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+ */
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+#define INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_VERSION 17
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+#define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_VERSION)
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+
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+/*
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+ * Request INTEL_SIP_SMC_RSU_MAX_RETRY
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+ *
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+ * Sync call used by service driver at EL1 to query max_retry parameter
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+ *
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+ * Call register usage:
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+ * a0 INTEL_SIP_SMC_RSU_MAX_RETRY
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+ * a1-7 not used
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+ *
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+ * Return status
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+ * a0 INTEL_SIP_SMC_STATUS_OK
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+ * a1 max_retry
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+ *
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+ * Or
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+ *
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+ * a0 INTEL_SIP_SMC_RSU_ERROR
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+ */
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+#define INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY 18
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+#define INTEL_SIP_SMC_RSU_MAX_RETRY \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY)
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+
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+/*
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+ * Request INTEL_SIP_SMC_RSU_COPY_MAX_RETRY
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+ *
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+ * Sync call used by SSBL (EL2) to copy RSU 'max retry' to ATF memory
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+ *
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+ * Call register usage:
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+ * a0 INTEL_SIP_SMC_RSU_COPY_MAX_RETRY
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+ * a1 max retry
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+ * a2-7 not used
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+ *
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+ * Return status
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+ * a0 INTEL_SIP_SMC_STATUS_OK
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+ */
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+#define INTEL_SIP_SMC_FUNCID_RSU_COPY_MAX_RETRY 19
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+#define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_MAX_RETRY)
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+
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+/*
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+ * Request INTEL_SIP_SMC_RSU_DCMF_STATUS
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+ *
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+ * Sync call used by service driver at EL1 to query DCMF status
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+ *
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+ * Call register usage:
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+ * a0 INTEL_SIP_SMC_RSU_DCMF_STATUS
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+ * a1-7 not used
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+ *
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+ * Return status
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+ * a0 INTEL_SIP_SMC_STATUS_OK
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+ * a1 dcmf3 status | dcmf2 status | dcmf1 status | dcmf0 status
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+ *
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+ * Or
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+ *
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+ * a0 INTEL_SIP_SMC_RSU_ERROR
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+ */
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+#define INTEL_SIP_SMC_FUNCID_RSU_DCMF_STATUS 20
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+#define INTEL_SIP_SMC_RSU_DCMF_STATUS \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_STATUS)
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+
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+/*
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+ * Request INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS
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+ *
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+ * Sync call used by SSBL (EL2) to copy RSU 'dcmf status' to ATF memory
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+ *
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+ * Call register usage:
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+ * a0 INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS
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+ * a1 dcmf status
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+ * a2-7 not used
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+ *
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+ * Return status
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+ * a0 INTEL_SIP_SMC_STATUS_OK
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+ */
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+#define INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_STATUS 21
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+#define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_STATUS)
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+
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+/*
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+ * Request INTEL_SIP_SMC_HPS_SET_BRIDGES
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+ *
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+ * Enable/disable the SoC FPGA bridges
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+ *
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+ * Call register usage:
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+ * a0 INTEL_SIP_SMC_HPS_SET_BRIDGES
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+ * a1 Set bridges status:
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+ * 0 - Disable
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+ * 1 - Enable
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+ * a2-7 not used
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+ *
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+ * Return status
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+ * a0 INTEL_SIP_SMC_STATUS_OK
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+ */
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+#define INTEL_SIP_SMC_FUNCID_HPS_SET_BRIDGES 50
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+#define INTEL_SIP_SMC_HPS_SET_BRIDGES \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_BRIDGES)
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+
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+/*
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+ * Request INTEL_SIP_SMC_MBOX_SEND_CMD
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+ *
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+ * Send mailbox command to SDM
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+ *
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+ * Call register usage:
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+ * a0 INTEL_SIP_SMC_MBOX_SEND_CMD
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+ * a1 Mailbox command
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+ * a2 64bit physical address pointer to command's arguments
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+ * a3 Length of the argument
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+ * a4 Urgent command:
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+ * 0 - Disable
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+ * 1 - Enable
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+ * a5 64bit physical address pointer to a buffer for receiving responses
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+ * a6 Length of the buffer
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+ *
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+ * Return status
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+ * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR
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+ * a1 Status of mailbox response
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+ * a2 Received length in the buffer
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+ */
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+#define INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD 60
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+#define INTEL_SIP_SMC_MBOX_SEND_CMD \
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD)
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+
|
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+/*
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+ * Request INTEL_SIP_SMC_HPS_SET_PHYINTF
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+ *
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+ * Select EMACx PHY interface
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+ *
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+ * Call register usage:
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+ * a0 INTEL_SIP_SMC_HPS_SET_PHYINTF
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+ * a1 EMAC number:
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+ * 0 - EMAC0
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+ * 1 - EMAC1
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+ * 2 - EMAC2
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+ * a2 Type of PHY interface:
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+ * 0 - GMII_MII
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+ * 1 - RGMII
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+ * 2 - RMII
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+ * 3 - RESET
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+ * a3-7 not used
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+ *
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+ * Return status
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+ * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR
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|
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+ */
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+#define INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF 61
|
|
|
+#define INTEL_SIP_SMC_HPS_SET_PHYINTF \
|
|
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+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF)
|
|
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+
|
|
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+/*
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|
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+ * Request INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK
|
|
|
+ *
|
|
|
+ * Select which phase shift of the clocks (drvsel & smplsel) for SDMMC
|
|
|
+ *
|
|
|
+ * Call register usage:
|
|
|
+ * a0 INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK
|
|
|
+ * a1 Select which phase shift of the clock for cclk_in_drv (drvsel):
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|
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+ * 0 - 0 degree
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+ * 1 - 45 degrees
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+ * 2 - 90 degrees
|
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+ * 3 - 135 degrees
|
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+ * 4 - 180 degrees
|
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+ * 5 - 225 degrees
|
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|
+ * 6 - 270 degrees
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+ * 7 - 315 degrees
|
|
|
+ * a2 Select which phase shift of the clock for cclk_in_sample (smplsel):
|
|
|
+ * (Same as above)
|
|
|
+ * a3-7 not used
|
|
|
+ *
|
|
|
+ * Return status
|
|
|
+ * a0 INTEL_SIP_SMC_STATUS_OK
|
|
|
+ */
|
|
|
+#define INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK 62
|
|
|
+#define INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK \
|
|
|
+ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK)
|
|
|
+
|
|
|
+#endif
|