reset_manager_s10.c 3.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #include <common.h>
  7. #include <hang.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/reset_manager.h>
  10. #include <asm/arch/smc_api.h>
  11. #include <asm/arch/system_manager.h>
  12. #include <dt-bindings/reset/altr,rst-mgr-s10.h>
  13. #include <linux/iopoll.h>
  14. #include <linux/intel-smc.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. /* Assert or de-assert SoCFPGA reset manager reset. */
  17. void socfpga_per_reset(u32 reset, int set)
  18. {
  19. unsigned long reg;
  20. if (RSTMGR_BANK(reset) == 0)
  21. reg = RSTMGR_SOC64_MPUMODRST;
  22. else if (RSTMGR_BANK(reset) == 1)
  23. reg = RSTMGR_SOC64_PER0MODRST;
  24. else if (RSTMGR_BANK(reset) == 2)
  25. reg = RSTMGR_SOC64_PER1MODRST;
  26. else if (RSTMGR_BANK(reset) == 3)
  27. reg = RSTMGR_SOC64_BRGMODRST;
  28. else /* Invalid reset register, do nothing */
  29. return;
  30. if (set)
  31. setbits_le32(socfpga_get_rstmgr_addr() + reg,
  32. 1 << RSTMGR_RESET(reset));
  33. else
  34. clrbits_le32(socfpga_get_rstmgr_addr() + reg,
  35. 1 << RSTMGR_RESET(reset));
  36. }
  37. /*
  38. * Assert reset on every peripheral but L4WD0.
  39. * Watchdog must be kept intact to prevent glitches
  40. * and/or hangs.
  41. */
  42. void socfpga_per_reset_all(void)
  43. {
  44. const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
  45. /* disable all except OCP and l4wd0. OCP disable later */
  46. writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
  47. socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
  48. writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
  49. writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST);
  50. }
  51. void socfpga_bridges_reset(int enable)
  52. {
  53. #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
  54. u64 arg = enable;
  55. int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0);
  56. if (ret) {
  57. printf("SMC call failed with error %d in %s.\n", ret, __func__);
  58. return;
  59. }
  60. #else
  61. u32 reg;
  62. if (enable) {
  63. /* clear idle request to all bridges */
  64. setbits_le32(socfpga_get_sysmgr_addr() +
  65. SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0);
  66. /* Release all bridges from reset state */
  67. clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
  68. ~0);
  69. /* Poll until all idleack to 0 */
  70. read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
  71. SYSMGR_SOC64_NOC_IDLEACK, reg, !reg, 1000,
  72. 300000);
  73. } else {
  74. /* set idle request to all bridges */
  75. writel(~0,
  76. socfpga_get_sysmgr_addr() +
  77. SYSMGR_SOC64_NOC_IDLEREQ_SET);
  78. /* Enable the NOC timeout */
  79. writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
  80. /* Poll until all idleack to 1 */
  81. read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
  82. SYSMGR_SOC64_NOC_IDLEACK, reg,
  83. reg == (SYSMGR_NOC_H2F_MSK |
  84. SYSMGR_NOC_LWH2F_MSK),
  85. 1000, 300000);
  86. /* Poll until all idlestatus to 1 */
  87. read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
  88. SYSMGR_SOC64_NOC_IDLESTATUS, reg,
  89. reg == (SYSMGR_NOC_H2F_MSK |
  90. SYSMGR_NOC_LWH2F_MSK),
  91. 1000, 300000);
  92. /* Reset all bridges (except NOR DDR scheduler & F2S) */
  93. setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
  94. ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
  95. RSTMGR_BRGMODRST_FPGA2SOC_MASK));
  96. /* Disable NOC timeout */
  97. writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
  98. }
  99. #endif
  100. }
  101. /*
  102. * Return non-zero if the CPU has been warm reset
  103. */
  104. int cpu_has_been_warmreset(void)
  105. {
  106. return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) &
  107. RSTMGR_L4WD_MPU_WARMRESET_MASK;
  108. }
  109. void print_reset_info(void)
  110. {
  111. bool iswd;
  112. int n;
  113. u32 stat = cpu_has_been_warmreset();
  114. printf("Reset state: %s%s", stat ? "Warm " : "Cold",
  115. (stat & RSTMGR_STAT_SDMWARMRST) ? "[from SDM] " : "");
  116. stat &= ~RSTMGR_STAT_SDMWARMRST;
  117. if (!stat) {
  118. puts("\n");
  119. return;
  120. }
  121. n = generic_ffs(stat) - 1;
  122. iswd = (n >= RSTMGR_STAT_L4WD0RST_BITPOS);
  123. printf("(Triggered by %s %d)\n", iswd ? "Watchdog" : "MPU",
  124. iswd ? (n - RSTMGR_STAT_L4WD0RST_BITPOS) :
  125. (n - RSTMGR_STAT_MPU0RST_BITPOS));
  126. }