socfpga_soc64_common.h 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220
  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
  7. #define __CONFIG_SOCFPGA_SOC64_COMMON_H__
  8. #include <asm/arch/base_addr_s10.h>
  9. #include <asm/arch/handoff_s10.h>
  10. #include <linux/stringify.h>
  11. /*
  12. * U-Boot general configurations
  13. */
  14. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  15. #define CONFIG_LOADADDR 0x2000000
  16. #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  17. #define CONFIG_REMAKE_ELF
  18. /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
  19. #define CPU_RELEASE_ADDR 0xFFD12210
  20. #define CONFIG_SYS_CACHELINE_SIZE 64
  21. #define CONFIG_SYS_MEM_RESERVE_SECURE 0 /* using OCRAM, not DDR */
  22. /*
  23. * U-Boot console configurations
  24. */
  25. #define CONFIG_SYS_MAXARGS 64
  26. #define CONFIG_SYS_CBSIZE 2048
  27. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  28. sizeof(CONFIG_SYS_PROMPT) + 16)
  29. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  30. /* Extend size of kernel image for uncompression */
  31. #define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
  32. /*
  33. * U-Boot run time memory configurations
  34. */
  35. #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
  36. #define CONFIG_SYS_INIT_RAM_SIZE 0x40000
  37. #ifdef CONFIG_SPL_BUILD
  38. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \
  39. + CONFIG_SYS_INIT_RAM_SIZE \
  40. - S10_HANDOFF_SIZE)
  41. #else
  42. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE \
  43. + 0x100000)
  44. #endif
  45. #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR)
  46. #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
  47. /*
  48. * U-Boot environment configurations
  49. */
  50. /*
  51. * QSPI support
  52. */
  53. #ifdef CONFIG_CADENCE_QSPI
  54. /* Enable it if you want to use dual-stacked mode */
  55. /*#define CONFIG_QSPI_RBF_ADDR 0x720000*/
  56. /* Flash device info */
  57. /*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
  58. #ifndef CONFIG_SPL_BUILD
  59. #define CONFIG_MTD_PARTITIONS
  60. #define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
  61. #endif /* CONFIG_SPL_BUILD */
  62. #ifndef __ASSEMBLY__
  63. unsigned int cm_get_qspi_controller_clk_hz(void);
  64. #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
  65. #endif
  66. #endif /* CONFIG_CADENCE_QSPI */
  67. /*
  68. * Boot arguments passed to the boot command. The value of
  69. * CONFIG_BOOTARGS goes into the environment value "bootargs".
  70. * Do note the value will override also the chosen node in FDT blob.
  71. */
  72. #ifdef CONFIG_FIT
  73. #define CONFIG_BOOTFILE "kernel.itb"
  74. #define CONFIG_BOOTCOMMAND "run fatscript; run mmcfitload;run linux_qspi_enable;" \
  75. "run mmcfitboot"
  76. #else
  77. #define CONFIG_BOOTFILE "Image"
  78. #define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \
  79. "run mmcboot"
  80. #endif
  81. #define CONFIG_EXTRA_ENV_SETTINGS \
  82. "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  83. "bootfile=" CONFIG_BOOTFILE "\0" \
  84. "fdt_addr=8000000\0" \
  85. "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
  86. "mmcroot=/dev/mmcblk0p2\0" \
  87. "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  88. " root=${mmcroot} rw rootwait;" \
  89. "booti ${loadaddr} - ${fdt_addr}\0" \
  90. "mmcload=mmc rescan;" \
  91. "load mmc 0:1 ${loadaddr} ${bootfile};" \
  92. "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  93. "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
  94. " root=${mmcroot} rw rootwait;" \
  95. "bootm ${loadaddr}\0" \
  96. "mmcfitload=mmc rescan;" \
  97. "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
  98. "linux_qspi_enable=if sf probe; then " \
  99. "echo Enabling QSPI at Linux DTB...;" \
  100. "fdt addr ${fdt_addr}; fdt resize;" \
  101. "fdt set /soc/spi@ff8d2000 status okay;" \
  102. "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
  103. " ${qspi_clock}; fi; \0" \
  104. "scriptaddr=0x02100000\0" \
  105. "scriptfile=u-boot.scr\0" \
  106. "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
  107. "then source ${scriptaddr}; fi\0" \
  108. "socfpga_legacy_reset_compat=1\0"
  109. /*
  110. * Generic Interrupt Controller Definitions
  111. */
  112. #define CONFIG_GICV2
  113. /*
  114. * External memory configurations
  115. */
  116. #define PHYS_SDRAM_1 0x0
  117. #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024)
  118. #define CONFIG_SYS_SDRAM_BASE 0
  119. /*
  120. * Serial / UART configurations
  121. */
  122. #define CONFIG_SYS_NS16550_CLK 100000000
  123. #define CONFIG_SYS_NS16550_MEM32
  124. /*
  125. * Timer & watchdog configurations
  126. */
  127. #define COUNTER_FREQUENCY 400000000
  128. /*
  129. * SDMMC configurations
  130. */
  131. #ifdef CONFIG_CMD_MMC
  132. #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
  133. #endif
  134. /*
  135. * Flash configurations
  136. */
  137. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  138. /* Ethernet on SoC (EMAC) */
  139. #if defined(CONFIG_CMD_NET)
  140. #define CONFIG_DW_ALTDESCRIPTOR
  141. #endif /* CONFIG_CMD_NET */
  142. /*
  143. * L4 Watchdog
  144. */
  145. #ifndef CONFIG_SPL_BUILD
  146. #undef CONFIG_HW_WATCHDOG
  147. #undef CONFIG_DESIGNWARE_WATCHDOG
  148. #endif
  149. #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
  150. #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
  151. #ifndef __ASSEMBLY__
  152. unsigned int cm_get_l4_sys_free_clk_hz(void);
  153. #define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000)
  154. #endif
  155. #else
  156. #define CONFIG_DW_WDT_CLOCK_KHZ 100000
  157. #endif
  158. /*
  159. * SPL memory layout
  160. *
  161. * On chip RAM
  162. * 0xFFE0_0000 ...... Start of OCRAM
  163. * SPL code, rwdata
  164. * empty space
  165. * 0xFFEx_xxxx ...... Top of stack (grows down)
  166. * 0xFFEy_yyyy ...... Global Data
  167. * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
  168. * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
  169. * 0xFFE3_FFFF ...... End of OCRAM
  170. *
  171. * SDRAM
  172. * 0x0000_0000 ...... Start of SDRAM_1
  173. * unused / empty space for image loading
  174. * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
  175. * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
  176. * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
  177. *
  178. */
  179. #define CONFIG_SPL_TARGET "spl/u-boot-spl.hex"
  180. #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
  181. #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
  182. #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
  183. #define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
  184. - CONFIG_SPL_BSS_MAX_SIZE)
  185. #define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN)
  186. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \
  187. - CONFIG_SYS_SPL_MALLOC_SIZE)
  188. /* SPL SDMMC boot support */
  189. #ifdef CONFIG_SPL_LOAD_FIT
  190. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb"
  191. #else
  192. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  193. #endif
  194. #endif /* __CONFIG_SOCFPGA_SOC64_COMMON_H__ */