Kconfig 6.1 KB

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  1. if ARCH_SOCFPGA
  2. config ERR_PTR_OFFSET
  3. default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
  4. config NR_DRAM_BANKS
  5. default 1
  6. config SPL_SIZE_LIMIT
  7. default 0x10000 if TARGET_SOCFPGA_GEN5
  8. config SPL_SIZE_LIMIT_PROVIDE_STACK
  9. default 0x200 if TARGET_SOCFPGA_GEN5
  10. config SPL_STACK_R_ADDR
  11. default 0x00800000 if TARGET_SOCFPGA_GEN5
  12. config SPL_SYS_MALLOC_F_LEN
  13. default 0x800 if TARGET_SOCFPGA_GEN5
  14. config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
  15. default 0xa2
  16. config SYS_MALLOC_F_LEN
  17. default 0x2000 if TARGET_SOCFPGA_ARRIA10
  18. default 0x2000 if TARGET_SOCFPGA_GEN5
  19. config SYS_TEXT_BASE
  20. default 0x01000040 if TARGET_SOCFPGA_ARRIA10
  21. default 0x01000040 if TARGET_SOCFPGA_GEN5
  22. config TARGET_SOCFPGA_AGILEX
  23. bool
  24. select ARMV8_MULTIENTRY
  25. select ARMV8_SET_SMPEN
  26. select BINMAN if SPL_ATF
  27. select CLK
  28. select FPGA_INTEL_SDM_MAILBOX
  29. select NCORE_CACHE
  30. select SPL_CLK if SPL
  31. config TARGET_SOCFPGA_ARRIA5
  32. bool
  33. select TARGET_SOCFPGA_GEN5
  34. config TARGET_SOCFPGA_ARRIA10
  35. bool
  36. select SPL_ALTERA_SDRAM
  37. select SPL_BOARD_INIT if SPL
  38. select SPL_CACHE if SPL
  39. select CLK
  40. select SPL_CLK if SPL
  41. select DM_I2C
  42. select DM_RESET
  43. select SPL_DM_RESET if SPL
  44. select REGMAP
  45. select SPL_REGMAP if SPL
  46. select SYSCON
  47. select SPL_SYSCON if SPL
  48. select ETH_DESIGNWARE_SOCFPGA
  49. imply FPGA_SOCFPGA
  50. imply SPL_USE_TINY_PRINTF
  51. config TARGET_SOCFPGA_CYCLONE5
  52. bool
  53. select TARGET_SOCFPGA_GEN5
  54. config TARGET_SOCFPGA_GEN5
  55. bool
  56. select SPL_ALTERA_SDRAM
  57. imply FPGA_SOCFPGA
  58. imply SPL_SIZE_LIMIT_SUBTRACT_GD
  59. imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
  60. imply SPL_STACK_R
  61. imply SPL_SYS_MALLOC_SIMPLE
  62. imply SPL_USE_TINY_PRINTF
  63. config TARGET_SOCFPGA_STRATIX10
  64. bool
  65. select ARMV8_MULTIENTRY
  66. select ARMV8_SET_SMPEN
  67. select BINMAN if SPL_ATF
  68. select FPGA_INTEL_SDM_MAILBOX
  69. choice
  70. prompt "Altera SOCFPGA board select"
  71. optional
  72. config TARGET_SOCFPGA_AGILEX_SOCDK
  73. bool "Intel SOCFPGA SoCDK (Agilex)"
  74. select TARGET_SOCFPGA_AGILEX
  75. config TARGET_SOCFPGA_ARIES_MCVEVK
  76. bool "Aries MCVEVK (Cyclone V)"
  77. select TARGET_SOCFPGA_CYCLONE5
  78. config TARGET_SOCFPGA_ARRIA10_SOCDK
  79. bool "Altera SOCFPGA SoCDK (Arria 10)"
  80. select TARGET_SOCFPGA_ARRIA10
  81. config TARGET_SOCFPGA_ARRIA5_SECU1
  82. bool "ABB SECU1 (Arria V)"
  83. select TARGET_SOCFPGA_ARRIA5
  84. select VENDOR_KM
  85. config TARGET_SOCFPGA_ARRIA5_SOCDK
  86. bool "Altera SOCFPGA SoCDK (Arria V)"
  87. select TARGET_SOCFPGA_ARRIA5
  88. config TARGET_SOCFPGA_CYCLONE5_SOCDK
  89. bool "Altera SOCFPGA SoCDK (Cyclone V)"
  90. select TARGET_SOCFPGA_CYCLONE5
  91. config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  92. bool "Devboards DBM-SoC1 (Cyclone V)"
  93. select TARGET_SOCFPGA_CYCLONE5
  94. config TARGET_SOCFPGA_EBV_SOCRATES
  95. bool "EBV SoCrates (Cyclone V)"
  96. select TARGET_SOCFPGA_CYCLONE5
  97. config TARGET_SOCFPGA_IS1
  98. bool "IS1 (Cyclone V)"
  99. select TARGET_SOCFPGA_CYCLONE5
  100. config TARGET_SOCFPGA_SOFTING_VINING_FPGA
  101. bool "Softing VIN|ING FPGA (Cyclone V)"
  102. select BOARD_LATE_INIT
  103. select TARGET_SOCFPGA_CYCLONE5
  104. config TARGET_SOCFPGA_SR1500
  105. bool "SR1500 (Cyclone V)"
  106. select TARGET_SOCFPGA_CYCLONE5
  107. config TARGET_SOCFPGA_STRATIX10_SOCDK
  108. bool "Intel SOCFPGA SoCDK (Stratix 10)"
  109. select TARGET_SOCFPGA_STRATIX10
  110. config TARGET_SOCFPGA_TERASIC_DE0_NANO
  111. bool "Terasic DE0-Nano-Atlas (Cyclone V)"
  112. select TARGET_SOCFPGA_CYCLONE5
  113. config TARGET_SOCFPGA_TERASIC_DE10_NANO
  114. bool "Terasic DE10-Nano (Cyclone V)"
  115. select TARGET_SOCFPGA_CYCLONE5
  116. config TARGET_SOCFPGA_TERASIC_DE1_SOC
  117. bool "Terasic DE1-SoC (Cyclone V)"
  118. select TARGET_SOCFPGA_CYCLONE5
  119. config TARGET_SOCFPGA_TERASIC_SOCKIT
  120. bool "Terasic SoCkit (Cyclone V)"
  121. select TARGET_SOCFPGA_CYCLONE5
  122. endchoice
  123. config SYS_BOARD
  124. default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
  125. default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  126. default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
  127. default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  128. default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  129. default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  130. default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
  131. default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
  132. default "is1" if TARGET_SOCFPGA_IS1
  133. default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
  134. default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
  135. default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
  136. default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
  137. default "sr1500" if TARGET_SOCFPGA_SR1500
  138. default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
  139. default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
  140. config SYS_VENDOR
  141. default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
  142. default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
  143. default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
  144. default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  145. default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
  146. default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
  147. default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  148. default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
  149. default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
  150. default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
  151. default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  152. default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
  153. default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
  154. default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
  155. config SYS_SOC
  156. default "socfpga"
  157. config SYS_CONFIG_NAME
  158. default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
  159. default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
  160. default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  161. default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
  162. default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  163. default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  164. default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  165. default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
  166. default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
  167. default "socfpga_is1" if TARGET_SOCFPGA_IS1
  168. default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
  169. default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
  170. default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
  171. default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
  172. default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
  173. default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
  174. source "board/keymile/Kconfig"
  175. endif