dwmac_socfpga.c 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Marek Vasut <marex@denx.de>
  4. *
  5. * Altera SoCFPGA EMAC extras
  6. */
  7. #include <common.h>
  8. #include <asm/arch/secure_reg_helper.h>
  9. #include <asm/arch/system_manager.h>
  10. #include <asm/io.h>
  11. #include <dm.h>
  12. #include <clk.h>
  13. #include <phy.h>
  14. #include <regmap.h>
  15. #include <reset.h>
  16. #include <syscon.h>
  17. #include "designware.h"
  18. #include <dm/device_compat.h>
  19. #include <linux/err.h>
  20. struct dwmac_socfpga_plat {
  21. struct dw_eth_pdata dw_eth_pdata;
  22. void *phy_intf;
  23. u32 reg_shift;
  24. };
  25. static int dwmac_socfpga_of_to_plat(struct udevice *dev)
  26. {
  27. struct dwmac_socfpga_plat *pdata = dev_get_plat(dev);
  28. struct regmap *regmap;
  29. struct ofnode_phandle_args args;
  30. void *range;
  31. int ret;
  32. ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL,
  33. 2, 0, &args);
  34. if (ret) {
  35. dev_err(dev, "Failed to get syscon: %d\n", ret);
  36. return ret;
  37. }
  38. if (args.args_count != 2) {
  39. dev_err(dev, "Invalid number of syscon args\n");
  40. return -EINVAL;
  41. }
  42. regmap = syscon_node_to_regmap(args.node);
  43. if (IS_ERR(regmap)) {
  44. ret = PTR_ERR(regmap);
  45. dev_err(dev, "Failed to get regmap: %d\n", ret);
  46. return ret;
  47. }
  48. range = regmap_get_range(regmap, 0);
  49. if (!range) {
  50. dev_err(dev, "Failed to get regmap range\n");
  51. return -ENOMEM;
  52. }
  53. pdata->phy_intf = range + args.args[0];
  54. pdata->reg_shift = args.args[1];
  55. return designware_eth_of_to_plat(dev);
  56. }
  57. static int dwmac_socfpga_do_setphy(struct udevice *dev, u32 modereg)
  58. {
  59. struct dwmac_socfpga_plat *pdata = dev_get_plat(dev);
  60. u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
  61. #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
  62. u32 index = ((u64)pdata->phy_intf - socfpga_get_sysmgr_addr() -
  63. SYSMGR_SOC64_EMAC0) >> 2;
  64. u32 id = SOCFPGA_SECURE_REG_SYSMGR_SOC64_EMAC0 + index;
  65. int ret = socfpga_secure_reg_update32(id,
  66. modemask,
  67. modereg << pdata->reg_shift);
  68. if (ret) {
  69. dev_err(dev, "Failed to set PHY register via SMC call\n");
  70. return ret;
  71. }
  72. #else
  73. clrsetbits_le32(pdata->phy_intf, modemask,
  74. modereg << pdata->reg_shift);
  75. #endif
  76. return 0;
  77. }
  78. static int dwmac_socfpga_probe(struct udevice *dev)
  79. {
  80. struct dwmac_socfpga_plat *pdata = dev_get_plat(dev);
  81. struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata;
  82. struct reset_ctl_bulk reset_bulk;
  83. int ret;
  84. u32 modereg;
  85. switch (edata->phy_interface) {
  86. case PHY_INTERFACE_MODE_MII:
  87. case PHY_INTERFACE_MODE_GMII:
  88. modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
  89. break;
  90. case PHY_INTERFACE_MODE_RMII:
  91. modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
  92. break;
  93. case PHY_INTERFACE_MODE_RGMII:
  94. modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
  95. break;
  96. default:
  97. dev_err(dev, "Unsupported PHY mode\n");
  98. return -EINVAL;
  99. }
  100. ret = reset_get_bulk(dev, &reset_bulk);
  101. if (ret) {
  102. dev_err(dev, "Failed to get reset: %d\n", ret);
  103. return ret;
  104. }
  105. reset_assert_bulk(&reset_bulk);
  106. ret = dwmac_socfpga_do_setphy(dev, modereg);
  107. if (ret)
  108. return ret;
  109. reset_release_bulk(&reset_bulk);
  110. return designware_eth_probe(dev);
  111. }
  112. static const struct udevice_id dwmac_socfpga_ids[] = {
  113. { .compatible = "altr,socfpga-stmmac" },
  114. { }
  115. };
  116. U_BOOT_DRIVER(dwmac_socfpga) = {
  117. .name = "dwmac_socfpga",
  118. .id = UCLASS_ETH,
  119. .of_match = dwmac_socfpga_ids,
  120. .of_to_plat = dwmac_socfpga_of_to_plat,
  121. .probe = dwmac_socfpga_probe,
  122. .ops = &designware_eth_ops,
  123. .priv_auto = sizeof(struct dw_eth_dev),
  124. .plat_auto = sizeof(struct dwmac_socfpga_plat),
  125. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  126. };