intel-smc.h 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2017-2018, Intel Corporation
  4. */
  5. #ifndef __INTEL_SMC_H
  6. #define __INTEL_SMC_H
  7. #include <linux/arm-smccc.h>
  8. #include <linux/bitops.h>
  9. /*
  10. * This file defines the Secure Monitor Call (SMC) message protocol used for
  11. * service layer driver in normal world (EL1) to communicate with secure
  12. * monitor software in Secure Monitor Exception Level 3 (EL3).
  13. *
  14. * This file is shared with secure firmware (FW) which is out of u-boot tree.
  15. *
  16. * An ARM SMC instruction takes a function identifier and up to 6 64-bit
  17. * register values as arguments, and can return up to 4 64-bit register
  18. * values. The operation of the secure monitor is determined by the parameter
  19. * values passed in through registers.
  20. * EL1 and EL3 communicates pointer as physical address rather than the
  21. * virtual address.
  22. */
  23. /*
  24. * Functions specified by ARM SMC Calling convention:
  25. *
  26. * FAST call executes atomic operations, returns when the requested operation
  27. * has completed.
  28. * STD call starts a operation which can be preempted by a non-secure
  29. * interrupt. The call can return before the requested operation has
  30. * completed.
  31. *
  32. * a0..a7 is used as register names in the descriptions below, on arm32
  33. * that translates to r0..r7 and on arm64 to w0..w7.
  34. */
  35. #define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \
  36. ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \
  37. ARM_SMCCC_OWNER_SIP, (func_num))
  38. #define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \
  39. ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \
  40. ARM_SMCCC_OWNER_SIP, (func_num))
  41. /*
  42. * Return values in INTEL_SIP_SMC_* call
  43. *
  44. * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION:
  45. * Secure monitor software doesn't recognize the request.
  46. *
  47. * INTEL_SIP_SMC_STATUS_OK:
  48. * SMC call completed successfully,
  49. * In case of FPGA configuration write operation, it means secure monitor
  50. * software can accept the next chunk of FPGA configuration data.
  51. *
  52. * INTEL_SIP_SMC_STATUS_BUSY:
  53. * In case of FPGA configuration write operation, it means secure monitor
  54. * software is still processing previous data & can't accept the next chunk
  55. * of data. Service driver needs to issue
  56. * INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the
  57. * completed block(s).
  58. *
  59. * INTEL_SIP_SMC_STATUS_ERROR:
  60. * There is error during the SMC call process.
  61. *
  62. * INTEL_SIP_SMC_REG_ERROR:
  63. * There is error during a read or write operation of the protected
  64. * registers.
  65. */
  66. #define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF
  67. #define INTEL_SIP_SMC_STATUS_OK 0x0
  68. #define INTEL_SIP_SMC_STATUS_BUSY 0x1
  69. #define INTEL_SIP_SMC_STATUS_REJECTED 0x2
  70. #define INTEL_SIP_SMC_STATUS_ERROR 0x4
  71. #define INTEL_SIP_SMC_REG_ERROR 0x5
  72. #define INTEL_SIP_SMC_RSU_ERROR 0x7
  73. /*
  74. * Request INTEL_SIP_SMC_FPGA_CONFIG_START
  75. *
  76. * Sync call used by service driver at EL1 to request the FPGA in EL3 to
  77. * be prepare to receive a new configuration.
  78. *
  79. * Call register usage:
  80. * a0: INTEL_SIP_SMC_FPGA_CONFIG_START.
  81. * a1: flag for full or partial configuration
  82. * 0 full reconfiguration.
  83. * 1 partial reconfiguration.
  84. * a2-7: not used.
  85. *
  86. * Return status:
  87. * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR.
  88. * a1-3: not used.
  89. */
  90. #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1
  91. #define INTEL_SIP_SMC_FPGA_CONFIG_START \
  92. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START)
  93. /*
  94. * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE
  95. *
  96. * Async call used by service driver at EL1 to provide FPGA configuration data
  97. * to secure world.
  98. *
  99. * Call register usage:
  100. * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE.
  101. * a1: 64bit physical address of the configuration data memory block
  102. * a2: Size of configuration data block.
  103. * a3-7: not used.
  104. *
  105. * Return status:
  106. * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY,
  107. * INTEL_SIP_SMC_STATUS_REJECTED or INTEL_SIP_SMC_STATUS_ERROR.
  108. * a1: 64bit physical address of 1st completed memory block if any completed
  109. * block, otherwise zero value.
  110. * a2: 64bit physical address of 2nd completed memory block if any completed
  111. * block, otherwise zero value.
  112. * a3: 64bit physical address of 3rd completed memory block if any completed
  113. * block, otherwise zero value.
  114. */
  115. #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE 2
  116. #define INTEL_SIP_SMC_FPGA_CONFIG_WRITE \
  117. INTEL_SIP_SMC_STD_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE)
  118. /*
  119. * Request INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE
  120. *
  121. * Sync call used by service driver at EL1 to track the completed write
  122. * transactions. This request is called after INTEL_SIP_SMC_FPGA_CONFIG_WRITE
  123. * call returns INTEL_SIP_SMC_STATUS_BUSY.
  124. *
  125. * Call register usage:
  126. * a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE.
  127. * a1-7: not used.
  128. *
  129. * Return status:
  130. * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or
  131. * INTEL_SIP_SMC_STATUS_ERROR.
  132. * a1: 64bit physical address of 1st completed memory block.
  133. * a2: 64bit physical address of 2nd completed memory block if
  134. * any completed block, otherwise zero value.
  135. * a3: 64bit physical address of 3rd completed memory block if
  136. * any completed block, otherwise zero value.
  137. */
  138. #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE 3
  139. #define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE \
  140. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
  141. /*
  142. * Request INTEL_SIP_SMC_FPGA_CONFIG_ISDONE
  143. *
  144. * Sync call used by service driver at EL1 to inform secure world that all
  145. * data are sent, to check whether or not the secure world had completed
  146. * the FPGA configuration process.
  147. *
  148. * Call register usage:
  149. * a0: INTEL_SIP_SMC_FPGA_CONFIG_ISDONE.
  150. * a1-7: not used.
  151. *
  152. * Return status:
  153. * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or
  154. * INTEL_SIP_SMC_STATUS_ERROR.
  155. * a1-3: not used.
  156. */
  157. #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4
  158. #define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE \
  159. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE)
  160. /*
  161. * Request INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM
  162. *
  163. * Sync call used by service driver at EL1 to query the physical address of
  164. * memory block reserved by secure monitor software.
  165. *
  166. * Call register usage:
  167. * a0:INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM.
  168. * a1-7: not used.
  169. *
  170. * Return status:
  171. * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
  172. * a1: start of physical address of reserved memory block.
  173. * a2: size of reserved memory block.
  174. * a3: not used.
  175. */
  176. #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM 5
  177. #define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM \
  178. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM)
  179. /*
  180. * Request INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK
  181. *
  182. * For SMC loop-back mode only, used for internal integration, debugging
  183. * or troubleshooting.
  184. *
  185. * Call register usage:
  186. * a0: INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK.
  187. * a1-7: not used.
  188. *
  189. * Return status:
  190. * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
  191. * a1-3: not used.
  192. */
  193. #define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK 6
  194. #define INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK \
  195. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK)
  196. /*
  197. * Request INTEL_SIP_SMC_REG_READ
  198. *
  199. * Read a protected register using SMCCC
  200. *
  201. * Call register usage:
  202. * a0: INTEL_SIP_SMC_REG_READ.
  203. * a1: register address.
  204. * a2-7: not used.
  205. *
  206. * Return status:
  207. * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
  208. * a1: Value in the register
  209. * a2-3: not used.
  210. */
  211. #define INTEL_SIP_SMC_FUNCID_REG_READ 7
  212. #define INTEL_SIP_SMC_REG_READ \
  213. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ)
  214. /*
  215. * Request INTEL_SIP_SMC_REG_WRITE
  216. *
  217. * Write a protected register using SMCCC
  218. *
  219. * Call register usage:
  220. * a0: INTEL_SIP_SMC_REG_WRITE.
  221. * a1: register address
  222. * a2: value to program into register.
  223. * a3-7: not used.
  224. *
  225. * Return status:
  226. * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
  227. * a1-3: not used.
  228. */
  229. #define INTEL_SIP_SMC_FUNCID_REG_WRITE 8
  230. #define INTEL_SIP_SMC_REG_WRITE \
  231. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE)
  232. /*
  233. * Request INTEL_SIP_SMC_FUNCID_REG_UPDATE
  234. *
  235. * Update one or more bits in a protected register using a
  236. * read-modify-write operation.
  237. *
  238. * Call register usage:
  239. * a0: INTEL_SIP_SMC_REG_UPDATE.
  240. * a1: register address
  241. * a2: Write Mask.
  242. * a3: Value to write.
  243. * a4-7: not used.
  244. *
  245. * Return status:
  246. * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
  247. * a1-3: Not used.
  248. */
  249. #define INTEL_SIP_SMC_FUNCID_REG_UPDATE 9
  250. #define INTEL_SIP_SMC_REG_UPDATE \
  251. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_UPDATE)
  252. /*
  253. * Request INTEL_SIP_SMC_RSU_STATUS
  254. *
  255. * Sync call used by service driver at EL1 to query the RSU status
  256. *
  257. * Call register usage:
  258. * a0 INTEL_SIP_SMC_RSU_STATUS
  259. * a1-7 not used
  260. *
  261. * Return status
  262. * a0: Current Image
  263. * a1: Last Failing Image
  264. * a2: Version [width 32 bit] | State [width 32 bit]
  265. * a3: Error details [width 32 bit] | Error location [width 32 bit]
  266. *
  267. * Or
  268. *
  269. * a0: INTEL_SIP_SMC_RSU_ERROR
  270. */
  271. #define INTEL_SIP_SMC_FUNCID_RSU_STATUS 11
  272. #define INTEL_SIP_SMC_RSU_STATUS \
  273. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_STATUS)
  274. /*
  275. * Request INTEL_SIP_SMC_RSU_UPDATE
  276. *
  277. * Sync call used by service driver at EL1 to tell you next reboot is RSU_UPDATE
  278. *
  279. * Call register usage:
  280. * a0 INTEL_SIP_SMC_RSU_UPDATE
  281. * a1 64bit physical address of the configuration data memory in flash
  282. * a2-7 not used
  283. *
  284. * Return status
  285. * a0 INTEL_SIP_SMC_STATUS_OK
  286. */
  287. #define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12
  288. #define INTEL_SIP_SMC_RSU_UPDATE \
  289. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE)
  290. /*
  291. * Request INTEL_SIP_SMC_ECC_DBE
  292. *
  293. * Sync call used by service driver at EL1 alert EL3 that a Double Bit
  294. * ECC error has occurred.
  295. *
  296. * Call register usage:
  297. * a0 INTEL_SIP_SMC_ECC_DBE
  298. * a1 SysManager Double Bit Error value
  299. * a2-7 not used
  300. *
  301. * Return status
  302. * a0 INTEL_SIP_SMC_STATUS_OK
  303. */
  304. #define INTEL_SIP_SMC_FUNCID_ECC_DBE 13
  305. #define INTEL_SIP_SMC_ECC_DBE \
  306. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_ECC_DBE)
  307. /*
  308. * Request INTEL_SIP_SMC_RSU_NOTIFY
  309. *
  310. * Sync call used by service driver at EL1 to report HPS software execution stage
  311. *
  312. * Call register usage:
  313. * a0 INTEL_SIP_SMC_RSU_NOTIFY
  314. * a1 32bit HPS software execution stage
  315. * a2-7 not used
  316. *
  317. * Return status
  318. * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
  319. */
  320. #define INTEL_SIP_SMC_FUNCID_RSU_NOTIFY 14
  321. #define INTEL_SIP_SMC_RSU_NOTIFY \
  322. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_NOTIFY)
  323. /*
  324. * Request INTEL_SIP_SMC_RSU_RETRY_COUNTER
  325. *
  326. * Sync call used by service driver at EL1 to query the RSU retry counter
  327. *
  328. * Call register usage:
  329. * a0 INTEL_SIP_SMC_RSU_RETRY_COUNTER
  330. * a1-7 not used
  331. *
  332. * Return status
  333. * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_RSU_ERROR.
  334. * a1 retry counter
  335. */
  336. #define INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER 15
  337. #define INTEL_SIP_SMC_RSU_RETRY_COUNTER \
  338. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER)
  339. /*
  340. * Request INTEL_SIP_SMC_RSU_DCMF_VERSION
  341. *
  342. * Sync call used by service driver at EL1 to query DCMF version
  343. *
  344. * Call register usage:
  345. * a0 INTEL_SIP_SMC_RSU_DCMF_VERSION
  346. * a1-7 not used
  347. *
  348. * Return status
  349. * a0 INTEL_SIP_SMC_STATUS_OK
  350. * a1 dcmf1 version | dcmf0 version
  351. * a2 dcmf3 version | dcmf2 version
  352. *
  353. * Or
  354. *
  355. * a0 INTEL_SIP_SMC_RSU_ERROR
  356. */
  357. #define INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION 16
  358. #define INTEL_SIP_SMC_RSU_DCMF_VERSION \
  359. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION)
  360. /*
  361. * Request INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION
  362. *
  363. * Sync call used by SSBL (EL2) to copy DCMF version to ATF memory
  364. *
  365. * Call register usage:
  366. * a0 INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION
  367. * a1 dcmf1 version | dcmf0 version
  368. * a2 dcmf3 version | dcmf2 version
  369. *
  370. * Return status
  371. * a0 INTEL_SIP_SMC_STATUS_OK
  372. */
  373. #define INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_VERSION 17
  374. #define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION \
  375. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_VERSION)
  376. /*
  377. * Request INTEL_SIP_SMC_RSU_MAX_RETRY
  378. *
  379. * Sync call used by service driver at EL1 to query max_retry parameter
  380. *
  381. * Call register usage:
  382. * a0 INTEL_SIP_SMC_RSU_MAX_RETRY
  383. * a1-7 not used
  384. *
  385. * Return status
  386. * a0 INTEL_SIP_SMC_STATUS_OK
  387. * a1 max_retry
  388. *
  389. * Or
  390. *
  391. * a0 INTEL_SIP_SMC_RSU_ERROR
  392. */
  393. #define INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY 18
  394. #define INTEL_SIP_SMC_RSU_MAX_RETRY \
  395. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY)
  396. /*
  397. * Request INTEL_SIP_SMC_RSU_COPY_MAX_RETRY
  398. *
  399. * Sync call used by SSBL (EL2) to copy RSU 'max retry' to ATF memory
  400. *
  401. * Call register usage:
  402. * a0 INTEL_SIP_SMC_RSU_COPY_MAX_RETRY
  403. * a1 max retry
  404. * a2-7 not used
  405. *
  406. * Return status
  407. * a0 INTEL_SIP_SMC_STATUS_OK
  408. */
  409. #define INTEL_SIP_SMC_FUNCID_RSU_COPY_MAX_RETRY 19
  410. #define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY \
  411. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_MAX_RETRY)
  412. /*
  413. * Request INTEL_SIP_SMC_RSU_DCMF_STATUS
  414. *
  415. * Sync call used by service driver at EL1 to query DCMF status
  416. *
  417. * Call register usage:
  418. * a0 INTEL_SIP_SMC_RSU_DCMF_STATUS
  419. * a1-7 not used
  420. *
  421. * Return status
  422. * a0 INTEL_SIP_SMC_STATUS_OK
  423. * a1 dcmf3 status | dcmf2 status | dcmf1 status | dcmf0 status
  424. *
  425. * Or
  426. *
  427. * a0 INTEL_SIP_SMC_RSU_ERROR
  428. */
  429. #define INTEL_SIP_SMC_FUNCID_RSU_DCMF_STATUS 20
  430. #define INTEL_SIP_SMC_RSU_DCMF_STATUS \
  431. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_STATUS)
  432. /*
  433. * Request INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS
  434. *
  435. * Sync call used by SSBL (EL2) to copy RSU 'dcmf status' to ATF memory
  436. *
  437. * Call register usage:
  438. * a0 INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS
  439. * a1 dcmf status
  440. * a2-7 not used
  441. *
  442. * Return status
  443. * a0 INTEL_SIP_SMC_STATUS_OK
  444. */
  445. #define INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_STATUS 21
  446. #define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS \
  447. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_COPY_DCMF_STATUS)
  448. /*
  449. * Request INTEL_SIP_SMC_HPS_SET_BRIDGES
  450. *
  451. * Enable/disable the SoC FPGA bridges
  452. *
  453. * Call register usage:
  454. * a0 INTEL_SIP_SMC_HPS_SET_BRIDGES
  455. * a1 Set bridges status:
  456. * 0 - Disable
  457. * 1 - Enable
  458. * a2-7 not used
  459. *
  460. * Return status
  461. * a0 INTEL_SIP_SMC_STATUS_OK
  462. */
  463. #define INTEL_SIP_SMC_FUNCID_HPS_SET_BRIDGES 50
  464. #define INTEL_SIP_SMC_HPS_SET_BRIDGES \
  465. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_BRIDGES)
  466. /*
  467. * Request INTEL_SIP_SMC_MBOX_SEND_CMD
  468. *
  469. * Send mailbox command to SDM
  470. *
  471. * Call register usage:
  472. * a0 INTEL_SIP_SMC_MBOX_SEND_CMD
  473. * a1 Mailbox command
  474. * a2 64bit physical address pointer to command's arguments
  475. * a3 Length of the argument
  476. * a4 Urgent command:
  477. * 0 - Disable
  478. * 1 - Enable
  479. * a5 64bit physical address pointer to a buffer for receiving responses
  480. * a6 Length of the buffer
  481. *
  482. * Return status
  483. * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR
  484. * a1 Status of mailbox response
  485. * a2 Received length in the buffer
  486. */
  487. #define INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD 60
  488. #define INTEL_SIP_SMC_MBOX_SEND_CMD \
  489. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_MBOX_SEND_CMD)
  490. /*
  491. * Request INTEL_SIP_SMC_HPS_SET_PHYINTF
  492. *
  493. * Select EMACx PHY interface
  494. *
  495. * Call register usage:
  496. * a0 INTEL_SIP_SMC_HPS_SET_PHYINTF
  497. * a1 EMAC number:
  498. * 0 - EMAC0
  499. * 1 - EMAC1
  500. * 2 - EMAC2
  501. * a2 Type of PHY interface:
  502. * 0 - GMII_MII
  503. * 1 - RGMII
  504. * 2 - RMII
  505. * 3 - RESET
  506. * a3-7 not used
  507. *
  508. * Return status
  509. * a0 INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR
  510. */
  511. #define INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF 61
  512. #define INTEL_SIP_SMC_HPS_SET_PHYINTF \
  513. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_PHYINTF)
  514. /*
  515. * Request INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK
  516. *
  517. * Select which phase shift of the clocks (drvsel & smplsel) for SDMMC
  518. *
  519. * Call register usage:
  520. * a0 INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK
  521. * a1 Select which phase shift of the clock for cclk_in_drv (drvsel):
  522. * 0 - 0 degree
  523. * 1 - 45 degrees
  524. * 2 - 90 degrees
  525. * 3 - 135 degrees
  526. * 4 - 180 degrees
  527. * 5 - 225 degrees
  528. * 6 - 270 degrees
  529. * 7 - 315 degrees
  530. * a2 Select which phase shift of the clock for cclk_in_sample (smplsel):
  531. * (Same as above)
  532. * a3-7 not used
  533. *
  534. * Return status
  535. * a0 INTEL_SIP_SMC_STATUS_OK
  536. */
  537. #define INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK 62
  538. #define INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK \
  539. INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_HPS_SET_SDMMC_CCLK)
  540. #endif