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+/*
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+ * Copyright 2021 StarFive, Inc
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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+ * as published by the Free Software Foundation, version 2.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <common.h>
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+#include <dm/device.h>
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+#include <dm/read.h>
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+#include <linux/bitops.h>
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+#include <linux/delay.h>
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+#include <linux/io.h>
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+#include <misc.h>
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+
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+#include <asm/arch/global_reg.h>
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+#include <asm/arch/io.h>
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+
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+#define BYTES_PER_FUSE 4
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+
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+// otp reg offset
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+#define OTP_CFGR 0x00
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+#define OTPC_IER 0x04
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+#define OTPC_SRR 0x08
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+#define OTP_OPRR 0x0c
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+#define OTPC_CTLR 0x10
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+#define OTPC_ADDRR 0x14
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+#define OTPC_DINR 0x18
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+#define OTPC_DOUTR 0x1c
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+
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+#define OTP_MEM_START 0x800
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+#define OTP_MEM_SIZE 0x800
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+#define OTP_EMPTY_CELL_VALUE 0xffffffffUL
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+
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+// cfgr (offset 0x00)
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+#define OTP_CFGR_PRG_CNT_MASK 0xff
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+#define OTP_CFGR_PRG_CNT_SHIFT 0
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+#define OTP_CFGR_DIV_1US_MASK 0xff
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+#define OTP_CFGR_DIV_1US_SHIFT 8
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+#define OTP_CFGR_RD_CYC_MASK 0x0f
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+#define OTP_CFGR_RD_CYC_SHIFT 16
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+
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+// ier (offset 0x04)
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+#define OTPC_IER_DONE_IE BIT(0)
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+#define OTPC_IER_BUSY_OPR_IE BIT(1)
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+
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+// srr (offset 0x08)
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+#define OTPC_SRR_DONE BIT(0)
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+#define OTPC_SRR_BUSY_OPR BIT(1)
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+#define OTPC_SRR_INFO_RD_LOCK BIT(29)
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+#define OTPC_SRR_INFO_WR_LOCK BIT(30)
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+#define OTPC_SRR_BUSY BIT(31)
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+
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+// oprr (offset 0x0c)
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+#define OTP_OPRR_OPR_MASK 0x00000007
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+#define OTP_OPRR_OPR_SHIFT 0
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+
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+#define OTP_OPR_STANDBY 0x0 // user mode
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+#define OTP_OPR_READ 0x1 // user mode
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+#define OTP_OPR_MARGIN_READ_PROG 0x2 // testing mode
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+#define OTP_OPR_MARGIN_READ_INIT 0x3 // testing mode
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+#define OTP_OPR_PROGRAM 0x4 // user mode
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+#define OTP_OPR_DEEP_STANDBY 0x5 // user mode
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+#define OTP_OPR_DEBUG 0x6 // user mode
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+
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+// ctlr (offset 0x10, see EG512X32TH028CW01_v1.0.pdf "Pin Description")
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+#define OTPC_CTLR_PCE BIT(0)
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+#define OTPC_CTLR_PTM_MASK 0x0000000e
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+#define OTPC_CTLR_PTM_SHIFT 1
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+#define OTPC_CTLR_PDSTB BIT(4)
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+#define OTPC_CTLR_PTR BIT(5)
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+#define OTPC_CTLR_PPROG BIT(6)
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+#define OTPC_CTLR_PWE BIT(7)
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+#define OTPC_CTLR_PCLK BIT(8)
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+
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+// addrr (offset 0x14)
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+#define OTPC_ADDRR_PA_MASK 0x000001ff
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+#define OTPC_ADDRR_PA_SHIFT 0
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+
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+/*
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+data formate
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+struct starfive_otp_data{
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+ char vendor[32];
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+ uint64_t sn;
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+ uint8_t mac_addr[6];
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+ uint8_t padding_0[2];
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+}
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+*/
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+
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+#define STARFIVE_OTP_GPIO 56 /*control power*/
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+
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+struct starfive_otp_regs {
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+ /* TODO: add otp ememory_eg512x32 registers define */
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+ uint32_t otp_cfg; /*!< timing Register., Address offset = 0x00 */
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+ uint32_t otpc_ie; /*!< interrupt Enable Register., Address offset = 0x04 */
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+ uint32_t otpc_sr; /*!< status Register., Address offset = 0x08 */
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+ uint32_t otp_opr; /*!< operation mode select Register., Address offset = 0x0C */
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+ uint32_t otpc_ctl; /*!< otp control port, Address offset = 0x10 */
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+ uint32_t otpc_addr; /*!< otp pa port , Address offset = 0x14 */
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+ uint32_t otpc_din; /*!< otp pdin port, Address offset = 0x18 */
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+ uint32_t otpc_dout; /*!< otp pdout, Address offset = 0x1C */
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+};
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+
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+struct starfive_otp_platdata {
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+ struct starfive_otp_regs __iomem *regs;
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+ u32 total_fuses;
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+};
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+
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+static void gpio_direction_output(u32 gpio, u32 val)
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+{
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+ volatile uint32_t __iomem *addr = EZGPIO_FULLMUX_BASE_ADDR + 0x50 +
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+ gpio * 8;
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+
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+ MA_OUTW(addr, val);
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+ MA_OUTW(addr + 1, val);
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+}
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+
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+static void gpio_set_value(u32 gpio, u32 val)
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+{
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+ volatile uint32_t __iomem *addr = EZGPIO_FULLMUX_BASE_ADDR + 0x50 +
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+ gpio * 8;
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+
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+ MA_OUTW(addr, val);
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+}
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+
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+/*
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+ * offset and size are assumed aligned to the size of the fuses (32-bit).
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+ */
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+static int starfive_otp_read(struct udevice *dev, int offset,
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+ void *buf, int size)
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+{
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+ struct starfive_otp_platdata *plat = dev_get_plat(dev);
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+ struct starfive_otp_regs *regs = (struct starfive_otp_regs *)plat->regs;
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+ int fuseidx = offset / BYTES_PER_FUSE;
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+ int fusecount = size / BYTES_PER_FUSE;
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+ u32 fusebuf[fusecount];
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+ u32 addr = (u32)regs;
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+
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+ /* Check if offset and size are multiple of BYTES_PER_FUSE */
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+ if ((size % BYTES_PER_FUSE) || (offset % BYTES_PER_FUSE)) {
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+ printf("%s: size and offset must be multiple of 4.\n",
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+ __func__);
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+ return -EINVAL;
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+ }
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+
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+ /* check bounds */
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+ if (offset < 0 || size < 0)
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+ return -EINVAL;
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+ if (fuseidx >= plat->total_fuses)
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+ return -EINVAL;
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+ if ((fuseidx + fusecount) > plat->total_fuses)
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+ return -EINVAL;
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+
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+ //otp power off and on
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+ gpio_direction_output(STARFIVE_OTP_GPIO, 0);
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+ mdelay(5);
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+ gpio_set_value(STARFIVE_OTP_GPIO, 1);
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+ mdelay(10);
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+
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+ //otp set to read mode
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+ writel(OTP_OPR_READ, ®s->otp_opr);
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+ mdelay(5);
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+
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+ /* read all requested fuses */
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+ for (unsigned int i = 0; i < fusecount; i++, fuseidx++) {
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+ /* read the value */
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+ fusebuf[i] = readl((volatile void __iomem *)
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+ (addr + OTP_MEM_START +
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+ fuseidx * BYTES_PER_FUSE));
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+ }
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+
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+ //otp power off
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+ gpio_set_value(STARFIVE_OTP_GPIO, 0);
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+ mdelay(5);
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+
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+ /* copy out */
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+ memcpy(buf, fusebuf, size);
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+
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+ return size;
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+}
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+
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+static int starfive_otp_ofdata_to_platdata(struct udevice *dev)
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+{
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+ struct starfive_otp_platdata *plat = dev_get_plat(dev);
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+ int ret;
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+
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+ plat->regs = dev_read_addr_ptr(dev);
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+
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+ ret = dev_read_u32(dev, "fuse-count", &plat->total_fuses);
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+ if (ret < 0) {
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+ pr_err("\"fuse-count\" not found\n");
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+ return ret;
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+ }
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+ return 0;
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+}
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+
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+static const struct misc_ops starfive_otp_ops = {
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+ .read = starfive_otp_read,
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+};
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+
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+static const struct udevice_id sifive_otp_ids[] = {
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+ { .compatible = "starfive,fu740-otp" },
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+ { }
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+};
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+
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+U_BOOT_DRIVER(starfive_otp) = {
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+ .name = "starfive_otp",
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+ .id = UCLASS_MISC,
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+ .of_match = sifive_otp_ids,
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+ .of_to_plat = starfive_otp_ofdata_to_platdata,
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+ .plat_auto = sizeof(struct starfive_otp_platdata),
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+ .ops = &starfive_otp_ops,
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+};
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