Kconfig 17 KB

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  1. #
  2. # Multifunction miscellaneous devices
  3. #
  4. menu "Multifunction device drivers"
  5. config MISC
  6. bool "Enable Driver Model for Misc drivers"
  7. depends on DM
  8. help
  9. Enable driver model for miscellaneous devices. This class is
  10. used only for those do not fit other more general classes. A
  11. set of generic read, write and ioctl methods may be used to
  12. access the device.
  13. config SPL_MISC
  14. bool "Enable Driver Model for Misc drivers in SPL"
  15. depends on SPL_DM
  16. help
  17. Enable driver model for miscellaneous devices. This class is
  18. used only for those do not fit other more general classes. A
  19. set of generic read, write and ioctl methods may be used to
  20. access the device.
  21. config TPL_MISC
  22. bool "Enable Driver Model for Misc drivers in TPL"
  23. depends on TPL_DM
  24. help
  25. Enable driver model for miscellaneous devices. This class is
  26. used only for those do not fit other more general classes. A
  27. set of generic read, write and ioctl methods may be used to
  28. access the device.
  29. config ALTERA_SYSID
  30. bool "Altera Sysid support"
  31. depends on MISC
  32. help
  33. Select this to enable a sysid for Altera devices. Please find
  34. details on the "Embedded Peripherals IP User Guide" of Altera.
  35. config ATSHA204A
  36. bool "Support for Atmel ATSHA204A module"
  37. depends on MISC
  38. help
  39. Enable support for I2C connected Atmel's ATSHA204A
  40. CryptoAuthentication module found for example on the Turris Omnia
  41. board.
  42. config ROCKCHIP_EFUSE
  43. bool "Rockchip e-fuse support"
  44. depends on MISC
  45. help
  46. Enable (read-only) access for the e-fuse block found in Rockchip
  47. SoCs: accesses can either be made using byte addressing and a length
  48. or through child-nodes that are generated based on the e-fuse map
  49. retrieved from the DTS.
  50. This driver currently supports the RK3399 only, but can easily be
  51. extended (by porting the read function from the Linux kernel sources)
  52. to support other recent Rockchip devices.
  53. config ROCKCHIP_OTP
  54. bool "Rockchip OTP Support"
  55. depends on MISC
  56. help
  57. Enable (read-only) access for the one-time-programmable memory block
  58. found in Rockchip SoCs: accesses can either be made using byte
  59. addressing and a length or through child-nodes that are generated
  60. based on the e-fuse map retrieved from the DTS.
  61. config SIFIVE_OTP
  62. bool "SiFive eMemory OTP driver"
  63. depends on MISC
  64. help
  65. Enable support for reading and writing the eMemory OTP on the
  66. SiFive SoCs.
  67. config STARFIVE_OTP
  68. bool "StarFive eMemory OTP driver"
  69. depends on MISC && VIC_BEAGLE_V
  70. default y if VIC_BEAGLE_V
  71. help
  72. Enable support for reading and writing the eMemory OTP on the
  73. StarFive SoCs.
  74. config VEXPRESS_CONFIG
  75. bool "Enable support for Arm Versatile Express config bus"
  76. depends on MISC
  77. help
  78. If you say Y here, you will get support for accessing the
  79. configuration bus on the Arm Versatile Express boards via
  80. a sysreg driver.
  81. config CMD_CROS_EC
  82. bool "Enable crosec command"
  83. depends on CROS_EC
  84. help
  85. Enable command-line access to the Chrome OS EC (Embedded
  86. Controller). This provides the 'crosec' command which has
  87. a number of sub-commands for performing EC tasks such as
  88. updating its flash, accessing a small saved context area
  89. and talking to the I2C bus behind the EC (if there is one).
  90. config CROS_EC
  91. bool "Enable Chrome OS EC"
  92. help
  93. Enable access to the Chrome OS EC. This is a separate
  94. microcontroller typically available on a SPI bus on Chromebooks. It
  95. provides access to the keyboard, some internal storage and may
  96. control access to the battery and main PMIC depending on the
  97. device. You can use the 'crosec' command to access it.
  98. config SPL_CROS_EC
  99. bool "Enable Chrome OS EC in SPL"
  100. depends on SPL
  101. help
  102. Enable access to the Chrome OS EC in SPL. This is a separate
  103. microcontroller typically available on a SPI bus on Chromebooks. It
  104. provides access to the keyboard, some internal storage and may
  105. control access to the battery and main PMIC depending on the
  106. device. You can use the 'crosec' command to access it.
  107. config TPL_CROS_EC
  108. bool "Enable Chrome OS EC in TPL"
  109. depends on TPL
  110. help
  111. Enable access to the Chrome OS EC in TPL. This is a separate
  112. microcontroller typically available on a SPI bus on Chromebooks. It
  113. provides access to the keyboard, some internal storage and may
  114. control access to the battery and main PMIC depending on the
  115. device. You can use the 'crosec' command to access it.
  116. config CROS_EC_I2C
  117. bool "Enable Chrome OS EC I2C driver"
  118. depends on CROS_EC
  119. help
  120. Enable I2C access to the Chrome OS EC. This is used on older
  121. ARM Chromebooks such as snow and spring before the standard bus
  122. changed to SPI. The EC will accept commands across the I2C using
  123. a special message protocol, and provide responses.
  124. config CROS_EC_LPC
  125. bool "Enable Chrome OS EC LPC driver"
  126. depends on CROS_EC
  127. help
  128. Enable I2C access to the Chrome OS EC. This is used on x86
  129. Chromebooks such as link and falco. The keyboard is provided
  130. through a legacy port interface, so on x86 machines the main
  131. function of the EC is power and thermal management.
  132. config SPL_CROS_EC_LPC
  133. bool "Enable Chrome OS EC LPC driver in SPL"
  134. depends on CROS_EC
  135. help
  136. Enable I2C access to the Chrome OS EC. This is used on x86
  137. Chromebooks such as link and falco. The keyboard is provided
  138. through a legacy port interface, so on x86 machines the main
  139. function of the EC is power and thermal management.
  140. config TPL_CROS_EC_LPC
  141. bool "Enable Chrome OS EC LPC driver in TPL"
  142. depends on CROS_EC
  143. help
  144. Enable I2C access to the Chrome OS EC. This is used on x86
  145. Chromebooks such as link and falco. The keyboard is provided
  146. through a legacy port interface, so on x86 machines the main
  147. function of the EC is power and thermal management.
  148. config CROS_EC_SANDBOX
  149. bool "Enable Chrome OS EC sandbox driver"
  150. depends on CROS_EC && SANDBOX
  151. help
  152. Enable a sandbox emulation of the Chrome OS EC. This supports
  153. keyboard (use the -l flag to enable the LCD), verified boot context,
  154. EC flash read/write/erase support and a few other things. It is
  155. enough to perform a Chrome OS verified boot on sandbox.
  156. config SPL_CROS_EC_SANDBOX
  157. bool "Enable Chrome OS EC sandbox driver in SPL"
  158. depends on SPL_CROS_EC && SANDBOX
  159. help
  160. Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
  161. keyboard (use the -l flag to enable the LCD), verified boot context,
  162. EC flash read/write/erase support and a few other things. It is
  163. enough to perform a Chrome OS verified boot on sandbox.
  164. config TPL_CROS_EC_SANDBOX
  165. bool "Enable Chrome OS EC sandbox driver in TPL"
  166. depends on TPL_CROS_EC && SANDBOX
  167. help
  168. Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
  169. keyboard (use the -l flag to enable the LCD), verified boot context,
  170. EC flash read/write/erase support and a few other things. It is
  171. enough to perform a Chrome OS verified boot on sandbox.
  172. config CROS_EC_SPI
  173. bool "Enable Chrome OS EC SPI driver"
  174. depends on CROS_EC
  175. help
  176. Enable SPI access to the Chrome OS EC. This is used on newer
  177. ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
  178. provides a faster and more robust interface than I2C but the bugs
  179. are less interesting.
  180. config DS4510
  181. bool "Enable support for DS4510 CPU supervisor"
  182. help
  183. Enable support for the Maxim DS4510 CPU supervisor. It has an
  184. integrated 64-byte EEPROM, four programmable non-volatile I/O pins
  185. and a configurable timer for the supervisor function. The device is
  186. connected over I2C.
  187. config FSL_SEC_MON
  188. bool "Enable FSL SEC_MON Driver"
  189. help
  190. Freescale Security Monitor block is responsible for monitoring
  191. system states.
  192. Security Monitor can be transitioned on any security failures,
  193. like software violations or hardware security violations.
  194. config IRQ
  195. bool "Intel Interrupt controller"
  196. depends on X86 || SANDBOX
  197. help
  198. This enables support for Intel interrupt controllers, including ITSS.
  199. Some devices have extra features, such as Apollo Lake. The
  200. device has its own uclass since there are several operations
  201. involved.
  202. config JZ4780_EFUSE
  203. bool "Ingenic JZ4780 eFUSE support"
  204. depends on ARCH_JZ47XX
  205. help
  206. This selects support for the eFUSE on Ingenic JZ4780 SoCs.
  207. config MXC_OCOTP
  208. bool "Enable MXC OCOTP Driver"
  209. depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
  210. default y
  211. help
  212. If you say Y here, you will get support for the One Time
  213. Programmable memory pages that are stored on the some
  214. Freescale i.MX processors.
  215. config NUVOTON_NCT6102D
  216. bool "Enable Nuvoton NCT6102D Super I/O driver"
  217. help
  218. If you say Y here, you will get support for the Nuvoton
  219. NCT6102D Super I/O driver. This can be used to enable or
  220. disable the legacy UART, the watchdog or other devices
  221. in the Nuvoton Super IO chips on X86 platforms.
  222. config P2SB
  223. bool "Intel Primary to Sideband Bridge"
  224. depends on X86 || SANDBOX
  225. help
  226. This enables support for the Intel Primary to Sideband Bridge,
  227. abbreviated to P2SB. The P2SB is used to access various peripherals
  228. such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
  229. space. The space is segmented into different channels and peripherals
  230. are accessed by device-specific means within those channels. Devices
  231. should be added in the device tree as subnodes of the P2SB. A
  232. Peripheral Channel Register? (PCR) API is provided to access those
  233. devices - see pcr_readl(), etc.
  234. config SPL_P2SB
  235. bool "Intel Primary to Sideband Bridge in SPL"
  236. depends on SPL && (X86 || SANDBOX)
  237. help
  238. The Primary to Sideband Bridge is used to access various peripherals
  239. through memory-mapped I/O in a large chunk of PCI space. The space is
  240. segmented into different channels and peripherals are accessed by
  241. device-specific means within those channels. Devices should be added
  242. in the device tree as subnodes of the p2sb.
  243. config TPL_P2SB
  244. bool "Intel Primary to Sideband Bridge in TPL"
  245. depends on TPL && (X86 || SANDBOX)
  246. help
  247. The Primary to Sideband Bridge is used to access various peripherals
  248. through memory-mapped I/O in a large chunk of PCI space. The space is
  249. segmented into different channels and peripherals are accessed by
  250. device-specific means within those channels. Devices should be added
  251. in the device tree as subnodes of the p2sb.
  252. config PWRSEQ
  253. bool "Enable power-sequencing drivers"
  254. depends on DM
  255. help
  256. Power-sequencing drivers provide support for controlling power for
  257. devices. They are typically referenced by a phandle from another
  258. device. When the device is started up, its power sequence can be
  259. initiated.
  260. config SPL_PWRSEQ
  261. bool "Enable power-sequencing drivers for SPL"
  262. depends on PWRSEQ
  263. help
  264. Power-sequencing drivers provide support for controlling power for
  265. devices. They are typically referenced by a phandle from another
  266. device. When the device is started up, its power sequence can be
  267. initiated.
  268. config PCA9551_LED
  269. bool "Enable PCA9551 LED driver"
  270. help
  271. Enable driver for PCA9551 LED controller. This controller
  272. is connected via I2C. So I2C needs to be enabled.
  273. config PCA9551_I2C_ADDR
  274. hex "I2C address of PCA9551 LED controller"
  275. depends on PCA9551_LED
  276. default 0x60
  277. help
  278. The I2C address of the PCA9551 LED controller.
  279. config STM32MP_FUSE
  280. bool "Enable STM32MP fuse wrapper providing the fuse API"
  281. depends on ARCH_STM32MP && MISC
  282. default y if CMD_FUSE
  283. help
  284. If you say Y here, you will get support for the fuse API (OTP)
  285. for STM32MP architecture.
  286. This API is needed for CMD_FUSE.
  287. config STM32_RCC
  288. bool "Enable RCC driver for the STM32 SoC's family"
  289. depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
  290. help
  291. Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
  292. block) is responsible of the management of the clock and reset
  293. generation.
  294. This driver is similar to an MFD driver in the Linux kernel.
  295. config TEGRA_CAR
  296. bool "Enable support for the Tegra CAR driver"
  297. depends on TEGRA_NO_BPMP
  298. help
  299. The Tegra CAR (Clock and Reset Controller) is a HW module that
  300. controls almost all clocks and resets in a Tegra SoC.
  301. config TEGRA186_BPMP
  302. bool "Enable support for the Tegra186 BPMP driver"
  303. depends on TEGRA186
  304. help
  305. The Tegra BPMP (Boot and Power Management Processor) is a separate
  306. auxiliary CPU embedded into Tegra to perform power management work,
  307. and controls related features such as clocks, resets, power domains,
  308. PMIC I2C bus, etc. This driver provides the core low-level
  309. communication path by which feature-specific drivers (such as clock)
  310. can make requests to the BPMP. This driver is similar to an MFD
  311. driver in the Linux kernel.
  312. config TEST_DRV
  313. bool "Enable support for test drivers"
  314. default y if SANDBOX
  315. help
  316. This enables drivers and uclasses that provides a way of testing the
  317. operations of memory allocation and driver/uclass methods in driver
  318. model. This should only be enabled for testing as it is not useful for
  319. anything else.
  320. config TWL4030_LED
  321. bool "Enable TWL4030 LED controller"
  322. help
  323. Enable this to add support for the TWL4030 LED controller.
  324. config WINBOND_W83627
  325. bool "Enable Winbond Super I/O driver"
  326. help
  327. If you say Y here, you will get support for the Winbond
  328. W83627 Super I/O driver. This can be used to enable the
  329. legacy UART or other devices in the Winbond Super IO chips
  330. on X86 platforms.
  331. config QFW
  332. bool
  333. help
  334. Hidden option to enable QEMU fw_cfg interface. This will be selected by
  335. either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
  336. config I2C_EEPROM
  337. bool "Enable driver for generic I2C-attached EEPROMs"
  338. depends on MISC
  339. help
  340. Enable a generic driver for EEPROMs attached via I2C.
  341. config SPL_I2C_EEPROM
  342. bool "Enable driver for generic I2C-attached EEPROMs for SPL"
  343. depends on MISC && SPL && SPL_DM
  344. help
  345. This option is an SPL-variant of the I2C_EEPROM option.
  346. See the help of I2C_EEPROM for details.
  347. if I2C_EEPROM
  348. config SYS_I2C_EEPROM_ADDR
  349. hex "Chip address of the EEPROM device"
  350. default 0
  351. config SYS_I2C_EEPROM_BUS
  352. int "I2C bus of the EEPROM device."
  353. default 0
  354. config SYS_EEPROM_SIZE
  355. int "Size in bytes of the EEPROM device"
  356. default 256
  357. config SYS_EEPROM_PAGE_WRITE_BITS
  358. int "Number of bits used to address bytes in a single page"
  359. default 0
  360. help
  361. The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
  362. A 64 byte page, for example would require six bits.
  363. config SYS_EEPROM_PAGE_WRITE_DELAY_MS
  364. int "Number of milliseconds to delay between page writes"
  365. default 0
  366. config SYS_I2C_EEPROM_ADDR_LEN
  367. int "Length in bytes of the EEPROM memory array address"
  368. default 1
  369. help
  370. Note: This is NOT the chip address length!
  371. config SYS_I2C_EEPROM_ADDR_OVERFLOW
  372. hex "EEPROM Address Overflow"
  373. default 0
  374. help
  375. EEPROM chips that implement "address overflow" are ones
  376. like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  377. address and the extra bits end up in the "chip address" bit
  378. slots. This makes a 24WC08 (1Kbyte) chip look like four 256
  379. byte chips.
  380. endif
  381. config GDSYS_RXAUI_CTRL
  382. bool "Enable gdsys RXAUI control driver"
  383. depends on MISC
  384. help
  385. Support gdsys FPGA's RXAUI control.
  386. config GDSYS_IOEP
  387. bool "Enable gdsys IOEP driver"
  388. depends on MISC
  389. help
  390. Support gdsys FPGA's IO endpoint driver.
  391. config MPC83XX_SERDES
  392. bool "Enable MPC83xx serdes driver"
  393. depends on MISC
  394. help
  395. Support for serdes found on MPC83xx SoCs.
  396. config FS_LOADER
  397. bool "Enable loader driver for file system"
  398. help
  399. This is file system generic loader which can be used to load
  400. the file image from the storage into target such as memory.
  401. The consumer driver would then use this loader to program whatever,
  402. ie. the FPGA device.
  403. config GDSYS_SOC
  404. bool "Enable gdsys SOC driver"
  405. depends on MISC
  406. help
  407. Support for gdsys IHS SOC, a simple bus associated with each gdsys
  408. IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
  409. register maps are contained within the FPGA's register map.
  410. config IHS_FPGA
  411. bool "Enable IHS FPGA driver"
  412. depends on MISC
  413. help
  414. Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
  415. gdsys devices, which supply the majority of the functionality offered
  416. by the devices. This driver supports both CON and CPU variants of the
  417. devices, depending on the device tree entry.
  418. config ESM_K3
  419. bool "Enable K3 ESM driver"
  420. depends on ARCH_K3
  421. help
  422. Support ESM (Error Signaling Module) on TI K3 SoCs.
  423. config MICROCHIP_FLEXCOM
  424. bool "Enable Microchip Flexcom driver"
  425. depends on MISC
  426. help
  427. The Atmel Flexcom is just a wrapper which embeds a SPI controller,
  428. an I2C controller and an USART.
  429. Only one function can be used at a time and is chosen at boot time
  430. according to the device tree.
  431. config K3_AVS0
  432. depends on ARCH_K3 && SPL_DM_REGULATOR
  433. bool "AVS class 0 support for K3 devices"
  434. help
  435. K3 devices have the optimized voltage values for the main voltage
  436. domains stored in efuse within the VTM IP. This driver reads the
  437. optimized voltage from the efuse, so that it can be programmed
  438. to the PMIC on board.
  439. config ESM_PMIC
  440. bool "Enable PMIC ESM driver"
  441. depends on DM_PMIC
  442. help
  443. Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
  444. typically to reboot the board in error condition.
  445. endmenu