Browse Source

riscv: make WayEnable can be configured by menuconfig

This patch also adds a debug function: cache_enable_ways_debug for
setting and printing the WayEnable register.
TekkamanV 3 years ago
parent
commit
2232385e6f

+ 18 - 2
arch/riscv/cpu/fu540/Kconfig

@@ -54,7 +54,8 @@ endif # ENV_IS_IN_SPI_FLASH
 config SIFIVE_FU540_L2CC_FLUSH
 	bool "Support Level 2 Cache Controller Flush operation of SiFive fu540"
 
-if SIFIVE_FU540_L2CC_FLUSH
+menu "Level 2 Cache Controller Flush range"
+	depends on SIFIVE_FU540_L2CC_FLUSH
 
 config SIFIVE_FU540_L2CC_FLUSH_START
 	hex "Level 2 Cache Flush operation start"
@@ -64,4 +65,19 @@ config SIFIVE_FU540_L2CC_FLUSH_SIZE
 	hex "Level 2 Cache Flush operation size"
 	default 0x800000000
 
-endif # SIFIVE_FU540_L2CC_FLUSH
+endmenu # SIFIVE_FU540_L2CC_FLUSH
+
+config SIFIVE_FU540_L2CC_WAYENABLE_DIY
+	bool "Config Level 2 Cache Controller: the largest way which has been enabled"
+
+menu "The index of the largest way"
+	depends on SIFIVE_FU540_L2CC_WAYENABLE_DIY
+
+config SIFIVE_FU540_L2CC_WAYENABLE_DIY_NUM
+	int "The index of the largest way which has been enabled for level 2 Cache "
+	default 1
+	range 0 255
+	help
+	  Range[0, 255]. The index of the largest way which has been enabled.
+
+endmenu # SIFIVE_FU540_L2CC_WAYENABLE_DIY

+ 24 - 0
arch/riscv/cpu/fu540/cache.c

@@ -52,12 +52,36 @@ int cache_enable_ways(void)
 
 	/* memory barrier */
 	mb();
+#if CONFIG_IS_ENABLED(SIFIVE_FU540_L2CC_WAYENABLE_DIY)
+	if (CONFIG_SIFIVE_FU540_L2CC_WAYENABLE_DIY_NUM >= ways)
+		(*enable) = ways;
+	(*enable) = CONFIG_SIFIVE_FU540_L2CC_WAYENABLE_DIY_NUM;
+#else
 	(*enable) = ways - 1;
+#endif //SIFIVE_FU540_L2CC_WAYENABLE_DIY
 	/* memory barrier */
 	mb();
 	return 0;
 }
 
+u32 cache_enable_ways_debug(u32 ways_input)
+{
+	fdt_addr_t base = l2cc_get_base_addr();
+	volatile u32 *enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
+
+	if (base == FDT_ADDR_T_NONE)
+		return 0xffffffff;
+
+	printf("cache config(0x%p): 0x%x --> ",	enable, readl(enable));
+	mb();
+	(*enable) = ways_input;
+	mb();
+	printf("0x%x \n", readl(enable));
+	mb();
+
+	return readl(enable);
+}
+
 #if CONFIG_IS_ENABLED(SIFIVE_FU540_L2CC_FLUSH)
 #define L2_CACHE_FLUSH64	0x200
 

+ 1 - 0
arch/riscv/include/asm/arch-fu540/cache.h

@@ -10,5 +10,6 @@
 #define _CACHE_SIFIVE_H
 
 int cache_enable_ways(void);
+u32 cache_enable_ways_debug(u32 ways_input);
 
 #endif /* _CACHE_SIFIVE_H */

+ 6 - 0
board/sifive/fu540/Kconfig

@@ -23,6 +23,12 @@ config SPL_TEXT_BASE
 config SPL_OPENSBI_LOAD_ADDR
 	default 0x80000000
 
+config CACHE_WAYENABLE
+	tristate "L2 cache wayenable"
+	default y
+	help
+	  L2 cache wayenable.
+
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select SIFIVE_FU540

+ 3 - 1
board/sifive/fu540/fu540.c

@@ -115,6 +115,8 @@ int misc_init_r(void)
 
 int board_init(void)
 {
+
+#if CONFIG_IS_ENABLED(CACHE_WAYENABLE)
 	int ret;
 
 	/* enable all cache ways */
@@ -123,6 +125,6 @@ int board_init(void)
 		debug("%s: could not enable cache ways\n", __func__);
 		return ret;
 	}
-
+#endif
 	return 0;
 }

+ 6 - 0
board/starfive/vic7100/Kconfig

@@ -32,6 +32,12 @@ config SPL_TEXT_BASE
 config SPL_OPENSBI_LOAD_ADDR
 	default 0x80000000
 
+config CACHE_WAYENABLE
+	tristate "L2 cache wayenable"
+	default n
+	help
+	  L2 cache wayenable.
+
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select SIFIVE_FU540

+ 7 - 0
cmd/Kconfig

@@ -2337,4 +2337,11 @@ config CMD_UBIFS
 	help
 	  UBIFS is a file system for flash devices which works on top of UBI.
 
+
+config CMD_CACHE_DEBUG
+	bool "L2 cache debug"
+	default y if TARGET_STARFIVE_VIC7100
+	help
+	  L2 cache debug.
+
 endmenu

+ 1 - 0
cmd/riscv/Makefile

@@ -2,3 +2,4 @@
 
 obj-$(CONFIG_CMD_EXCEPTION) += exception.o
 obj-$(CONFIG_CMD_SBI) += sbi.o
+obj-$(CONFIG_CMD_CACHE_DEBUG) += cache_debug.o

+ 34 - 0
cmd/riscv/cache_debug.c

@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * The 'sbi' command displays information about the SBI implementation.
+ *
+ * Copyright (c) 2020, Heinrich Schuchardt <xypron.glpk@gmx.de>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch-fu540/cache.h>
+
+static int do_cache_debug(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	u32 way_enable;
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	way_enable = simple_strtoul(argv[1], NULL, 10);
+	printf("Input is %d !\n", way_enable);
+	if (way_enable >= 255)
+		return CMD_RET_USAGE;
+
+	way_enable = cache_enable_ways_debug(way_enable);
+	printf("Readback is %d !\n", way_enable);
+
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	cache_debug,	2,	0,	do_cache_debug,
+	"cache config debug",
+	"wayenable number"
+);