starfive_vic7100_beagle_v.dts 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680
  1. /dts-v1/;
  2. #include "starfive_vic7100_clk.dtsi"
  3. #include <dt-bindings/starfive_fb.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. / {
  6. #address-cells = <2>;
  7. #size-cells = <2>;
  8. compatible = "sifive,freedom-u74-arty";
  9. model = "sifive,freedom-u74-arty";
  10. chosen {
  11. linux,initrd-start = <0x0 0x86100000>;
  12. linux,initrd-end = <0x0 0x8c000000>;
  13. stdout-path = "/soc/serial@12440000:115200";
  14. #bootargs = "debug console=ttyS0 rootwait";
  15. };
  16. aliases {
  17. spi0="/soc/qspi@11860000";
  18. mshc0="/soc/sdio0@10000000";
  19. mshc1="/soc/sdio1@10010000";
  20. usb0="/soc/usb@104c0000";
  21. };
  22. cpus: cpus {
  23. #address-cells = <1>;
  24. #size-cells = <0>;
  25. timebase-frequency = <6250000>;
  26. compatible = "starfive,fu74-g000";
  27. cpu@0 {
  28. clock-frequency = <0>;
  29. compatible = "starfive,rocket0", "riscv";
  30. d-cache-block-size = <64>;
  31. d-cache-sets = <64>;
  32. d-cache-size = <32768>;
  33. d-tlb-sets = <1>;
  34. d-tlb-size = <32>;
  35. device_type = "cpu";
  36. i-cache-block-size = <64>;
  37. i-cache-sets = <64>;
  38. i-cache-size = <32768>;
  39. i-tlb-sets = <1>;
  40. i-tlb-size = <32>;
  41. mmu-type = "riscv,sv39";
  42. next-level-cache = <&cachectrl>;
  43. reg = <0>;
  44. riscv,isa = "rv64imafdc";
  45. starfive,itim = <&itim0>;
  46. status = "okay";
  47. tlb-split;
  48. cpu0intctrl: interrupt-controller {
  49. #interrupt-cells = <1>;
  50. compatible = "riscv,cpu-intc";
  51. interrupt-controller;
  52. };
  53. };
  54. cpu@1 {
  55. clock-frequency = <0>;
  56. compatible = "starfive,rocket0", "riscv";
  57. d-cache-block-size = <64>;
  58. d-cache-sets = <64>;
  59. d-cache-size = <32768>;
  60. d-tlb-sets = <1>;
  61. d-tlb-size = <32>;
  62. device_type = "cpu";
  63. i-cache-block-size = <64>;
  64. i-cache-sets = <64>;
  65. i-cache-size = <32768>;
  66. i-tlb-sets = <1>;
  67. i-tlb-size = <32>;
  68. mmu-type = "riscv,sv39";
  69. next-level-cache = <&cachectrl>;
  70. reg = <1>;
  71. riscv,isa = "rv64imafdc";
  72. starfive,itim = <&itim1>;
  73. status = "okay";
  74. tlb-split;
  75. cpu1intctrl: interrupt-controller {
  76. #interrupt-cells = <1>;
  77. compatible = "riscv,cpu-intc";
  78. interrupt-controller;
  79. };
  80. };
  81. };
  82. memory@80000000 {
  83. device_type = "memory";
  84. reg = <0x0 0x80000000 0x2 0x0>;
  85. };
  86. memory@3000000000 {
  87. device_type = "memory";
  88. reg = <0x30 0x0 0x0 0x0>;
  89. };
  90. reserved-memory {
  91. #address-cells = <2>;
  92. #size-cells = <2>;
  93. ranges;
  94. linux,cma {
  95. compatible = "shared-dma-pool";
  96. reusable;
  97. size = <0x0 0x28000000>;
  98. alignment = <0x0 0x1000>;
  99. alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>;
  100. linux,cma-default;
  101. };
  102. jpu_reserved: framebuffer@c9000000 {
  103. reg = <0x0 0xc9000000 0x0 0x4000000>;
  104. };
  105. nvdla_reserved:framebuffer@d0000000{
  106. reg = <0x0 0xd0000000 0x0 0x28000000>;
  107. };
  108. vin_reserved: framebuffer@f9000000 {
  109. compatible = "shared-dma-pool";
  110. no-map;
  111. reg = <0x0 0xf9000000 0x0 0x1000000>;
  112. };
  113. sffb_reserved: framebuffer@fb000000 {
  114. compatible = "shared-dma-pool";
  115. no-map;
  116. reg = <0x0 0xfb000000 0x0 0x2000000>;
  117. };
  118. };
  119. soc {
  120. #address-cells = <2>;
  121. #size-cells = <2>;
  122. #clock-cells = <1>;
  123. compatible = "starfive,freedom-u74-arty", "simple-bus";
  124. ranges;
  125. cachectrl: cache-controller@2010000 {
  126. cache-block-size = <64>;
  127. cache-level = <2>;
  128. cache-sets = <2048>;
  129. cache-size = <2097152>;
  130. cache-unified;
  131. compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
  132. interrupt-parent = <&plic>;
  133. interrupts = <128 131 129 130>;
  134. /*next-level-cache = <&L40 &L36>;*/
  135. reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>;
  136. reg-names = "control", "sideband";
  137. };
  138. dtim: dtim@1000000 {
  139. compatible = "starfive,dtim0";
  140. reg = <0x0 0x1000000 0x0 0x2000>;
  141. reg-names = "mem";
  142. };
  143. itim0: itim@1808000 {
  144. compatible = "starfive,itim0";
  145. reg = <0x0 0x1808000 0x0 0x8000>;
  146. reg-names = "mem";
  147. };
  148. itim1: itim@1820000 {
  149. compatible = "starfive,itim0";
  150. reg = <0x0 0x1820000 0x0 0x8000>;
  151. reg-names = "mem";
  152. };
  153. clint: clint@2000000 {
  154. #interrupt-cells = <1>;
  155. compatible = "riscv,clint0";
  156. interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7 &cpu1intctrl 3 &cpu1intctrl 7 >;
  157. reg = <0x0 0x2000000 0x0 0x10000>;
  158. reg-names = "control";
  159. };
  160. plic: plic@c000000 {
  161. #interrupt-cells = <1>;
  162. compatible = "riscv,plic0";
  163. interrupt-controller;
  164. interrupts-extended = <&cpu0intctrl 11 &cpu0intctrl 9 &cpu1intctrl 11 &cpu1intctrl 9 >;
  165. reg = <0x0 0xc000000 0x0 0x4000000>;
  166. reg-names = "control";
  167. riscv,max-priority = <7>;
  168. riscv,ndev = <127>;
  169. };
  170. uart3: serial@12440000 {
  171. compatible = "snps,dw-apb-uart", "starfive,uart0";
  172. interrupt-parent = <&plic>;
  173. interrupts = <73>;
  174. reg = <0x0 0x12440000 0x0 0x10000>;
  175. reg-io-width = <4>;
  176. reg-shift = <2>;
  177. clocks = <&uartclk>, <&apb2clk>;
  178. clock-names = "baudclk", "apb_pclk";
  179. current-clock = <100000000>;
  180. current-speed = <115200>;
  181. status = "okay";
  182. };
  183. uart2: serial@12430000 {
  184. compatible = "snps,dw-apb-uart";
  185. interrupt-parent = <&plic>;
  186. interrupts = <72>;
  187. reg = <0x0 0x12430000 0x0 0x10000>;
  188. reg-io-width = <4>;
  189. reg-shift = <2>;
  190. clocks = <&uartclk>, <&apb2clk>;
  191. clock-names = "baudclk", "apb_pclk";
  192. current-clock = <100000000>;
  193. current-speed = <115200>;
  194. status = "disabled";
  195. };
  196. uart1: hs_serial@11880000 {
  197. compatible = "snps,dw-apb-uart";
  198. interrupt-parent = <&plic>;
  199. interrupts = <93>;
  200. reg = <0x0 0x11880000 0x0 0x10000>;
  201. reg-io-width = <4>;
  202. reg-shift = <2>;
  203. clocks = <&hs_uartclk>, <&apb1clk>;
  204. clock-names = "baudclk","apb_pclk";
  205. current-clock = <74250000>;
  206. current-speed = <115200>;
  207. status = "disabled";
  208. };
  209. uart0: hs_serial@11870000 {
  210. compatible = "snps,dw-apb-uart";
  211. interrupt-parent = <&plic>;
  212. interrupts = <92>;
  213. reg = <0x0 0x11870000 0x0 0x10000>;
  214. reg-io-width = <4>;
  215. reg-shift = <2>;
  216. clocks = <&hs_uartclk>, <&apb1clk>;
  217. clock-names = "baudclk", "apb_pclk";
  218. current-clock = <74250000>;
  219. current-speed = <115200>;
  220. status = "okay";
  221. };
  222. dma2p: sgdma2p@100b0000 {
  223. compatible = "snps,axi-dma-1.01a";
  224. reg = <0x0 0x100b0000 0x0 0x10000>;
  225. clocks = <&axiclk>,<&ahb0clk>;
  226. clock-names = "core-clk", "cfgr-clk";
  227. interrupt-parent = <&plic>;
  228. interrupts = <2>;
  229. dma-channels = <4>;
  230. snps,dma-masters = <1>;
  231. snps,data-width = <4>;
  232. snps,block-size = <4096 4096 4096 4096>;
  233. snps,priority = <0 1 2 3>;
  234. snps,axi-max-burst-len = <128>;
  235. status = "okay";
  236. };
  237. dma1p: sgdma1p@10500000 {
  238. compatible = "snps,axi-dma-1.01a";
  239. reg = <0x0 0x10500000 0x0 0x10000>;
  240. clocks = <&axiclk>,<&ahb0clk>;
  241. clock-names = "core-clk", "cfgr-clk";
  242. interrupt-parent = <&plic>;
  243. interrupts = <1>;
  244. dma-channels = <16>;
  245. snps,dma-masters = <1>;
  246. snps,data-width = <3>;
  247. snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
  248. snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  249. snps,axi-max-burst-len = <64>;
  250. status = "okay";
  251. };
  252. USB30: usb@104c0000 {
  253. compatible = "cdns,usb3";
  254. reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers
  255. <0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers
  256. <0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers
  257. reg-names = "otg", "xhci", "dev";
  258. interrupt-parent = <&plic>;
  259. interrupts = <43>, <44>, <52>;
  260. interrupt-names = "otg",
  261. "host",
  262. "peripheral";
  263. phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
  264. status = "okay";
  265. };
  266. gpio: gpio@11910000 {
  267. compatible = "starfive,gpio0";
  268. interrupt-parent = <&plic>;
  269. interrupts = <32>;
  270. reg = <0x0 0x11910000 0x0 0x10000>;
  271. reg-names = "control";
  272. interrupt-controller;
  273. #gpio-cells = <2>;
  274. };
  275. gpiorst:gpio-restart {
  276. compatible = "gpio-restart";
  277. gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
  278. };
  279. gpiopof:gpio-poweroff {
  280. compatible = "gpio-poweroff";
  281. gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
  282. };
  283. i2c0: i2c@118b0000 {
  284. #address-cells = <1>;
  285. #size-cells = <0>;
  286. #clock-cells = <0>;
  287. compatible = "snps,designware-i2c";
  288. reg = <0x0 0x118b0000 0x0 0x10000>;
  289. interrupt-parent = <&plic>;
  290. interrupts = <96>;
  291. clocks = <49500000>;
  292. clock-frequency = <100000>;
  293. i2c-sda-hold-time-ns = <300>;
  294. i2c-sda-falling-time-ns = <500>;
  295. i2c-scl-falling-time-ns = <500>;
  296. scl-gpio = <&gpio 62 0>;
  297. sda-gpio = <&gpio 61 0>;
  298. tda998x@70 {
  299. compatible = "nxp,tda998x";
  300. reg = <0x70>;
  301. };
  302. imx219@10 {
  303. compatible = "imx219";
  304. reg = <0x10>;
  305. reset-gpio = <&gpio 58 0>;
  306. };
  307. };
  308. i2c1: i2c@118c0000 {
  309. #address-cells = <1>;
  310. #size-cells = <0>;
  311. #clock-cells = <0>;
  312. compatible = "snps,designware-i2c";
  313. reg = <0x0 0x118c0000 0x0 0x10000>;
  314. interrupt-parent = <&plic>;
  315. interrupts = <97>;
  316. clocks = <49500000>;
  317. clock-frequency = <400000>;
  318. i2c-sda-hold-time-ns = <300>;
  319. i2c-sda-falling-time-ns = <100>;
  320. i2c-scl-falling-time-ns = <100>;
  321. scl-gpio = <&gpio 47 0>;
  322. sda-gpio = <&gpio 48 0>;
  323. };
  324. i2c2: i2c@12450000 {
  325. #address-cells = <1>;
  326. #size-cells = <0>;
  327. #clock-cells = <0>;
  328. compatible = "snps,designware-i2c";
  329. reg = <0x0 0x12450000 0x0 0x10000>;
  330. interrupt-parent = <&plic>;
  331. interrupts = <74>;
  332. clocks = <50000000>;
  333. clock-frequency = <100000>;
  334. i2c-sda-hold-time-ns = <300>;
  335. i2c-sda-falling-time-ns = <500>;
  336. i2c-scl-falling-time-ns = <500>;
  337. scl-gpio = <&gpio 60 0>;
  338. sda-gpio = <&gpio 59 0>;
  339. seeed_plane_i2c@45 {
  340. compatible = "seeed_panel";
  341. reg = <0x45>;
  342. };
  343. };
  344. trng: trng@118d0000 {
  345. compatible = "starfive,vic-rng";
  346. reg = <0x0 0x118d0000 0x0 0x10000>;
  347. interrupt-parent = <&plic>;
  348. interrupts = <98>;
  349. clocks = <&hfclk>;
  350. };
  351. crypto: crypto@100d0000 {
  352. compatible = "starfive,vic-sec";
  353. reg = <0x0 0x100d0000 0x0 0x20000>,
  354. <0x0 0x11800234 0x0 0xc>;
  355. reg-names = "secmem","secclk";
  356. interrupt-parent = <&plic>;
  357. interrupts = <31>;
  358. clocks = <&hfclk>;
  359. };
  360. /*gmac device configuration*/
  361. stmmac_axi_setup: stmmac-axi-config {
  362. snps,wr_osr_lmt = <0xf>;
  363. snps,rd_osr_lmt = <0xf>;
  364. snps,blen = <256 128 64 32 0 0 0>;
  365. };
  366. gmac:gmac@10020000{
  367. compatible = "snps,dwmac";
  368. reg = <0x0 0x10020000 0x0 0x10000>;
  369. interrupt-parent = <&plic>;
  370. interrupts = <6 7>;
  371. interrupt-names = "macirq","eth_wake_irq";
  372. max-frame-size = <9000>;
  373. phy-mode = "rgmii-txid";
  374. snps,multicast-filter-bins = <256>;
  375. snps,perfect-filter-entries = <128>;
  376. rx-fifo-depth = <32768>;
  377. tx-fifo-depth = <16384>;
  378. clocks = <&gmacclk>;
  379. clock-names = "stmmaceth";
  380. snps,fixed-burst = <1>;
  381. snps,no-pbl-x8 = <1>;
  382. /*snps,force_sf_dma_mode;*/
  383. snps,force_thresh_dma_mode;
  384. snps,axi-config = <&stmmac_axi_setup>;
  385. };
  386. nbdla: nvdla@0x11940000 {
  387. compatible = "nvidia,nvdla_os_initial";
  388. interrupt-parent = <&plic>;
  389. interrupts = <22>;
  390. memory-region = <&nvdla_reserved>;
  391. reg = <0x0 0x11940000 0x0 0x40000>;
  392. status = "okay";
  393. };
  394. jpu:coadj12@11900000 {
  395. compatible = "cm,codaj12-jpu-1";
  396. reg = <0x0 0x11900000 0x0 0x300>;
  397. memory-region = <&jpu_reserved>;
  398. interrupt-parent = <&plic>;
  399. interrupts = <24>;
  400. clocks = <&jpuclk>;
  401. clock-names = "jpege";
  402. reg-names = "control";
  403. status = "okay";
  404. };
  405. vpu_dec:vpu_dec@118F0000 {
  406. compatible = "c&m,cm511-vpu";
  407. reg = <0 0x118F0000 0 0x10000>;
  408. //memory-region = <&vpu_reserved>;
  409. interrupt-parent = <&plic>;
  410. interrupts = <23>;
  411. clocks = <&vpuclk>;
  412. clock-names = "vcodec";
  413. status = "okay";
  414. };
  415. vpu_enc:vpu_enc@118E0000 {
  416. compatible = "cm,cm521-vpu";
  417. reg = <0x0 0x118E0000 0x0 0x4000>;
  418. interrupt-parent = <&plic>;
  419. interrupts = <26>;
  420. clocks = <&vpuclk>;
  421. clock-names = "vcodec";
  422. reg-names = "control";
  423. };
  424. ptc: pwm@12490000 {
  425. compatible = "starfive,pwm0";
  426. reg = <0x0 0x12490000 0x0 0x10000>;
  427. reg-names = "control";
  428. sifive,approx-period = <100000000>;
  429. clocks = <&pwmclk>;
  430. #pwm-cells=<3>;
  431. sifive,npwm = <8>;
  432. };
  433. qspi:qspi@11860000 {
  434. compatible = "cadence,qspi","cdns,qspi-nor";
  435. #address-cells = <1>;
  436. #size-cells = <0>;
  437. reg = <0x0 0x11860000 0x0 0x10000 0x0 0x20000000 0x0 0x20000000 >;
  438. interrupts = <3>;
  439. interrupt-parent = <&plic>;
  440. clocks = <&qspi_clk>;
  441. cdns,fifo-depth = <256>;
  442. cdns,fifo-width = <4>;
  443. cdns,trigger-address = <0x00000000>;
  444. status = "okay";
  445. spi-max-frequency = <250000000>;
  446. nor_flash:nor-flash@0 {
  447. compatible = "spi-flash";
  448. reg=<0>;
  449. spi-max-frequency = <31250000>;
  450. page-size = <256>;
  451. block-size = <16>;
  452. cdns,read-delay = <4>;
  453. cdns,tshsl-ns = <1>;
  454. cdns,tsd2d-ns = <1>;
  455. cdns,tchsh-ns = <1>;
  456. cdns,tslch-ns = <1>;
  457. spi-tx-bus-width = <1>;
  458. spi-rx-bus-width = <1>;
  459. };
  460. nand_flash:nand-flash@1 {
  461. compatible = "spi-flash-nand";
  462. reg=<1>;
  463. spi-max-frequency = <31250000>;
  464. page-size = <2048>;
  465. block-size = <17>;
  466. cdns,read-delay = <4>;
  467. cdns,tshsl-ns = <1>;
  468. cdns,tsd2d-ns = <1>;
  469. cdns,tchsh-ns = <1>;
  470. cdns,tslch-ns = <1>;
  471. spi-tx-bus-width = <1>;
  472. spi-rx-bus-width = <1>;
  473. };
  474. };
  475. spi2:spi2@12410000 {
  476. compatible = "snps,dw-apb-ssi";
  477. #address-cells = <1>;
  478. #size-cells = <0>;
  479. interrupt-parent = <&plic>;
  480. interrupts = <70>;
  481. reg = <0x0 0x12410000 0x0 0x10000>;
  482. clocks = <&spiclk>;
  483. /*num-cs = <1>;
  484. cs-gpios = <&gpio 0 0>;*/
  485. spi_dev0: spi@0 {
  486. compatible = "rohm,dh2228fv";
  487. spi-max-frequency = <10000000>;
  488. reg = <0>;
  489. status = "okay";
  490. };
  491. };
  492. xrp@0 {
  493. compatible = "cdns,xrp";
  494. reg = <0x0 0xf0000000 0x0 0x01ffffff
  495. 0x10 0x72000000 0x0 0x00001000
  496. 0x10 0x72001000 0x0 0x00fff000
  497. 0x0 0x124b0000 0x0 0x00010000>;
  498. clocks = <&hfclk>;
  499. interrupt-parent = <&plic>;
  500. firmware-name = "vp6_elf";
  501. dsp-irq = <19 20>;
  502. dsp-irq-src = <0x20 0x21>;
  503. intc-irq-mode = <1>;
  504. intc-irq = <0 1>;
  505. interrupts = <27 28>;
  506. #address-cells = <1>;
  507. #size-cells = <1>;
  508. ranges = <0x40000000 0x0 0x40000000 0x01000000
  509. 0xb0000000 0x10 0x70000000 0x3000000>;
  510. dsp@0 {
  511. };
  512. };
  513. sdio0:sdio0@10000000{
  514. compatible = "snps,dw-mshc";
  515. reg = <0x0 0x10000000 0x0 0x10000>;
  516. interrupts = <4>;
  517. interrupt-parent = <&plic>;
  518. clocks = <&dwmmc_biuclk>;
  519. clock-names = "biu";
  520. clock-frequency = <100000000>;
  521. max-frequency = <10000000>;
  522. fifo-depth = <32>;
  523. card-detect-delay = <300>;
  524. fifo-watermark-aligned;
  525. data-addr = <0>;
  526. bus-width = <4>;
  527. cap-sd-highspeed;
  528. broken-cd;
  529. no-sdio;
  530. post-power-on-delay-ms = <200>;
  531. };
  532. sdio1:sdio1@10010000{
  533. compatible = "snps,dw-mshc";
  534. reg = <0x0 0x10010000 0x0 0x10000>;
  535. interrupts = <5>;
  536. interrupt-parent = <&plic>;
  537. clocks = <&dwmmc_biuclk>;
  538. clock-names = "biu";
  539. clock-frequency = <100000000>;
  540. max-frequency = <10000000>;
  541. fifo-depth = <32>;
  542. card-detect-delay = <300>;
  543. fifo-watermark-aligned;
  544. data-addr = <0>;
  545. bus-width = <4>;
  546. cap-sd-highspeed;
  547. /*broken-cd;*/
  548. cap-sdio-irq;
  549. cap-mmc-hw-reset;
  550. non-removable;
  551. enable-sdio-wakeup;
  552. keep-power-in-suspend;
  553. /*cap-power-off-card;*/
  554. cap-mmc-highspeed;
  555. /*fixed-emmc-driver-type;*/
  556. post-power-on-delay-ms = <200>;
  557. /*
  558. bcmdhd_wlan: bcmdhd_wlan@1 {
  559. compatible = "android,bcmdhd_wlan";
  560. gpios = <&gpio 26 0>;
  561. };
  562. */
  563. };
  564. sfivefb:sfivefb@12000000 {
  565. compatible = "starfive,vpp-lcdc";
  566. interrupt-parent = <&plic>;
  567. interrupts = <101>, <103>;
  568. interrupt-names = "lcdc_irq", "vpp1_irq";
  569. reg = <0x0 0x12000000 0x0 0x10000>,
  570. <0x0 0x12100000 0x0 0x10000>,
  571. <0x0 0x12040000 0x0 0x10000>,
  572. <0x0 0x12080000 0x0 0x10000>,
  573. <0x0 0x120c0000 0x0 0x10000>,
  574. <0x0 0x12240000 0x0 0x10000>,
  575. <0x0 0x12250000 0x0 0x10000>,
  576. <0x0 0x12260000 0x0 0x10000>;
  577. reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
  578. memory-region = <&sffb_reserved>;
  579. clocks = <&uartclk>, <&apb2clk>;
  580. clock-names = "baudclk", "apb_pclk";
  581. status = "okay";
  582. ddr-format = <WIN_FMT_RGB565>;/*LCDC win_format*/
  583. /*pp1 {
  584. pp-id = <1>;
  585. fifo-out;
  586. src-format = <COLOR_YUV420_NV21>;
  587. src-width = <800>;
  588. src-height = <480>;
  589. dst-format = <COLOR_RGB888_ARGB>;
  590. dst-width = <800>;
  591. dst-height = <480>;
  592. };*/
  593. };
  594. vin_sysctl:vin_sysctl@19800000 {
  595. compatible = "starfive,stf-vin";
  596. reg = <0x0 0x19800000 0x0 0x10000>,
  597. <0x0 0x19810000 0x0 0x10000>,
  598. <0x0 0x19820000 0x0 0x10000>,
  599. <0x0 0x19830000 0x0 0x10000>,
  600. <0x0 0x19840000 0x0 0x10000>,
  601. <0x0 0x19870000 0x0 0x30000>,
  602. <0x0 0x198a0000 0x0 0x30000>,
  603. <0x0 0x11800000 0x0 0x10000>,
  604. <0x0 0x11840000 0x0 0x10000>,
  605. <0x0 0x11858000 0x0 0x10000>;
  606. reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl", "isp0", "isp1", "tclk", "trst", "iopad"; interrupt-parent = <&plic>;
  607. interrupts = <119 109>;
  608. memory-region = <&vin_reserved>;
  609. /*defaule config for imx219 vin&isp*/
  610. format = <SRC_CSI2RX_VIN_ISP>;
  611. frame-width = <800>;
  612. frame-height =<480>;
  613. isp0_enable;
  614. csi-lane = <2>;
  615. csi-dlane-swaps = /bits/ 8 <1>,/bits/ 8 <2>,/bits/ 8 <3>,/bits/ 8 <4>;
  616. csi-dlane-pn-swaps = /bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>;
  617. csi-clane-swap = /bits/ 8 <0>;
  618. csi-clane-pn-swap = /bits/ 8 <0>;
  619. csi-mipiID = <0>;
  620. csi-width = <1920>;
  621. csi-height = <1080>;
  622. csi-dt = <0x2b>;
  623. };
  624. sfc_tmp:tmpsensor@124A0000 {
  625. compatible = "sfc,tempsensor";
  626. reg = <0x0 0x124A0000 0x0 0x1000>;
  627. interrupt-parent = <&plic>;
  628. interrupts = <122>;
  629. status = "okay";
  630. };
  631. otp:otp@11810000{
  632. compatible = "starfive,fu740-otp";
  633. reg = <0x0 0x11810000 0x0 0x10000>;
  634. fuse-count = <0x200>;
  635. };
  636. };
  637. };
  638. #include "tda998x_1080p.dtsi"
  639. #include "seeed5inch.dtsi"