starfive-otp.c 6.0 KB

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  1. /*
  2. * Copyright 2021 StarFive, Inc
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * as published by the Free Software Foundation, version 2.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <common.h>
  14. #include <dm/device.h>
  15. #include <dm/read.h>
  16. #include <linux/bitops.h>
  17. #include <linux/delay.h>
  18. #include <linux/io.h>
  19. #include <misc.h>
  20. #include <asm/arch/global_reg.h>
  21. #include <asm/arch/io.h>
  22. #define BYTES_PER_FUSE 4
  23. // otp reg offset
  24. #define OTP_CFGR 0x00
  25. #define OTPC_IER 0x04
  26. #define OTPC_SRR 0x08
  27. #define OTP_OPRR 0x0c
  28. #define OTPC_CTLR 0x10
  29. #define OTPC_ADDRR 0x14
  30. #define OTPC_DINR 0x18
  31. #define OTPC_DOUTR 0x1c
  32. #define OTP_MEM_START 0x800
  33. #define OTP_MEM_SIZE 0x800
  34. #define OTP_EMPTY_CELL_VALUE 0xffffffffUL
  35. // cfgr (offset 0x00)
  36. #define OTP_CFGR_PRG_CNT_MASK 0xff
  37. #define OTP_CFGR_PRG_CNT_SHIFT 0
  38. #define OTP_CFGR_DIV_1US_MASK 0xff
  39. #define OTP_CFGR_DIV_1US_SHIFT 8
  40. #define OTP_CFGR_RD_CYC_MASK 0x0f
  41. #define OTP_CFGR_RD_CYC_SHIFT 16
  42. // ier (offset 0x04)
  43. #define OTPC_IER_DONE_IE BIT(0)
  44. #define OTPC_IER_BUSY_OPR_IE BIT(1)
  45. // srr (offset 0x08)
  46. #define OTPC_SRR_DONE BIT(0)
  47. #define OTPC_SRR_BUSY_OPR BIT(1)
  48. #define OTPC_SRR_INFO_RD_LOCK BIT(29)
  49. #define OTPC_SRR_INFO_WR_LOCK BIT(30)
  50. #define OTPC_SRR_BUSY BIT(31)
  51. // oprr (offset 0x0c)
  52. #define OTP_OPRR_OPR_MASK 0x00000007
  53. #define OTP_OPRR_OPR_SHIFT 0
  54. #define OTP_OPR_STANDBY 0x0 // user mode
  55. #define OTP_OPR_READ 0x1 // user mode
  56. #define OTP_OPR_MARGIN_READ_PROG 0x2 // testing mode
  57. #define OTP_OPR_MARGIN_READ_INIT 0x3 // testing mode
  58. #define OTP_OPR_PROGRAM 0x4 // user mode
  59. #define OTP_OPR_DEEP_STANDBY 0x5 // user mode
  60. #define OTP_OPR_DEBUG 0x6 // user mode
  61. // ctlr (offset 0x10, see EG512X32TH028CW01_v1.0.pdf "Pin Description")
  62. #define OTPC_CTLR_PCE BIT(0)
  63. #define OTPC_CTLR_PTM_MASK 0x0000000e
  64. #define OTPC_CTLR_PTM_SHIFT 1
  65. #define OTPC_CTLR_PDSTB BIT(4)
  66. #define OTPC_CTLR_PTR BIT(5)
  67. #define OTPC_CTLR_PPROG BIT(6)
  68. #define OTPC_CTLR_PWE BIT(7)
  69. #define OTPC_CTLR_PCLK BIT(8)
  70. // addrr (offset 0x14)
  71. #define OTPC_ADDRR_PA_MASK 0x000001ff
  72. #define OTPC_ADDRR_PA_SHIFT 0
  73. /*
  74. data formate
  75. struct starfive_otp_data{
  76. char vendor[32];
  77. uint64_t sn;
  78. uint8_t mac_addr[6];
  79. uint8_t padding_0[2];
  80. }
  81. */
  82. #define STARFIVE_OTP_GPIO 56 /*control power*/
  83. struct starfive_otp_regs {
  84. /* TODO: add otp ememory_eg512x32 registers define */
  85. uint32_t otp_cfg; /*!< timing Register., Address offset = 0x00 */
  86. uint32_t otpc_ie; /*!< interrupt Enable Register., Address offset = 0x04 */
  87. uint32_t otpc_sr; /*!< status Register., Address offset = 0x08 */
  88. uint32_t otp_opr; /*!< operation mode select Register., Address offset = 0x0C */
  89. uint32_t otpc_ctl; /*!< otp control port, Address offset = 0x10 */
  90. uint32_t otpc_addr; /*!< otp pa port , Address offset = 0x14 */
  91. uint32_t otpc_din; /*!< otp pdin port, Address offset = 0x18 */
  92. uint32_t otpc_dout; /*!< otp pdout, Address offset = 0x1C */
  93. };
  94. struct starfive_otp_platdata {
  95. struct starfive_otp_regs __iomem *regs;
  96. u32 total_fuses;
  97. };
  98. static void gpio_direction_output(u32 gpio, u32 val)
  99. {
  100. volatile uint32_t __iomem *addr = EZGPIO_FULLMUX_BASE_ADDR + 0x50 +
  101. gpio * 8;
  102. MA_OUTW(addr, val);
  103. MA_OUTW(addr + 1, val);
  104. }
  105. static void gpio_set_value(u32 gpio, u32 val)
  106. {
  107. volatile uint32_t __iomem *addr = EZGPIO_FULLMUX_BASE_ADDR + 0x50 +
  108. gpio * 8;
  109. MA_OUTW(addr, val);
  110. }
  111. /*
  112. * offset and size are assumed aligned to the size of the fuses (32-bit).
  113. */
  114. static int starfive_otp_read(struct udevice *dev, int offset,
  115. void *buf, int size)
  116. {
  117. struct starfive_otp_platdata *plat = dev_get_plat(dev);
  118. struct starfive_otp_regs *regs = (struct starfive_otp_regs *)plat->regs;
  119. int fuseidx = offset / BYTES_PER_FUSE;
  120. int fusecount = size / BYTES_PER_FUSE;
  121. u32 fusebuf[fusecount];
  122. u32 addr = (u32)regs;
  123. /* Check if offset and size are multiple of BYTES_PER_FUSE */
  124. if ((size % BYTES_PER_FUSE) || (offset % BYTES_PER_FUSE)) {
  125. printf("%s: size and offset must be multiple of 4.\n",
  126. __func__);
  127. return -EINVAL;
  128. }
  129. /* check bounds */
  130. if (offset < 0 || size < 0)
  131. return -EINVAL;
  132. if (fuseidx >= plat->total_fuses)
  133. return -EINVAL;
  134. if ((fuseidx + fusecount) > plat->total_fuses)
  135. return -EINVAL;
  136. //otp power off and on
  137. gpio_direction_output(STARFIVE_OTP_GPIO, 0);
  138. mdelay(5);
  139. gpio_set_value(STARFIVE_OTP_GPIO, 1);
  140. mdelay(10);
  141. //otp set to read mode
  142. writel(OTP_OPR_READ, &regs->otp_opr);
  143. mdelay(5);
  144. /* read all requested fuses */
  145. for (unsigned int i = 0; i < fusecount; i++, fuseidx++) {
  146. /* read the value */
  147. fusebuf[i] = readl((volatile void __iomem *)
  148. (addr + OTP_MEM_START +
  149. fuseidx * BYTES_PER_FUSE));
  150. }
  151. //otp power off
  152. gpio_set_value(STARFIVE_OTP_GPIO, 0);
  153. mdelay(5);
  154. /* copy out */
  155. memcpy(buf, fusebuf, size);
  156. return size;
  157. }
  158. static int starfive_otp_ofdata_to_platdata(struct udevice *dev)
  159. {
  160. struct starfive_otp_platdata *plat = dev_get_plat(dev);
  161. int ret;
  162. plat->regs = dev_read_addr_ptr(dev);
  163. ret = dev_read_u32(dev, "fuse-count", &plat->total_fuses);
  164. if (ret < 0) {
  165. pr_err("\"fuse-count\" not found\n");
  166. return ret;
  167. }
  168. return 0;
  169. }
  170. static const struct misc_ops starfive_otp_ops = {
  171. .read = starfive_otp_read,
  172. };
  173. static const struct udevice_id sifive_otp_ids[] = {
  174. { .compatible = "starfive,fu740-otp" },
  175. { }
  176. };
  177. U_BOOT_DRIVER(starfive_otp) = {
  178. .name = "starfive_otp",
  179. .id = UCLASS_MISC,
  180. .of_match = sifive_otp_ids,
  181. .of_to_plat = starfive_otp_ofdata_to_platdata,
  182. .plat_auto = sizeof(struct starfive_otp_platdata),
  183. .ops = &starfive_otp_ops,
  184. };