Browse Source

freescale/powerpc: Rename the config CONFIG_SECURE_BOOT name

Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid
conflicts with UEFI secure boot.

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Udit Agarwal 4 years ago
parent
commit
bef1845404
56 changed files with 73 additions and 73 deletions
  1. 2 2
      arch/powerpc/cpu/mpc85xx/Kconfig
  2. 4 4
      arch/powerpc/cpu/mpc85xx/cpu_init.c
  3. 5 5
      arch/powerpc/cpu/mpc85xx/start.S
  4. 2 2
      arch/powerpc/cpu/mpc8xxx/law.c
  5. 2 2
      arch/powerpc/include/asm/fsl_secure_boot.h
  6. 1 1
      board/freescale/common/p_corenet/tlb.c
  7. 2 2
      board/freescale/t104xrdb/tlb.c
  8. 1 1
      configs/B4860QDS_SECURE_BOOT_defconfig
  9. 1 1
      configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
  10. 1 1
      configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
  11. 1 1
      configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
  12. 1 1
      configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
  13. 1 1
      configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
  14. 1 1
      configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
  15. 1 1
      configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
  16. 1 1
      configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
  17. 1 1
      configs/C29XPCIE_NOR_SECBOOT_defconfig
  18. 1 1
      configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
  19. 1 1
      configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
  20. 1 1
      configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
  21. 1 1
      configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
  22. 1 1
      configs/P1010RDB-PA_NAND_SECBOOT_defconfig
  23. 1 1
      configs/P1010RDB-PA_NOR_SECBOOT_defconfig
  24. 1 1
      configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
  25. 1 1
      configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
  26. 1 1
      configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
  27. 1 1
      configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
  28. 1 1
      configs/P1010RDB-PB_NAND_SECBOOT_defconfig
  29. 1 1
      configs/P1010RDB-PB_NOR_SECBOOT_defconfig
  30. 1 1
      configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
  31. 1 1
      configs/P2041RDB_SECURE_BOOT_defconfig
  32. 1 1
      configs/P3041DS_NAND_SECURE_BOOT_defconfig
  33. 1 1
      configs/P3041DS_SECURE_BOOT_defconfig
  34. 1 1
      configs/P4080DS_SECURE_BOOT_defconfig
  35. 1 1
      configs/P5020DS_NAND_SECURE_BOOT_defconfig
  36. 1 1
      configs/P5020DS_SECURE_BOOT_defconfig
  37. 1 1
      configs/P5040DS_NAND_SECURE_BOOT_defconfig
  38. 1 1
      configs/P5040DS_SECURE_BOOT_defconfig
  39. 1 1
      configs/T1023RDB_SECURE_BOOT_defconfig
  40. 1 1
      configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
  41. 1 1
      configs/T1024QDS_SECURE_BOOT_defconfig
  42. 1 1
      configs/T1024RDB_SECURE_BOOT_defconfig
  43. 1 1
      configs/T1040D4RDB_SECURE_BOOT_defconfig
  44. 1 1
      configs/T1040QDS_SECURE_BOOT_defconfig
  45. 1 1
      configs/T1040RDB_SECURE_BOOT_defconfig
  46. 1 1
      configs/T1042D4RDB_SECURE_BOOT_defconfig
  47. 1 1
      configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
  48. 1 1
      configs/T1042RDB_SECURE_BOOT_defconfig
  49. 1 1
      configs/T2080QDS_SECURE_BOOT_defconfig
  50. 1 1
      configs/T2080RDB_SECURE_BOOT_defconfig
  51. 1 1
      configs/T4160QDS_SECURE_BOOT_defconfig
  52. 1 1
      configs/T4240QDS_SECURE_BOOT_defconfig
  53. 4 4
      doc/README.mpc85xx
  54. 2 2
      include/configs/P1010RDB.h
  55. 3 3
      include/configs/T104xRDB.h
  56. 1 1
      include/configs/corenet_ds.h

+ 2 - 2
arch/powerpc/cpu/mpc85xx/Kconfig

@@ -1208,8 +1208,8 @@ config FSL_LAW
 	help
 		Use Freescale common code for Local Access Window
 
-config SECURE_BOOT
-	bool	"Secure Boot"
+config NXP_ESBC
+	bool	"NXP_ESBC"
 	help
 		Enable Freescale Secure Boot feature. Normally selected
 		by defconfig. If unsure, do not change.

+ 4 - 4
arch/powerpc/cpu/mpc85xx/cpu_init.c

@@ -38,7 +38,7 @@
 #ifdef CONFIG_FSL_CAAM
 #include <fsl_sec.h>
 #endif
-#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
 #include <asm/fsl_pamu.h>
 #include <fsl_secboot_err.h>
 #endif
@@ -440,7 +440,7 @@ ulong cpu_init_f(void)
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
-#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
 	struct law_entry law;
 #endif
 #ifdef CONFIG_ARCH_MPC8548
@@ -460,7 +460,7 @@ ulong cpu_init_f(void)
 	disable_tlb(14);
 	disable_tlb(15);
 
-#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
 	/* Disable the LAW created for NOR flash by the PBI commands */
 	law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
 	if (law.index != -1)
@@ -963,7 +963,7 @@ int cpu_init_r(void)
 	fman_enet_init();
 #endif
 
-#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
 	if (pamu_init() < 0)
 		fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
 #endif

+ 5 - 5
arch/powerpc/cpu/mpc85xx/start.S

@@ -33,7 +33,7 @@
 #endif
 
 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
-	!defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+	!defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define NOR_BOOT
 #endif
 
@@ -123,7 +123,7 @@ _start_e500:
 #endif
 
 
-#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \
+#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_E500MC) && \
 	!defined(CONFIG_E6500)
 	/* ISBC uses L2 as stack.
 	 * Disable L2 cache here so that u-boot can enable it later
@@ -467,7 +467,7 @@ nexti:	mflr	r1		/* R1 = our PC */
 	blt	1b
 
 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \
-	!defined(CONFIG_SECURE_BOOT)
+	!defined(CONFIG_NXP_ESBC)
 /*
  * TLB entry for debuggging in AS1
  * Create temporary TLB entry in AS0 to handle debug exception
@@ -1065,7 +1065,7 @@ create_init_ram_area:
 		0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
 		0, r6
 
-#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
+#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC)
 	/* create a temp mapping in AS = 1 for Flash mapping
 	 * created by PBL for ISBC code
 	 */
@@ -1080,7 +1080,7 @@ create_init_ram_area:
  * and for targets with CONFIG_SPL like T1, T2, T4, only for
  * u-boot-spl i.e. CONFIG_SPL_BUILD
  */
-#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT) && \
+#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_NXP_ESBC) && \
 	(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 	/* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE
 	 * to L3 Address configured by PBL for ISBC code

+ 2 - 2
arch/powerpc/cpu/mpc8xxx/law.c

@@ -259,7 +259,7 @@ void init_laws(void)
 #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
 #endif
 
-#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500) && \
+#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_E500) && \
 						!defined(CONFIG_E500MC)
 	/* ISBC (Boot ROM) creates a LAW 0 entry for non PBL platforms,
 	 * which is not disabled before transferring the control to uboot.
@@ -268,7 +268,7 @@ void init_laws(void)
 	disable_law(0);
 #endif
 
-#if !defined(CONFIG_SECURE_BOOT)
+#if !defined(CONFIG_NXP_ESBC)
 	/*
 	 * if any non DDR LAWs has been created earlier, remove them before
 	 * LAW table is parsed.

+ 2 - 2
arch/powerpc/include/asm/fsl_secure_boot.h

@@ -7,7 +7,7 @@
 #define __FSL_SECURE_BOOT_H
 #include <asm/config_mpc85xx.h>
 
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
 #if defined(CONFIG_FSL_CORENET)
 #define CONFIG_SYS_PBI_FLASH_BASE		0xc0000000
 #elif defined(CONFIG_TARGET_BSC9132QDS)
@@ -74,7 +74,7 @@
  */
 #define CONFIG_FSL_ISBC_KEY_EXT
 #endif
-#endif /* #ifdef CONFIG_SECURE_BOOT */
+#endif /* #ifdef CONFIG_NXP_ESBC */
 
 #ifdef CONFIG_CHAIN_OF_TRUST
 #ifdef CONFIG_SPL_BUILD

+ 1 - 1
board/freescale/common/p_corenet/tlb.c

@@ -43,7 +43,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	/* *I*** - Covers boot page */
 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
 
-#if !defined(CONFIG_SECURE_BOOT)
+#if !defined(CONFIG_NXP_ESBC)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
 	 * SRAM is at 0xfff00000, it covered the 0xfffff000.

+ 2 - 2
board/freescale/t104xrdb/tlb.c

@@ -28,7 +28,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
-	!defined(CONFIG_SECURE_BOOT)
+	!defined(CONFIG_NXP_ESBC)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
 	 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
@@ -37,7 +37,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_256K, 1),
 
-#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD)
+#elif defined(CONFIG_NXP_ESBC) && defined(CONFIG_SPL_BUILD)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot
 	 * the physical address of the SRAM is at 0xbffc0000,

+ 1 - 1
configs/B4860QDS_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_B4860QDS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x8FF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x8FF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_BSC9132QDS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/C29XPCIE_NOR_SECBOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_C29XPCIE=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_C29XPCIE=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P1010RDB-PA_NAND_SECBOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P1010RDB-PA_NOR_SECBOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PA=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P1010RDB-PB_NAND_SECBOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P1010RDB-PB_NOR_SECBOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P1010RDB_PB=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P2041RDB_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P2041RDB=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P3041DS_NAND_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P3041DS_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P3041DS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P4080DS_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P4080DS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P5020DS_NAND_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5020DS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P5020DS_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5020DS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P5040DS_NAND_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/P5040DS_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_P5040DS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/T1023RDB_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1023RDB=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/T1024QDS_DDR4_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024QDS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/T1024QDS_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024QDS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/T1024RDB_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/T1040D4RDB_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1040D4RDB=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/T1040QDS_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1040QDS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/T1040RDB_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1040RDB=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/T1042D4RDB_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig

@@ -2,7 +2,7 @@ CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0x30001000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y

+ 1 - 1
configs/T1042RDB_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042RDB=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/T2080QDS_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y

+ 1 - 1
configs/T2080RDB_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/T4160QDS_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4160QDS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 1 - 1
configs/T4240QDS_SECURE_BOOT_defconfig

@@ -1,6 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SECURE_BOOT=y
+CONFIG_NXP_ESBC=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240QDS=y
 # CONFIG_SYS_MALLOC_F is not set

+ 4 - 4
doc/README.mpc85xx

@@ -28,11 +28,11 @@ Major Config Switches during various boot Modes
 NOR boot
 		!defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
 NOR boot Secure
-		!defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
+		!defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC)
 RAMBOOT(SD, SPI & NAND boot)
 		 defined(CONFIG_SYS_RAMBOOT)
 RAMBOOT Secure (SD, SPI & NAND)
-		 defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
+		 defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC)
 NAND SPL BOOT
 		 defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL)
 
@@ -93,7 +93,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
    1) TLB entry to overcome e500 v1/v2 debug restriction
        Location	  : Label "_start_e500"
        TLB Entry  : CONFIG_SYS_PPC_E500_DEBUG_TLB
-#if defined(CONFIG_SECURE_BOOT)
+#if defined(CONFIG_NXP_ESBC)
        EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
        Properties : 1M, AS1, I, G, IPROT
 #else
@@ -104,7 +104,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
    2) TLB entry for working in AS1
        Location	  : Label "create_init_ram_area"
        TLB Entry  : 15
-#if defined(CONFIG_SECURE_BOOT)
+#if defined(CONFIG_NXP_ESBC)
        EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
        Properties : 1M, AS1, I, G, IPROT
 #else

+ 2 - 2
include/configs/P1010RDB.h

@@ -29,7 +29,7 @@
 #endif
 
 #ifdef CONFIG_SPIFLASH
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
 #define CONFIG_RAMBOOT_SPIFLASH
 #define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
 #else
@@ -50,7 +50,7 @@
 #endif
 
 #ifdef CONFIG_NAND
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"

+ 3 - 3
include/configs/T104xRDB.h

@@ -13,7 +13,7 @@
 
 #ifdef CONFIG_RAMBOOT_PBL
 
-#ifndef CONFIG_SECURE_BOOT
+#ifndef CONFIG_NXP_ESBC
 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
 #else
 #define CONFIG_SYS_FSL_PBL_PBI \
@@ -32,7 +32,7 @@
 #define BOOT_PAGE_OFFSET		0x27000
 
 #ifdef CONFIG_NAND
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
 #define CONFIG_U_BOOT_HDR_SIZE		(16 << 10)
 /*
  * HDR would be appended at end of image and copied to DDR along
@@ -163,7 +163,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 #define CONFIG_ENV_SIZE			0x2000
 #define CONFIG_ENV_OFFSET		(512 * 0x800)
 #elif defined(CONFIG_NAND)
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
 #define CONFIG_RAMBOOT_NAND
 #define CONFIG_BOOTSCRIPT_COPY_RAM
 #endif

+ 1 - 1
include/configs/corenet_ds.h

@@ -12,7 +12,7 @@
 #include "../board/freescale/common/ics307_clk.h"
 
 #ifdef CONFIG_RAMBOOT_PBL
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
 #ifdef CONFIG_NAND