Kconfig 34 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628
  1. menu "mpc85xx CPU"
  2. depends on MPC85xx
  3. config SYS_CPU
  4. default "mpc85xx"
  5. config CMD_ERRATA
  6. bool "Enable the 'errata' command"
  7. depends on MPC85xx
  8. default y
  9. help
  10. This enables the 'errata' command which displays a list of errata
  11. work-arounds which are enabled for the current board.
  12. choice
  13. prompt "Target select"
  14. optional
  15. config TARGET_SBC8548
  16. bool "Support sbc8548"
  17. select ARCH_MPC8548
  18. config TARGET_SOCRATES
  19. bool "Support socrates"
  20. select ARCH_MPC8544
  21. config TARGET_B4420QDS
  22. bool "Support B4420QDS"
  23. select ARCH_B4420
  24. select SUPPORT_SPL
  25. select PHYS_64BIT
  26. imply PANIC_HANG
  27. config TARGET_B4860QDS
  28. bool "Support B4860QDS"
  29. select ARCH_B4860
  30. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  31. select SUPPORT_SPL
  32. select PHYS_64BIT
  33. select FSL_DDR_INTERACTIVE if !SPL_BUILD
  34. imply PANIC_HANG
  35. config TARGET_BSC9131RDB
  36. bool "Support BSC9131RDB"
  37. select ARCH_BSC9131
  38. select SUPPORT_SPL
  39. select BOARD_EARLY_INIT_F
  40. config TARGET_BSC9132QDS
  41. bool "Support BSC9132QDS"
  42. select ARCH_BSC9132
  43. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  44. select SUPPORT_SPL
  45. select BOARD_EARLY_INIT_F
  46. select FSL_DDR_INTERACTIVE
  47. config TARGET_C29XPCIE
  48. bool "Support C29XPCIE"
  49. select ARCH_C29X
  50. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  51. select SUPPORT_SPL
  52. select SUPPORT_TPL
  53. select PHYS_64BIT
  54. imply PANIC_HANG
  55. config TARGET_P3041DS
  56. bool "Support P3041DS"
  57. select PHYS_64BIT
  58. select ARCH_P3041
  59. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  60. imply CMD_SATA
  61. imply PANIC_HANG
  62. config TARGET_P4080DS
  63. bool "Support P4080DS"
  64. select PHYS_64BIT
  65. select ARCH_P4080
  66. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  67. imply CMD_SATA
  68. imply PANIC_HANG
  69. config TARGET_P5020DS
  70. bool "Support P5020DS"
  71. select PHYS_64BIT
  72. select ARCH_P5020
  73. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  74. imply CMD_SATA
  75. imply PANIC_HANG
  76. config TARGET_P5040DS
  77. bool "Support P5040DS"
  78. select PHYS_64BIT
  79. select ARCH_P5040
  80. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  81. imply CMD_SATA
  82. imply PANIC_HANG
  83. config TARGET_MPC8536DS
  84. bool "Support MPC8536DS"
  85. select ARCH_MPC8536
  86. # Use DDR3 controller with DDR2 DIMMs on this board
  87. select SYS_FSL_DDRC_GEN3
  88. imply CMD_SATA
  89. imply FSL_SATA
  90. config TARGET_MPC8541CDS
  91. bool "Support MPC8541CDS"
  92. select ARCH_MPC8541
  93. config TARGET_MPC8544DS
  94. bool "Support MPC8544DS"
  95. select ARCH_MPC8544
  96. imply PANIC_HANG
  97. config TARGET_MPC8548CDS
  98. bool "Support MPC8548CDS"
  99. select ARCH_MPC8548
  100. config TARGET_MPC8555CDS
  101. bool "Support MPC8555CDS"
  102. select ARCH_MPC8555
  103. config TARGET_MPC8568MDS
  104. bool "Support MPC8568MDS"
  105. select ARCH_MPC8568
  106. config TARGET_MPC8569MDS
  107. bool "Support MPC8569MDS"
  108. select ARCH_MPC8569
  109. config TARGET_MPC8572DS
  110. bool "Support MPC8572DS"
  111. select ARCH_MPC8572
  112. # Use DDR3 controller with DDR2 DIMMs on this board
  113. select SYS_FSL_DDRC_GEN3
  114. imply SCSI
  115. imply PANIC_HANG
  116. config TARGET_P1010RDB_PA
  117. bool "Support P1010RDB_PA"
  118. select ARCH_P1010
  119. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  120. select SUPPORT_SPL
  121. select SUPPORT_TPL
  122. imply CMD_EEPROM
  123. imply CMD_SATA
  124. imply PANIC_HANG
  125. config TARGET_P1010RDB_PB
  126. bool "Support P1010RDB_PB"
  127. select ARCH_P1010
  128. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  129. select SUPPORT_SPL
  130. select SUPPORT_TPL
  131. imply CMD_EEPROM
  132. imply CMD_SATA
  133. imply PANIC_HANG
  134. config TARGET_P1022DS
  135. bool "Support P1022DS"
  136. select ARCH_P1022
  137. select SUPPORT_SPL
  138. select SUPPORT_TPL
  139. imply CMD_SATA
  140. imply FSL_SATA
  141. config TARGET_P1023RDB
  142. bool "Support P1023RDB"
  143. select ARCH_P1023
  144. select FSL_DDR_INTERACTIVE
  145. imply CMD_EEPROM
  146. imply PANIC_HANG
  147. config TARGET_P1020MBG
  148. bool "Support P1020MBG-PC"
  149. select SUPPORT_SPL
  150. select SUPPORT_TPL
  151. select ARCH_P1020
  152. imply CMD_EEPROM
  153. imply CMD_SATA
  154. imply PANIC_HANG
  155. config TARGET_P1020RDB_PC
  156. bool "Support P1020RDB-PC"
  157. select SUPPORT_SPL
  158. select SUPPORT_TPL
  159. select ARCH_P1020
  160. imply CMD_EEPROM
  161. imply CMD_SATA
  162. imply PANIC_HANG
  163. config TARGET_P1020RDB_PD
  164. bool "Support P1020RDB-PD"
  165. select SUPPORT_SPL
  166. select SUPPORT_TPL
  167. select ARCH_P1020
  168. imply CMD_EEPROM
  169. imply CMD_SATA
  170. imply PANIC_HANG
  171. config TARGET_P1020UTM
  172. bool "Support P1020UTM"
  173. select SUPPORT_SPL
  174. select SUPPORT_TPL
  175. select ARCH_P1020
  176. imply CMD_EEPROM
  177. imply CMD_SATA
  178. imply PANIC_HANG
  179. config TARGET_P1021RDB
  180. bool "Support P1021RDB"
  181. select SUPPORT_SPL
  182. select SUPPORT_TPL
  183. select ARCH_P1021
  184. imply CMD_EEPROM
  185. imply CMD_SATA
  186. imply PANIC_HANG
  187. config TARGET_P1024RDB
  188. bool "Support P1024RDB"
  189. select SUPPORT_SPL
  190. select SUPPORT_TPL
  191. select ARCH_P1024
  192. imply CMD_EEPROM
  193. imply CMD_SATA
  194. imply PANIC_HANG
  195. config TARGET_P1025RDB
  196. bool "Support P1025RDB"
  197. select SUPPORT_SPL
  198. select SUPPORT_TPL
  199. select ARCH_P1025
  200. imply CMD_EEPROM
  201. imply CMD_SATA
  202. imply SATA_SIL
  203. config TARGET_P2020RDB
  204. bool "Support P2020RDB-PC"
  205. select SUPPORT_SPL
  206. select SUPPORT_TPL
  207. select ARCH_P2020
  208. imply CMD_EEPROM
  209. imply CMD_SATA
  210. imply SATA_SIL
  211. config TARGET_P1_TWR
  212. bool "Support p1_twr"
  213. select ARCH_P1025
  214. config TARGET_P2041RDB
  215. bool "Support P2041RDB"
  216. select ARCH_P2041
  217. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  218. select PHYS_64BIT
  219. imply CMD_SATA
  220. imply FSL_SATA
  221. config TARGET_QEMU_PPCE500
  222. bool "Support qemu-ppce500"
  223. select ARCH_QEMU_E500
  224. select PHYS_64BIT
  225. config TARGET_T1024QDS
  226. bool "Support T1024QDS"
  227. select ARCH_T1024
  228. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  229. select SUPPORT_SPL
  230. select PHYS_64BIT
  231. imply CMD_EEPROM
  232. imply CMD_SATA
  233. imply FSL_SATA
  234. config TARGET_T1023RDB
  235. bool "Support T1023RDB"
  236. select ARCH_T1023
  237. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  238. select SUPPORT_SPL
  239. select PHYS_64BIT
  240. select FSL_DDR_INTERACTIVE
  241. imply CMD_EEPROM
  242. imply PANIC_HANG
  243. config TARGET_T1024RDB
  244. bool "Support T1024RDB"
  245. select ARCH_T1024
  246. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  247. select SUPPORT_SPL
  248. select PHYS_64BIT
  249. select FSL_DDR_INTERACTIVE
  250. imply CMD_EEPROM
  251. imply PANIC_HANG
  252. config TARGET_T1040QDS
  253. bool "Support T1040QDS"
  254. select ARCH_T1040
  255. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  256. select PHYS_64BIT
  257. select FSL_DDR_INTERACTIVE
  258. imply CMD_EEPROM
  259. imply CMD_SATA
  260. imply PANIC_HANG
  261. config TARGET_T1040RDB
  262. bool "Support T1040RDB"
  263. select ARCH_T1040
  264. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  265. select SUPPORT_SPL
  266. select PHYS_64BIT
  267. imply CMD_SATA
  268. imply PANIC_HANG
  269. config TARGET_T1040D4RDB
  270. bool "Support T1040D4RDB"
  271. select ARCH_T1040
  272. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  273. select SUPPORT_SPL
  274. select PHYS_64BIT
  275. imply CMD_SATA
  276. imply PANIC_HANG
  277. config TARGET_T1042RDB
  278. bool "Support T1042RDB"
  279. select ARCH_T1042
  280. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  281. select SUPPORT_SPL
  282. select PHYS_64BIT
  283. imply CMD_SATA
  284. config TARGET_T1042D4RDB
  285. bool "Support T1042D4RDB"
  286. select ARCH_T1042
  287. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  288. select SUPPORT_SPL
  289. select PHYS_64BIT
  290. imply CMD_SATA
  291. imply PANIC_HANG
  292. config TARGET_T1042RDB_PI
  293. bool "Support T1042RDB_PI"
  294. select ARCH_T1042
  295. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  296. select SUPPORT_SPL
  297. select PHYS_64BIT
  298. imply CMD_SATA
  299. imply PANIC_HANG
  300. config TARGET_T2080QDS
  301. bool "Support T2080QDS"
  302. select ARCH_T2080
  303. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  304. select SUPPORT_SPL
  305. select PHYS_64BIT
  306. select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  307. select FSL_DDR_INTERACTIVE
  308. config TARGET_T2080RDB
  309. bool "Support T2080RDB"
  310. select ARCH_T2080
  311. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  312. select SUPPORT_SPL
  313. select PHYS_64BIT
  314. imply CMD_SATA
  315. imply FSL_SATA
  316. imply PANIC_HANG
  317. config TARGET_T2081QDS
  318. bool "Support T2081QDS"
  319. select ARCH_T2081
  320. select SUPPORT_SPL
  321. select PHYS_64BIT
  322. select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  323. select FSL_DDR_INTERACTIVE
  324. config TARGET_T4160QDS
  325. bool "Support T4160QDS"
  326. select ARCH_T4160
  327. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  328. select SUPPORT_SPL
  329. select PHYS_64BIT
  330. imply CMD_SATA
  331. imply PANIC_HANG
  332. config TARGET_T4160RDB
  333. bool "Support T4160RDB"
  334. select ARCH_T4160
  335. select SUPPORT_SPL
  336. select PHYS_64BIT
  337. imply PANIC_HANG
  338. config TARGET_T4240QDS
  339. bool "Support T4240QDS"
  340. select ARCH_T4240
  341. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  342. select SUPPORT_SPL
  343. select PHYS_64BIT
  344. select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  345. imply CMD_SATA
  346. imply PANIC_HANG
  347. config TARGET_T4240RDB
  348. bool "Support T4240RDB"
  349. select ARCH_T4240
  350. select SUPPORT_SPL
  351. select PHYS_64BIT
  352. select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  353. imply CMD_SATA
  354. imply PANIC_HANG
  355. config TARGET_CONTROLCENTERD
  356. bool "Support controlcenterd"
  357. select ARCH_P1022
  358. config TARGET_KMP204X
  359. bool "Support kmp204x"
  360. select VENDOR_KM
  361. config TARGET_XPEDITE520X
  362. bool "Support xpedite520x"
  363. select ARCH_MPC8548
  364. config TARGET_XPEDITE537X
  365. bool "Support xpedite537x"
  366. select ARCH_MPC8572
  367. # Use DDR3 controller with DDR2 DIMMs on this board
  368. select SYS_FSL_DDRC_GEN3
  369. config TARGET_XPEDITE550X
  370. bool "Support xpedite550x"
  371. select ARCH_P2020
  372. config TARGET_UCP1020
  373. bool "Support uCP1020"
  374. select ARCH_P1020
  375. imply CMD_SATA
  376. imply PANIC_HANG
  377. config TARGET_CYRUS_P5020
  378. bool "Support Varisys Cyrus P5020"
  379. select ARCH_P5020
  380. select PHYS_64BIT
  381. imply PANIC_HANG
  382. config TARGET_CYRUS_P5040
  383. bool "Support Varisys Cyrus P5040"
  384. select ARCH_P5040
  385. select PHYS_64BIT
  386. imply PANIC_HANG
  387. endchoice
  388. config ARCH_B4420
  389. bool
  390. select E500MC
  391. select E6500
  392. select FSL_LAW
  393. select SYS_FSL_DDR_VER_47
  394. select SYS_FSL_ERRATUM_A004477
  395. select SYS_FSL_ERRATUM_A005871
  396. select SYS_FSL_ERRATUM_A006379
  397. select SYS_FSL_ERRATUM_A006384
  398. select SYS_FSL_ERRATUM_A006475
  399. select SYS_FSL_ERRATUM_A006593
  400. select SYS_FSL_ERRATUM_A007075
  401. select SYS_FSL_ERRATUM_A007186
  402. select SYS_FSL_ERRATUM_A007212
  403. select SYS_FSL_ERRATUM_A009942
  404. select SYS_FSL_HAS_DDR3
  405. select SYS_FSL_HAS_SEC
  406. select SYS_FSL_QORIQ_CHASSIS2
  407. select SYS_FSL_SEC_BE
  408. select SYS_FSL_SEC_COMPAT_4
  409. select SYS_PPC64
  410. select FSL_IFC
  411. imply CMD_EEPROM
  412. imply CMD_NAND
  413. imply CMD_REGINFO
  414. config ARCH_B4860
  415. bool
  416. select E500MC
  417. select E6500
  418. select FSL_LAW
  419. select SYS_FSL_DDR_VER_47
  420. select SYS_FSL_ERRATUM_A004477
  421. select SYS_FSL_ERRATUM_A005871
  422. select SYS_FSL_ERRATUM_A006379
  423. select SYS_FSL_ERRATUM_A006384
  424. select SYS_FSL_ERRATUM_A006475
  425. select SYS_FSL_ERRATUM_A006593
  426. select SYS_FSL_ERRATUM_A007075
  427. select SYS_FSL_ERRATUM_A007186
  428. select SYS_FSL_ERRATUM_A007212
  429. select SYS_FSL_ERRATUM_A007907
  430. select SYS_FSL_ERRATUM_A009942
  431. select SYS_FSL_HAS_DDR3
  432. select SYS_FSL_HAS_SEC
  433. select SYS_FSL_QORIQ_CHASSIS2
  434. select SYS_FSL_SEC_BE
  435. select SYS_FSL_SEC_COMPAT_4
  436. select SYS_PPC64
  437. select FSL_IFC
  438. imply CMD_EEPROM
  439. imply CMD_NAND
  440. imply CMD_REGINFO
  441. config ARCH_BSC9131
  442. bool
  443. select FSL_LAW
  444. select SYS_FSL_DDR_VER_44
  445. select SYS_FSL_ERRATUM_A004477
  446. select SYS_FSL_ERRATUM_A005125
  447. select SYS_FSL_ERRATUM_ESDHC111
  448. select SYS_FSL_HAS_DDR3
  449. select SYS_FSL_HAS_SEC
  450. select SYS_FSL_SEC_BE
  451. select SYS_FSL_SEC_COMPAT_4
  452. select FSL_IFC
  453. imply CMD_EEPROM
  454. imply CMD_NAND
  455. imply CMD_REGINFO
  456. config ARCH_BSC9132
  457. bool
  458. select FSL_LAW
  459. select SYS_FSL_DDR_VER_46
  460. select SYS_FSL_ERRATUM_A004477
  461. select SYS_FSL_ERRATUM_A005125
  462. select SYS_FSL_ERRATUM_A005434
  463. select SYS_FSL_ERRATUM_ESDHC111
  464. select SYS_FSL_ERRATUM_I2C_A004447
  465. select SYS_FSL_ERRATUM_IFC_A002769
  466. select FSL_PCIE_RESET
  467. select SYS_FSL_HAS_DDR3
  468. select SYS_FSL_HAS_SEC
  469. select SYS_FSL_SEC_BE
  470. select SYS_FSL_SEC_COMPAT_4
  471. select SYS_PPC_E500_USE_DEBUG_TLB
  472. select FSL_IFC
  473. imply CMD_EEPROM
  474. imply CMD_MTDPARTS
  475. imply CMD_NAND
  476. imply CMD_PCI
  477. imply CMD_REGINFO
  478. config ARCH_C29X
  479. bool
  480. select FSL_LAW
  481. select SYS_FSL_DDR_VER_46
  482. select SYS_FSL_ERRATUM_A005125
  483. select SYS_FSL_ERRATUM_ESDHC111
  484. select FSL_PCIE_RESET
  485. select SYS_FSL_HAS_DDR3
  486. select SYS_FSL_HAS_SEC
  487. select SYS_FSL_SEC_BE
  488. select SYS_FSL_SEC_COMPAT_6
  489. select SYS_PPC_E500_USE_DEBUG_TLB
  490. select FSL_IFC
  491. imply CMD_NAND
  492. imply CMD_PCI
  493. imply CMD_REGINFO
  494. config ARCH_MPC8536
  495. bool
  496. select FSL_LAW
  497. select SYS_FSL_ERRATUM_A004508
  498. select SYS_FSL_ERRATUM_A005125
  499. select FSL_PCIE_RESET
  500. select SYS_FSL_HAS_DDR2
  501. select SYS_FSL_HAS_DDR3
  502. select SYS_FSL_HAS_SEC
  503. select SYS_FSL_SEC_BE
  504. select SYS_FSL_SEC_COMPAT_2
  505. select SYS_PPC_E500_USE_DEBUG_TLB
  506. select FSL_ELBC
  507. imply CMD_NAND
  508. imply CMD_SATA
  509. imply CMD_REGINFO
  510. config ARCH_MPC8540
  511. bool
  512. select FSL_LAW
  513. select SYS_FSL_HAS_DDR1
  514. config ARCH_MPC8541
  515. bool
  516. select FSL_LAW
  517. select SYS_FSL_HAS_DDR1
  518. select SYS_FSL_HAS_SEC
  519. select SYS_FSL_SEC_BE
  520. select SYS_FSL_SEC_COMPAT_2
  521. config ARCH_MPC8544
  522. bool
  523. select FSL_LAW
  524. select SYS_FSL_ERRATUM_A005125
  525. select FSL_PCIE_RESET
  526. select SYS_FSL_HAS_DDR2
  527. select SYS_FSL_HAS_SEC
  528. select SYS_FSL_SEC_BE
  529. select SYS_FSL_SEC_COMPAT_2
  530. select SYS_PPC_E500_USE_DEBUG_TLB
  531. select FSL_ELBC
  532. config ARCH_MPC8548
  533. bool
  534. select FSL_LAW
  535. select SYS_FSL_ERRATUM_A005125
  536. select SYS_FSL_ERRATUM_NMG_DDR120
  537. select SYS_FSL_ERRATUM_NMG_LBC103
  538. select SYS_FSL_ERRATUM_NMG_ETSEC129
  539. select SYS_FSL_ERRATUM_I2C_A004447
  540. select FSL_PCIE_RESET
  541. select SYS_FSL_HAS_DDR2
  542. select SYS_FSL_HAS_DDR1
  543. select SYS_FSL_HAS_SEC
  544. select SYS_FSL_SEC_BE
  545. select SYS_FSL_SEC_COMPAT_2
  546. select SYS_PPC_E500_USE_DEBUG_TLB
  547. imply CMD_REGINFO
  548. config ARCH_MPC8555
  549. bool
  550. select FSL_LAW
  551. select SYS_FSL_HAS_DDR1
  552. select SYS_FSL_HAS_SEC
  553. select SYS_FSL_SEC_BE
  554. select SYS_FSL_SEC_COMPAT_2
  555. config ARCH_MPC8560
  556. bool
  557. select FSL_LAW
  558. select SYS_FSL_HAS_DDR1
  559. config ARCH_MPC8568
  560. bool
  561. select FSL_LAW
  562. select FSL_PCIE_RESET
  563. select SYS_FSL_HAS_DDR2
  564. select SYS_FSL_HAS_SEC
  565. select SYS_FSL_SEC_BE
  566. select SYS_FSL_SEC_COMPAT_2
  567. config ARCH_MPC8569
  568. bool
  569. select FSL_LAW
  570. select SYS_FSL_ERRATUM_A004508
  571. select SYS_FSL_ERRATUM_A005125
  572. select FSL_PCIE_RESET
  573. select SYS_FSL_HAS_DDR3
  574. select SYS_FSL_HAS_SEC
  575. select SYS_FSL_SEC_BE
  576. select SYS_FSL_SEC_COMPAT_2
  577. select FSL_ELBC
  578. imply CMD_NAND
  579. config ARCH_MPC8572
  580. bool
  581. select FSL_LAW
  582. select SYS_FSL_ERRATUM_A004508
  583. select SYS_FSL_ERRATUM_A005125
  584. select SYS_FSL_ERRATUM_DDR_115
  585. select SYS_FSL_ERRATUM_DDR111_DDR134
  586. select FSL_PCIE_RESET
  587. select SYS_FSL_HAS_DDR2
  588. select SYS_FSL_HAS_DDR3
  589. select SYS_FSL_HAS_SEC
  590. select SYS_FSL_SEC_BE
  591. select SYS_FSL_SEC_COMPAT_2
  592. select SYS_PPC_E500_USE_DEBUG_TLB
  593. select FSL_ELBC
  594. imply CMD_NAND
  595. config ARCH_P1010
  596. bool
  597. select FSL_LAW
  598. select SYS_FSL_ERRATUM_A004477
  599. select SYS_FSL_ERRATUM_A004508
  600. select SYS_FSL_ERRATUM_A005125
  601. select SYS_FSL_ERRATUM_A005275
  602. select SYS_FSL_ERRATUM_A006261
  603. select SYS_FSL_ERRATUM_A007075
  604. select SYS_FSL_ERRATUM_ESDHC111
  605. select SYS_FSL_ERRATUM_I2C_A004447
  606. select SYS_FSL_ERRATUM_IFC_A002769
  607. select SYS_FSL_ERRATUM_P1010_A003549
  608. select SYS_FSL_ERRATUM_SEC_A003571
  609. select SYS_FSL_ERRATUM_IFC_A003399
  610. select FSL_PCIE_RESET
  611. select SYS_FSL_HAS_DDR3
  612. select SYS_FSL_HAS_SEC
  613. select SYS_FSL_SEC_BE
  614. select SYS_FSL_SEC_COMPAT_4
  615. select SYS_PPC_E500_USE_DEBUG_TLB
  616. select FSL_IFC
  617. imply CMD_EEPROM
  618. imply CMD_MTDPARTS
  619. imply CMD_NAND
  620. imply CMD_SATA
  621. imply CMD_PCI
  622. imply CMD_REGINFO
  623. imply FSL_SATA
  624. config ARCH_P1011
  625. bool
  626. select FSL_LAW
  627. select SYS_FSL_ERRATUM_A004508
  628. select SYS_FSL_ERRATUM_A005125
  629. select SYS_FSL_ERRATUM_ELBC_A001
  630. select SYS_FSL_ERRATUM_ESDHC111
  631. select FSL_PCIE_DISABLE_ASPM
  632. select SYS_FSL_HAS_DDR3
  633. select SYS_FSL_HAS_SEC
  634. select SYS_FSL_SEC_BE
  635. select SYS_FSL_SEC_COMPAT_2
  636. select SYS_PPC_E500_USE_DEBUG_TLB
  637. select FSL_ELBC
  638. config ARCH_P1020
  639. bool
  640. select FSL_LAW
  641. select SYS_FSL_ERRATUM_A004508
  642. select SYS_FSL_ERRATUM_A005125
  643. select SYS_FSL_ERRATUM_ELBC_A001
  644. select SYS_FSL_ERRATUM_ESDHC111
  645. select FSL_PCIE_DISABLE_ASPM
  646. select FSL_PCIE_RESET
  647. select SYS_FSL_HAS_DDR3
  648. select SYS_FSL_HAS_SEC
  649. select SYS_FSL_SEC_BE
  650. select SYS_FSL_SEC_COMPAT_2
  651. select SYS_PPC_E500_USE_DEBUG_TLB
  652. select FSL_ELBC
  653. imply CMD_NAND
  654. imply CMD_SATA
  655. imply CMD_PCI
  656. imply CMD_REGINFO
  657. imply SATA_SIL
  658. config ARCH_P1021
  659. bool
  660. select FSL_LAW
  661. select SYS_FSL_ERRATUM_A004508
  662. select SYS_FSL_ERRATUM_A005125
  663. select SYS_FSL_ERRATUM_ELBC_A001
  664. select SYS_FSL_ERRATUM_ESDHC111
  665. select FSL_PCIE_DISABLE_ASPM
  666. select FSL_PCIE_RESET
  667. select SYS_FSL_HAS_DDR3
  668. select SYS_FSL_HAS_SEC
  669. select SYS_FSL_SEC_BE
  670. select SYS_FSL_SEC_COMPAT_2
  671. select SYS_PPC_E500_USE_DEBUG_TLB
  672. select FSL_ELBC
  673. imply CMD_REGINFO
  674. imply CMD_NAND
  675. imply CMD_SATA
  676. imply CMD_REGINFO
  677. imply SATA_SIL
  678. config ARCH_P1022
  679. bool
  680. select FSL_LAW
  681. select SYS_FSL_ERRATUM_A004477
  682. select SYS_FSL_ERRATUM_A004508
  683. select SYS_FSL_ERRATUM_A005125
  684. select SYS_FSL_ERRATUM_ELBC_A001
  685. select SYS_FSL_ERRATUM_ESDHC111
  686. select SYS_FSL_ERRATUM_SATA_A001
  687. select FSL_PCIE_RESET
  688. select SYS_FSL_HAS_DDR3
  689. select SYS_FSL_HAS_SEC
  690. select SYS_FSL_SEC_BE
  691. select SYS_FSL_SEC_COMPAT_2
  692. select SYS_PPC_E500_USE_DEBUG_TLB
  693. select FSL_ELBC
  694. config ARCH_P1023
  695. bool
  696. select FSL_LAW
  697. select SYS_FSL_ERRATUM_A004508
  698. select SYS_FSL_ERRATUM_A005125
  699. select SYS_FSL_ERRATUM_I2C_A004447
  700. select FSL_PCIE_RESET
  701. select SYS_FSL_HAS_DDR3
  702. select SYS_FSL_HAS_SEC
  703. select SYS_FSL_SEC_BE
  704. select SYS_FSL_SEC_COMPAT_4
  705. select FSL_ELBC
  706. config ARCH_P1024
  707. bool
  708. select FSL_LAW
  709. select SYS_FSL_ERRATUM_A004508
  710. select SYS_FSL_ERRATUM_A005125
  711. select SYS_FSL_ERRATUM_ELBC_A001
  712. select SYS_FSL_ERRATUM_ESDHC111
  713. select FSL_PCIE_DISABLE_ASPM
  714. select FSL_PCIE_RESET
  715. select SYS_FSL_HAS_DDR3
  716. select SYS_FSL_HAS_SEC
  717. select SYS_FSL_SEC_BE
  718. select SYS_FSL_SEC_COMPAT_2
  719. select SYS_PPC_E500_USE_DEBUG_TLB
  720. select FSL_ELBC
  721. imply CMD_EEPROM
  722. imply CMD_NAND
  723. imply CMD_SATA
  724. imply CMD_PCI
  725. imply CMD_REGINFO
  726. imply SATA_SIL
  727. config ARCH_P1025
  728. bool
  729. select FSL_LAW
  730. select SYS_FSL_ERRATUM_A004508
  731. select SYS_FSL_ERRATUM_A005125
  732. select SYS_FSL_ERRATUM_ELBC_A001
  733. select SYS_FSL_ERRATUM_ESDHC111
  734. select FSL_PCIE_DISABLE_ASPM
  735. select FSL_PCIE_RESET
  736. select SYS_FSL_HAS_DDR3
  737. select SYS_FSL_HAS_SEC
  738. select SYS_FSL_SEC_BE
  739. select SYS_FSL_SEC_COMPAT_2
  740. select SYS_PPC_E500_USE_DEBUG_TLB
  741. select FSL_ELBC
  742. imply CMD_SATA
  743. imply CMD_REGINFO
  744. config ARCH_P2020
  745. bool
  746. select FSL_LAW
  747. select SYS_FSL_ERRATUM_A004477
  748. select SYS_FSL_ERRATUM_A004508
  749. select SYS_FSL_ERRATUM_A005125
  750. select SYS_FSL_ERRATUM_ESDHC111
  751. select SYS_FSL_ERRATUM_ESDHC_A001
  752. select FSL_PCIE_RESET
  753. select SYS_FSL_HAS_DDR3
  754. select SYS_FSL_HAS_SEC
  755. select SYS_FSL_SEC_BE
  756. select SYS_FSL_SEC_COMPAT_2
  757. select SYS_PPC_E500_USE_DEBUG_TLB
  758. select FSL_ELBC
  759. imply CMD_EEPROM
  760. imply CMD_NAND
  761. imply CMD_REGINFO
  762. config ARCH_P2041
  763. bool
  764. select E500MC
  765. select FSL_LAW
  766. select SYS_FSL_ERRATUM_A004510
  767. select SYS_FSL_ERRATUM_A004849
  768. select SYS_FSL_ERRATUM_A005275
  769. select SYS_FSL_ERRATUM_A006261
  770. select SYS_FSL_ERRATUM_CPU_A003999
  771. select SYS_FSL_ERRATUM_DDR_A003
  772. select SYS_FSL_ERRATUM_DDR_A003474
  773. select SYS_FSL_ERRATUM_ESDHC111
  774. select SYS_FSL_ERRATUM_I2C_A004447
  775. select SYS_FSL_ERRATUM_NMG_CPU_A011
  776. select SYS_FSL_ERRATUM_SRIO_A004034
  777. select SYS_FSL_ERRATUM_USB14
  778. select SYS_FSL_HAS_DDR3
  779. select SYS_FSL_HAS_SEC
  780. select SYS_FSL_QORIQ_CHASSIS1
  781. select SYS_FSL_SEC_BE
  782. select SYS_FSL_SEC_COMPAT_4
  783. select FSL_ELBC
  784. imply CMD_NAND
  785. config ARCH_P3041
  786. bool
  787. select E500MC
  788. select FSL_LAW
  789. select SYS_FSL_DDR_VER_44
  790. select SYS_FSL_ERRATUM_A004510
  791. select SYS_FSL_ERRATUM_A004849
  792. select SYS_FSL_ERRATUM_A005275
  793. select SYS_FSL_ERRATUM_A005812
  794. select SYS_FSL_ERRATUM_A006261
  795. select SYS_FSL_ERRATUM_CPU_A003999
  796. select SYS_FSL_ERRATUM_DDR_A003
  797. select SYS_FSL_ERRATUM_DDR_A003474
  798. select SYS_FSL_ERRATUM_ESDHC111
  799. select SYS_FSL_ERRATUM_I2C_A004447
  800. select SYS_FSL_ERRATUM_NMG_CPU_A011
  801. select SYS_FSL_ERRATUM_SRIO_A004034
  802. select SYS_FSL_ERRATUM_USB14
  803. select SYS_FSL_HAS_DDR3
  804. select SYS_FSL_HAS_SEC
  805. select SYS_FSL_QORIQ_CHASSIS1
  806. select SYS_FSL_SEC_BE
  807. select SYS_FSL_SEC_COMPAT_4
  808. select FSL_ELBC
  809. imply CMD_NAND
  810. imply CMD_SATA
  811. imply CMD_REGINFO
  812. imply FSL_SATA
  813. config ARCH_P4080
  814. bool
  815. select E500MC
  816. select FSL_LAW
  817. select SYS_FSL_DDR_VER_44
  818. select SYS_FSL_ERRATUM_A004510
  819. select SYS_FSL_ERRATUM_A004580
  820. select SYS_FSL_ERRATUM_A004849
  821. select SYS_FSL_ERRATUM_A005812
  822. select SYS_FSL_ERRATUM_A007075
  823. select SYS_FSL_ERRATUM_CPC_A002
  824. select SYS_FSL_ERRATUM_CPC_A003
  825. select SYS_FSL_ERRATUM_CPU_A003999
  826. select SYS_FSL_ERRATUM_DDR_A003
  827. select SYS_FSL_ERRATUM_DDR_A003474
  828. select SYS_FSL_ERRATUM_ELBC_A001
  829. select SYS_FSL_ERRATUM_ESDHC111
  830. select SYS_FSL_ERRATUM_ESDHC13
  831. select SYS_FSL_ERRATUM_ESDHC135
  832. select SYS_FSL_ERRATUM_I2C_A004447
  833. select SYS_FSL_ERRATUM_NMG_CPU_A011
  834. select SYS_FSL_ERRATUM_SRIO_A004034
  835. select SYS_P4080_ERRATUM_CPU22
  836. select SYS_P4080_ERRATUM_PCIE_A003
  837. select SYS_P4080_ERRATUM_SERDES8
  838. select SYS_P4080_ERRATUM_SERDES9
  839. select SYS_P4080_ERRATUM_SERDES_A001
  840. select SYS_P4080_ERRATUM_SERDES_A005
  841. select SYS_FSL_HAS_DDR3
  842. select SYS_FSL_HAS_SEC
  843. select SYS_FSL_QORIQ_CHASSIS1
  844. select SYS_FSL_SEC_BE
  845. select SYS_FSL_SEC_COMPAT_4
  846. select FSL_ELBC
  847. imply CMD_SATA
  848. imply CMD_REGINFO
  849. imply SATA_SIL
  850. config ARCH_P5020
  851. bool
  852. select E500MC
  853. select FSL_LAW
  854. select SYS_FSL_DDR_VER_44
  855. select SYS_FSL_ERRATUM_A004510
  856. select SYS_FSL_ERRATUM_A005275
  857. select SYS_FSL_ERRATUM_A006261
  858. select SYS_FSL_ERRATUM_DDR_A003
  859. select SYS_FSL_ERRATUM_DDR_A003474
  860. select SYS_FSL_ERRATUM_ESDHC111
  861. select SYS_FSL_ERRATUM_I2C_A004447
  862. select SYS_FSL_ERRATUM_SRIO_A004034
  863. select SYS_FSL_ERRATUM_USB14
  864. select SYS_FSL_HAS_DDR3
  865. select SYS_FSL_HAS_SEC
  866. select SYS_FSL_QORIQ_CHASSIS1
  867. select SYS_FSL_SEC_BE
  868. select SYS_FSL_SEC_COMPAT_4
  869. select SYS_PPC64
  870. select FSL_ELBC
  871. imply CMD_SATA
  872. imply CMD_REGINFO
  873. imply FSL_SATA
  874. config ARCH_P5040
  875. bool
  876. select E500MC
  877. select FSL_LAW
  878. select SYS_FSL_DDR_VER_44
  879. select SYS_FSL_ERRATUM_A004510
  880. select SYS_FSL_ERRATUM_A004699
  881. select SYS_FSL_ERRATUM_A005275
  882. select SYS_FSL_ERRATUM_A005812
  883. select SYS_FSL_ERRATUM_A006261
  884. select SYS_FSL_ERRATUM_DDR_A003
  885. select SYS_FSL_ERRATUM_DDR_A003474
  886. select SYS_FSL_ERRATUM_ESDHC111
  887. select SYS_FSL_ERRATUM_USB14
  888. select SYS_FSL_HAS_DDR3
  889. select SYS_FSL_HAS_SEC
  890. select SYS_FSL_QORIQ_CHASSIS1
  891. select SYS_FSL_SEC_BE
  892. select SYS_FSL_SEC_COMPAT_4
  893. select SYS_PPC64
  894. select FSL_ELBC
  895. imply CMD_SATA
  896. imply CMD_REGINFO
  897. imply FSL_SATA
  898. config ARCH_QEMU_E500
  899. bool
  900. config ARCH_T1023
  901. bool
  902. select E500MC
  903. select FSL_LAW
  904. select SYS_FSL_DDR_VER_50
  905. select SYS_FSL_ERRATUM_A008378
  906. select SYS_FSL_ERRATUM_A009663
  907. select SYS_FSL_ERRATUM_A009942
  908. select SYS_FSL_ERRATUM_ESDHC111
  909. select SYS_FSL_HAS_DDR3
  910. select SYS_FSL_HAS_DDR4
  911. select SYS_FSL_HAS_SEC
  912. select SYS_FSL_QORIQ_CHASSIS2
  913. select SYS_FSL_SEC_BE
  914. select SYS_FSL_SEC_COMPAT_5
  915. select FSL_IFC
  916. imply CMD_EEPROM
  917. imply CMD_NAND
  918. imply CMD_REGINFO
  919. config ARCH_T1024
  920. bool
  921. select E500MC
  922. select FSL_LAW
  923. select SYS_FSL_DDR_VER_50
  924. select SYS_FSL_ERRATUM_A008378
  925. select SYS_FSL_ERRATUM_A009663
  926. select SYS_FSL_ERRATUM_A009942
  927. select SYS_FSL_ERRATUM_ESDHC111
  928. select SYS_FSL_HAS_DDR3
  929. select SYS_FSL_HAS_DDR4
  930. select SYS_FSL_HAS_SEC
  931. select SYS_FSL_QORIQ_CHASSIS2
  932. select SYS_FSL_SEC_BE
  933. select SYS_FSL_SEC_COMPAT_5
  934. select FSL_IFC
  935. imply CMD_EEPROM
  936. imply CMD_NAND
  937. imply CMD_MTDPARTS
  938. imply CMD_REGINFO
  939. config ARCH_T1040
  940. bool
  941. select E500MC
  942. select FSL_LAW
  943. select SYS_FSL_DDR_VER_50
  944. select SYS_FSL_ERRATUM_A008044
  945. select SYS_FSL_ERRATUM_A008378
  946. select SYS_FSL_ERRATUM_A009663
  947. select SYS_FSL_ERRATUM_A009942
  948. select SYS_FSL_ERRATUM_ESDHC111
  949. select SYS_FSL_HAS_DDR3
  950. select SYS_FSL_HAS_DDR4
  951. select SYS_FSL_HAS_SEC
  952. select SYS_FSL_QORIQ_CHASSIS2
  953. select SYS_FSL_SEC_BE
  954. select SYS_FSL_SEC_COMPAT_5
  955. select FSL_IFC
  956. imply CMD_MTDPARTS
  957. imply CMD_NAND
  958. imply CMD_SATA
  959. imply CMD_REGINFO
  960. imply FSL_SATA
  961. config ARCH_T1042
  962. bool
  963. select E500MC
  964. select FSL_LAW
  965. select SYS_FSL_DDR_VER_50
  966. select SYS_FSL_ERRATUM_A008044
  967. select SYS_FSL_ERRATUM_A008378
  968. select SYS_FSL_ERRATUM_A009663
  969. select SYS_FSL_ERRATUM_A009942
  970. select SYS_FSL_ERRATUM_ESDHC111
  971. select SYS_FSL_HAS_DDR3
  972. select SYS_FSL_HAS_DDR4
  973. select SYS_FSL_HAS_SEC
  974. select SYS_FSL_QORIQ_CHASSIS2
  975. select SYS_FSL_SEC_BE
  976. select SYS_FSL_SEC_COMPAT_5
  977. select FSL_IFC
  978. imply CMD_MTDPARTS
  979. imply CMD_NAND
  980. imply CMD_SATA
  981. imply CMD_REGINFO
  982. imply FSL_SATA
  983. config ARCH_T2080
  984. bool
  985. select E500MC
  986. select E6500
  987. select FSL_LAW
  988. select SYS_FSL_DDR_VER_47
  989. select SYS_FSL_ERRATUM_A006379
  990. select SYS_FSL_ERRATUM_A006593
  991. select SYS_FSL_ERRATUM_A007186
  992. select SYS_FSL_ERRATUM_A007212
  993. select SYS_FSL_ERRATUM_A007815
  994. select SYS_FSL_ERRATUM_A007907
  995. select SYS_FSL_ERRATUM_A009942
  996. select SYS_FSL_ERRATUM_ESDHC111
  997. select FSL_PCIE_RESET
  998. select SYS_FSL_HAS_DDR3
  999. select SYS_FSL_HAS_SEC
  1000. select SYS_FSL_QORIQ_CHASSIS2
  1001. select SYS_FSL_SEC_BE
  1002. select SYS_FSL_SEC_COMPAT_4
  1003. select SYS_PPC64
  1004. select FSL_IFC
  1005. imply CMD_NAND
  1006. imply CMD_REGINFO
  1007. config ARCH_T2081
  1008. bool
  1009. select E500MC
  1010. select E6500
  1011. select FSL_LAW
  1012. select SYS_FSL_DDR_VER_47
  1013. select SYS_FSL_ERRATUM_A006379
  1014. select SYS_FSL_ERRATUM_A006593
  1015. select SYS_FSL_ERRATUM_A007186
  1016. select SYS_FSL_ERRATUM_A007212
  1017. select SYS_FSL_ERRATUM_A009942
  1018. select SYS_FSL_ERRATUM_ESDHC111
  1019. select FSL_PCIE_RESET
  1020. select SYS_FSL_HAS_DDR3
  1021. select SYS_FSL_HAS_SEC
  1022. select SYS_FSL_QORIQ_CHASSIS2
  1023. select SYS_FSL_SEC_BE
  1024. select SYS_FSL_SEC_COMPAT_4
  1025. select SYS_PPC64
  1026. select FSL_IFC
  1027. imply CMD_NAND
  1028. imply CMD_REGINFO
  1029. config ARCH_T4160
  1030. bool
  1031. select E500MC
  1032. select E6500
  1033. select FSL_LAW
  1034. select SYS_FSL_DDR_VER_47
  1035. select SYS_FSL_ERRATUM_A004468
  1036. select SYS_FSL_ERRATUM_A005871
  1037. select SYS_FSL_ERRATUM_A006379
  1038. select SYS_FSL_ERRATUM_A006593
  1039. select SYS_FSL_ERRATUM_A007186
  1040. select SYS_FSL_ERRATUM_A007798
  1041. select SYS_FSL_ERRATUM_A009942
  1042. select SYS_FSL_HAS_DDR3
  1043. select SYS_FSL_HAS_SEC
  1044. select SYS_FSL_QORIQ_CHASSIS2
  1045. select SYS_FSL_SEC_BE
  1046. select SYS_FSL_SEC_COMPAT_4
  1047. select SYS_PPC64
  1048. select FSL_IFC
  1049. imply CMD_SATA
  1050. imply CMD_NAND
  1051. imply CMD_REGINFO
  1052. imply FSL_SATA
  1053. config ARCH_T4240
  1054. bool
  1055. select E500MC
  1056. select E6500
  1057. select FSL_LAW
  1058. select SYS_FSL_DDR_VER_47
  1059. select SYS_FSL_ERRATUM_A004468
  1060. select SYS_FSL_ERRATUM_A005871
  1061. select SYS_FSL_ERRATUM_A006261
  1062. select SYS_FSL_ERRATUM_A006379
  1063. select SYS_FSL_ERRATUM_A006593
  1064. select SYS_FSL_ERRATUM_A007186
  1065. select SYS_FSL_ERRATUM_A007798
  1066. select SYS_FSL_ERRATUM_A007815
  1067. select SYS_FSL_ERRATUM_A007907
  1068. select SYS_FSL_ERRATUM_A009942
  1069. select SYS_FSL_HAS_DDR3
  1070. select SYS_FSL_HAS_SEC
  1071. select SYS_FSL_QORIQ_CHASSIS2
  1072. select SYS_FSL_SEC_BE
  1073. select SYS_FSL_SEC_COMPAT_4
  1074. select SYS_PPC64
  1075. select FSL_IFC
  1076. imply CMD_SATA
  1077. imply CMD_NAND
  1078. imply CMD_REGINFO
  1079. imply FSL_SATA
  1080. config MPC85XX_HAVE_RESET_VECTOR
  1081. bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
  1082. depends on MPC85xx
  1083. config BOOKE
  1084. bool
  1085. default y
  1086. config E500
  1087. bool
  1088. default y
  1089. help
  1090. Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
  1091. config E500MC
  1092. bool
  1093. imply CMD_PCI
  1094. help
  1095. Enble PowerPC E500MC core
  1096. config E6500
  1097. bool
  1098. help
  1099. Enable PowerPC E6500 core
  1100. config FSL_LAW
  1101. bool
  1102. help
  1103. Use Freescale common code for Local Access Window
  1104. config NXP_ESBC
  1105. bool "NXP_ESBC"
  1106. help
  1107. Enable Freescale Secure Boot feature. Normally selected
  1108. by defconfig. If unsure, do not change.
  1109. config MAX_CPUS
  1110. int "Maximum number of CPUs permitted for MPC85xx"
  1111. default 12 if ARCH_T4240
  1112. default 8 if ARCH_P4080 || \
  1113. ARCH_T4160
  1114. default 4 if ARCH_B4860 || \
  1115. ARCH_P2041 || \
  1116. ARCH_P3041 || \
  1117. ARCH_P5040 || \
  1118. ARCH_T1040 || \
  1119. ARCH_T1042 || \
  1120. ARCH_T2080 || \
  1121. ARCH_T2081
  1122. default 2 if ARCH_B4420 || \
  1123. ARCH_BSC9132 || \
  1124. ARCH_MPC8572 || \
  1125. ARCH_P1020 || \
  1126. ARCH_P1021 || \
  1127. ARCH_P1022 || \
  1128. ARCH_P1023 || \
  1129. ARCH_P1024 || \
  1130. ARCH_P1025 || \
  1131. ARCH_P2020 || \
  1132. ARCH_P5020 || \
  1133. ARCH_T1023 || \
  1134. ARCH_T1024
  1135. default 1
  1136. help
  1137. Set this number to the maximum number of possible CPUs in the SoC.
  1138. SoCs may have multiple clusters with each cluster may have multiple
  1139. ports. If some ports are reserved but higher ports are used for
  1140. cores, count the reserved ports. This will allocate enough memory
  1141. in spin table to properly handle all cores.
  1142. config SYS_CCSRBAR_DEFAULT
  1143. hex "Default CCSRBAR address"
  1144. default 0xff700000 if ARCH_BSC9131 || \
  1145. ARCH_BSC9132 || \
  1146. ARCH_C29X || \
  1147. ARCH_MPC8536 || \
  1148. ARCH_MPC8540 || \
  1149. ARCH_MPC8541 || \
  1150. ARCH_MPC8544 || \
  1151. ARCH_MPC8548 || \
  1152. ARCH_MPC8555 || \
  1153. ARCH_MPC8560 || \
  1154. ARCH_MPC8568 || \
  1155. ARCH_MPC8569 || \
  1156. ARCH_MPC8572 || \
  1157. ARCH_P1010 || \
  1158. ARCH_P1011 || \
  1159. ARCH_P1020 || \
  1160. ARCH_P1021 || \
  1161. ARCH_P1022 || \
  1162. ARCH_P1024 || \
  1163. ARCH_P1025 || \
  1164. ARCH_P2020
  1165. default 0xff600000 if ARCH_P1023
  1166. default 0xfe000000 if ARCH_B4420 || \
  1167. ARCH_B4860 || \
  1168. ARCH_P2041 || \
  1169. ARCH_P3041 || \
  1170. ARCH_P4080 || \
  1171. ARCH_P5020 || \
  1172. ARCH_P5040 || \
  1173. ARCH_T1023 || \
  1174. ARCH_T1024 || \
  1175. ARCH_T1040 || \
  1176. ARCH_T1042 || \
  1177. ARCH_T2080 || \
  1178. ARCH_T2081 || \
  1179. ARCH_T4160 || \
  1180. ARCH_T4240
  1181. default 0xe0000000 if ARCH_QEMU_E500
  1182. help
  1183. Default value of CCSRBAR comes from power-on-reset. It
  1184. is fixed on each SoC. Some SoCs can have different value
  1185. if changed by pre-boot regime. The value here must match
  1186. the current value in SoC. If not sure, do not change.
  1187. config SYS_FSL_ERRATUM_A004468
  1188. bool
  1189. config SYS_FSL_ERRATUM_A004477
  1190. bool
  1191. config SYS_FSL_ERRATUM_A004508
  1192. bool
  1193. config SYS_FSL_ERRATUM_A004580
  1194. bool
  1195. config SYS_FSL_ERRATUM_A004699
  1196. bool
  1197. config SYS_FSL_ERRATUM_A004849
  1198. bool
  1199. config SYS_FSL_ERRATUM_A004510
  1200. bool
  1201. config SYS_FSL_ERRATUM_A004510_SVR_REV
  1202. hex
  1203. depends on SYS_FSL_ERRATUM_A004510
  1204. default 0x20 if ARCH_P4080
  1205. default 0x10
  1206. config SYS_FSL_ERRATUM_A004510_SVR_REV2
  1207. hex
  1208. depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
  1209. default 0x11
  1210. config SYS_FSL_ERRATUM_A005125
  1211. bool
  1212. config SYS_FSL_ERRATUM_A005434
  1213. bool
  1214. config SYS_FSL_ERRATUM_A005812
  1215. bool
  1216. config SYS_FSL_ERRATUM_A005871
  1217. bool
  1218. config SYS_FSL_ERRATUM_A005275
  1219. bool
  1220. config SYS_FSL_ERRATUM_A006261
  1221. bool
  1222. config SYS_FSL_ERRATUM_A006379
  1223. bool
  1224. config SYS_FSL_ERRATUM_A006384
  1225. bool
  1226. config SYS_FSL_ERRATUM_A006475
  1227. bool
  1228. config SYS_FSL_ERRATUM_A006593
  1229. bool
  1230. config SYS_FSL_ERRATUM_A007075
  1231. bool
  1232. config SYS_FSL_ERRATUM_A007186
  1233. bool
  1234. config SYS_FSL_ERRATUM_A007212
  1235. bool
  1236. config SYS_FSL_ERRATUM_A007815
  1237. bool
  1238. config SYS_FSL_ERRATUM_A007798
  1239. bool
  1240. config SYS_FSL_ERRATUM_A007907
  1241. bool
  1242. config SYS_FSL_ERRATUM_A008044
  1243. bool
  1244. config SYS_FSL_ERRATUM_CPC_A002
  1245. bool
  1246. config SYS_FSL_ERRATUM_CPC_A003
  1247. bool
  1248. config SYS_FSL_ERRATUM_CPU_A003999
  1249. bool
  1250. config SYS_FSL_ERRATUM_ELBC_A001
  1251. bool
  1252. config SYS_FSL_ERRATUM_I2C_A004447
  1253. bool
  1254. config SYS_FSL_A004447_SVR_REV
  1255. hex
  1256. depends on SYS_FSL_ERRATUM_I2C_A004447
  1257. default 0x00 if ARCH_MPC8548
  1258. default 0x10 if ARCH_P1010
  1259. default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
  1260. default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
  1261. config SYS_FSL_ERRATUM_IFC_A002769
  1262. bool
  1263. config SYS_FSL_ERRATUM_IFC_A003399
  1264. bool
  1265. config SYS_FSL_ERRATUM_NMG_CPU_A011
  1266. bool
  1267. config SYS_FSL_ERRATUM_NMG_ETSEC129
  1268. bool
  1269. config SYS_FSL_ERRATUM_NMG_LBC103
  1270. bool
  1271. config SYS_FSL_ERRATUM_P1010_A003549
  1272. bool
  1273. config SYS_FSL_ERRATUM_SATA_A001
  1274. bool
  1275. config SYS_FSL_ERRATUM_SEC_A003571
  1276. bool
  1277. config SYS_FSL_ERRATUM_SRIO_A004034
  1278. bool
  1279. config SYS_FSL_ERRATUM_USB14
  1280. bool
  1281. config SYS_P4080_ERRATUM_CPU22
  1282. bool
  1283. config SYS_P4080_ERRATUM_PCIE_A003
  1284. bool
  1285. config SYS_P4080_ERRATUM_SERDES8
  1286. bool
  1287. config SYS_P4080_ERRATUM_SERDES9
  1288. bool
  1289. config SYS_P4080_ERRATUM_SERDES_A001
  1290. bool
  1291. config SYS_P4080_ERRATUM_SERDES_A005
  1292. bool
  1293. config FSL_PCIE_DISABLE_ASPM
  1294. bool
  1295. config FSL_PCIE_RESET
  1296. bool
  1297. config SYS_FSL_QORIQ_CHASSIS1
  1298. bool
  1299. config SYS_FSL_QORIQ_CHASSIS2
  1300. bool
  1301. config SYS_FSL_NUM_LAWS
  1302. int "Number of local access windows"
  1303. depends on FSL_LAW
  1304. default 32 if ARCH_B4420 || \
  1305. ARCH_B4860 || \
  1306. ARCH_P2041 || \
  1307. ARCH_P3041 || \
  1308. ARCH_P4080 || \
  1309. ARCH_P5020 || \
  1310. ARCH_P5040 || \
  1311. ARCH_T2080 || \
  1312. ARCH_T2081 || \
  1313. ARCH_T4160 || \
  1314. ARCH_T4240
  1315. default 16 if ARCH_T1023 || \
  1316. ARCH_T1024 || \
  1317. ARCH_T1040 || \
  1318. ARCH_T1042
  1319. default 12 if ARCH_BSC9131 || \
  1320. ARCH_BSC9132 || \
  1321. ARCH_C29X || \
  1322. ARCH_MPC8536 || \
  1323. ARCH_MPC8572 || \
  1324. ARCH_P1010 || \
  1325. ARCH_P1011 || \
  1326. ARCH_P1020 || \
  1327. ARCH_P1021 || \
  1328. ARCH_P1022 || \
  1329. ARCH_P1023 || \
  1330. ARCH_P1024 || \
  1331. ARCH_P1025 || \
  1332. ARCH_P2020
  1333. default 10 if ARCH_MPC8544 || \
  1334. ARCH_MPC8548 || \
  1335. ARCH_MPC8568 || \
  1336. ARCH_MPC8569
  1337. default 8 if ARCH_MPC8540 || \
  1338. ARCH_MPC8541 || \
  1339. ARCH_MPC8555 || \
  1340. ARCH_MPC8560
  1341. help
  1342. Number of local access windows. This is fixed per SoC.
  1343. If not sure, do not change.
  1344. config SYS_FSL_THREADS_PER_CORE
  1345. int
  1346. default 2 if E6500
  1347. default 1
  1348. config SYS_NUM_TLBCAMS
  1349. int "Number of TLB CAM entries"
  1350. default 64 if E500MC
  1351. default 16
  1352. help
  1353. Number of TLB CAM entries for Book-E chips. 64 for E500MC,
  1354. 16 for other E500 SoCs.
  1355. config SYS_PPC64
  1356. bool
  1357. config SYS_PPC_E500_USE_DEBUG_TLB
  1358. bool
  1359. config FSL_IFC
  1360. bool
  1361. config FSL_ELBC
  1362. bool
  1363. config SYS_PPC_E500_DEBUG_TLB
  1364. int "Temporary TLB entry for external debugger"
  1365. depends on SYS_PPC_E500_USE_DEBUG_TLB
  1366. default 0 if ARCH_MPC8544 || ARCH_MPC8548
  1367. default 1 if ARCH_MPC8536
  1368. default 2 if ARCH_MPC8572 || \
  1369. ARCH_P1011 || \
  1370. ARCH_P1020 || \
  1371. ARCH_P1021 || \
  1372. ARCH_P1022 || \
  1373. ARCH_P1024 || \
  1374. ARCH_P1025 || \
  1375. ARCH_P2020
  1376. default 3 if ARCH_P1010 || \
  1377. ARCH_BSC9132 || \
  1378. ARCH_C29X
  1379. help
  1380. Select a temporary TLB entry to be used during boot to work
  1381. around limitations in e500v1 and e500v2 external debugger
  1382. support. This reduces the portions of the boot code where
  1383. breakpoints and single stepping do not work. The value of this
  1384. symbol should be set to the TLB1 entry to be used for this
  1385. purpose. If unsure, do not change.
  1386. config SYS_FSL_IFC_CLK_DIV
  1387. int "Divider of platform clock"
  1388. depends on FSL_IFC
  1389. default 2 if ARCH_B4420 || \
  1390. ARCH_B4860 || \
  1391. ARCH_T1024 || \
  1392. ARCH_T1023 || \
  1393. ARCH_T1040 || \
  1394. ARCH_T1042 || \
  1395. ARCH_T4160 || \
  1396. ARCH_T4240
  1397. default 1
  1398. help
  1399. Defines divider of platform clock(clock input to
  1400. IFC controller).
  1401. config SYS_FSL_LBC_CLK_DIV
  1402. int "Divider of platform clock"
  1403. depends on FSL_ELBC || ARCH_MPC8540 || \
  1404. ARCH_MPC8548 || ARCH_MPC8541 || \
  1405. ARCH_MPC8555 || ARCH_MPC8560 || \
  1406. ARCH_MPC8568
  1407. default 2 if ARCH_P2041 || \
  1408. ARCH_P3041 || \
  1409. ARCH_P4080 || \
  1410. ARCH_P5020 || \
  1411. ARCH_P5040
  1412. default 1
  1413. help
  1414. Defines divider of platform clock(clock input to
  1415. eLBC controller).
  1416. source "board/freescale/b4860qds/Kconfig"
  1417. source "board/freescale/bsc9131rdb/Kconfig"
  1418. source "board/freescale/bsc9132qds/Kconfig"
  1419. source "board/freescale/c29xpcie/Kconfig"
  1420. source "board/freescale/corenet_ds/Kconfig"
  1421. source "board/freescale/mpc8536ds/Kconfig"
  1422. source "board/freescale/mpc8541cds/Kconfig"
  1423. source "board/freescale/mpc8544ds/Kconfig"
  1424. source "board/freescale/mpc8548cds/Kconfig"
  1425. source "board/freescale/mpc8555cds/Kconfig"
  1426. source "board/freescale/mpc8568mds/Kconfig"
  1427. source "board/freescale/mpc8569mds/Kconfig"
  1428. source "board/freescale/mpc8572ds/Kconfig"
  1429. source "board/freescale/p1010rdb/Kconfig"
  1430. source "board/freescale/p1022ds/Kconfig"
  1431. source "board/freescale/p1023rdb/Kconfig"
  1432. source "board/freescale/p1_p2_rdb_pc/Kconfig"
  1433. source "board/freescale/p1_twr/Kconfig"
  1434. source "board/freescale/p2041rdb/Kconfig"
  1435. source "board/freescale/qemu-ppce500/Kconfig"
  1436. source "board/freescale/t102xqds/Kconfig"
  1437. source "board/freescale/t102xrdb/Kconfig"
  1438. source "board/freescale/t1040qds/Kconfig"
  1439. source "board/freescale/t104xrdb/Kconfig"
  1440. source "board/freescale/t208xqds/Kconfig"
  1441. source "board/freescale/t208xrdb/Kconfig"
  1442. source "board/freescale/t4qds/Kconfig"
  1443. source "board/freescale/t4rdb/Kconfig"
  1444. source "board/gdsys/p1022/Kconfig"
  1445. source "board/keymile/Kconfig"
  1446. source "board/sbc8548/Kconfig"
  1447. source "board/socrates/Kconfig"
  1448. source "board/varisys/cyrus/Kconfig"
  1449. source "board/xes/xpedite520x/Kconfig"
  1450. source "board/xes/xpedite537x/Kconfig"
  1451. source "board/xes/xpedite550x/Kconfig"
  1452. source "board/Arcturus/ucp1020/Kconfig"
  1453. endmenu