T104xRDB.h 26 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __CONFIG_H
  6. #define __CONFIG_H
  7. /*
  8. * T104x RDB board configuration file
  9. */
  10. #include <asm/config_mpc85xx.h>
  11. #ifdef CONFIG_RAMBOOT_PBL
  12. #ifndef CONFIG_NXP_ESBC
  13. #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
  14. #else
  15. #define CONFIG_SYS_FSL_PBL_PBI \
  16. $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
  17. #endif
  18. #define CONFIG_SPL_FLUSH_IMAGE
  19. #define CONFIG_SPL_PAD_TO 0x40000
  20. #define CONFIG_SPL_MAX_SIZE 0x28000
  21. #ifdef CONFIG_SPL_BUILD
  22. #define CONFIG_SPL_SKIP_RELOCATE
  23. #define CONFIG_SPL_COMMON_INIT_DDR
  24. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  25. #endif
  26. #define RESET_VECTOR_OFFSET 0x27FFC
  27. #define BOOT_PAGE_OFFSET 0x27000
  28. #ifdef CONFIG_NAND
  29. #ifdef CONFIG_NXP_ESBC
  30. #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  31. /*
  32. * HDR would be appended at end of image and copied to DDR along
  33. * with U-Boot image.
  34. */
  35. #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
  36. CONFIG_U_BOOT_HDR_SIZE)
  37. #else
  38. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  39. #endif
  40. #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
  41. #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
  42. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
  43. #ifdef CONFIG_TARGET_T1040RDB
  44. #define CONFIG_SYS_FSL_PBL_RCW \
  45. $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
  46. #endif
  47. #ifdef CONFIG_TARGET_T1042RDB_PI
  48. #define CONFIG_SYS_FSL_PBL_RCW \
  49. $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
  50. #endif
  51. #ifdef CONFIG_TARGET_T1042RDB
  52. #define CONFIG_SYS_FSL_PBL_RCW \
  53. $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
  54. #endif
  55. #ifdef CONFIG_TARGET_T1040D4RDB
  56. #define CONFIG_SYS_FSL_PBL_RCW \
  57. $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
  58. #endif
  59. #ifdef CONFIG_TARGET_T1042D4RDB
  60. #define CONFIG_SYS_FSL_PBL_RCW \
  61. $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
  62. #endif
  63. #endif
  64. #ifdef CONFIG_SPIFLASH
  65. #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
  66. #define CONFIG_SPL_SPI_FLASH_MINIMAL
  67. #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
  68. #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
  69. #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
  70. #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
  71. #ifndef CONFIG_SPL_BUILD
  72. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  73. #endif
  74. #ifdef CONFIG_TARGET_T1040RDB
  75. #define CONFIG_SYS_FSL_PBL_RCW \
  76. $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
  77. #endif
  78. #ifdef CONFIG_TARGET_T1042RDB_PI
  79. #define CONFIG_SYS_FSL_PBL_RCW \
  80. $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
  81. #endif
  82. #ifdef CONFIG_TARGET_T1042RDB
  83. #define CONFIG_SYS_FSL_PBL_RCW \
  84. $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
  85. #endif
  86. #ifdef CONFIG_TARGET_T1040D4RDB
  87. #define CONFIG_SYS_FSL_PBL_RCW \
  88. $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
  89. #endif
  90. #ifdef CONFIG_TARGET_T1042D4RDB
  91. #define CONFIG_SYS_FSL_PBL_RCW \
  92. $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
  93. #endif
  94. #endif
  95. #ifdef CONFIG_SDCARD
  96. #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
  97. #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  98. #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
  99. #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
  100. #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  101. #ifndef CONFIG_SPL_BUILD
  102. #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  103. #endif
  104. #ifdef CONFIG_TARGET_T1040RDB
  105. #define CONFIG_SYS_FSL_PBL_RCW \
  106. $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
  107. #endif
  108. #ifdef CONFIG_TARGET_T1042RDB_PI
  109. #define CONFIG_SYS_FSL_PBL_RCW \
  110. $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
  111. #endif
  112. #ifdef CONFIG_TARGET_T1042RDB
  113. #define CONFIG_SYS_FSL_PBL_RCW \
  114. $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
  115. #endif
  116. #ifdef CONFIG_TARGET_T1040D4RDB
  117. #define CONFIG_SYS_FSL_PBL_RCW \
  118. $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
  119. #endif
  120. #ifdef CONFIG_TARGET_T1042D4RDB
  121. #define CONFIG_SYS_FSL_PBL_RCW \
  122. $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
  123. #endif
  124. #endif
  125. #endif
  126. /* High Level Configuration Options */
  127. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  128. /* support deep sleep */
  129. #define CONFIG_DEEP_SLEEP
  130. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  131. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  132. #endif
  133. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  134. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  135. #define CONFIG_PCIE1 /* PCIE controller 1 */
  136. #define CONFIG_PCIE2 /* PCIE controller 2 */
  137. #define CONFIG_PCIE3 /* PCIE controller 3 */
  138. #define CONFIG_PCIE4 /* PCIE controller 4 */
  139. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  140. #define CONFIG_ENV_OVERWRITE
  141. #if defined(CONFIG_SPIFLASH)
  142. #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  143. #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  144. #define CONFIG_ENV_SECT_SIZE 0x10000
  145. #elif defined(CONFIG_SDCARD)
  146. #define CONFIG_SYS_MMC_ENV_DEV 0
  147. #define CONFIG_ENV_SIZE 0x2000
  148. #define CONFIG_ENV_OFFSET (512 * 0x800)
  149. #elif defined(CONFIG_NAND)
  150. #ifdef CONFIG_NXP_ESBC
  151. #define CONFIG_RAMBOOT_NAND
  152. #define CONFIG_BOOTSCRIPT_COPY_RAM
  153. #endif
  154. #define CONFIG_ENV_SIZE 0x2000
  155. #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
  156. #else
  157. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  158. #define CONFIG_ENV_SIZE 0x2000
  159. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  160. #endif
  161. #define CONFIG_SYS_CLK_FREQ 100000000
  162. #define CONFIG_DDR_CLK_FREQ 66666666
  163. /*
  164. * These can be toggled for performance analysis, otherwise use default.
  165. */
  166. #define CONFIG_SYS_CACHE_STASHING
  167. #define CONFIG_BACKSIDE_L2_CACHE
  168. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  169. #define CONFIG_BTB /* toggle branch predition */
  170. #define CONFIG_DDR_ECC
  171. #ifdef CONFIG_DDR_ECC
  172. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  173. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  174. #endif
  175. #define CONFIG_ENABLE_36BIT_PHYS
  176. #define CONFIG_ADDR_MAP
  177. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  178. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  179. #define CONFIG_SYS_MEMTEST_END 0x00400000
  180. /*
  181. * Config the L3 Cache as L3 SRAM
  182. */
  183. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  184. /*
  185. * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
  186. * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
  187. * (CONFIG_SYS_INIT_L3_VADDR) will be different.
  188. */
  189. #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
  190. #define CONFIG_SYS_L3_SIZE 256 << 10
  191. #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
  192. #ifdef CONFIG_RAMBOOT_PBL
  193. #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  194. #endif
  195. #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  196. #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
  197. #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  198. #define CONFIG_SYS_DCSRBAR 0xf0000000
  199. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  200. /*
  201. * DDR Setup
  202. */
  203. #define CONFIG_VERY_BIG_RAM
  204. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  205. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  206. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  207. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  208. #define CONFIG_DDR_SPD
  209. #define CONFIG_SYS_SPD_BUS_NUM 0
  210. #define SPD_EEPROM_ADDRESS 0x51
  211. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  212. /*
  213. * IFC Definitions
  214. */
  215. #define CONFIG_SYS_FLASH_BASE 0xe8000000
  216. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  217. #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
  218. #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
  219. CSPR_PORT_SIZE_16 | \
  220. CSPR_MSEL_NOR | \
  221. CSPR_V)
  222. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  223. /*
  224. * TDM Definition
  225. */
  226. #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
  227. /* NOR Flash Timing Params */
  228. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  229. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  230. FTIM0_NOR_TEADC(0x5) | \
  231. FTIM0_NOR_TEAHC(0x5))
  232. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  233. FTIM1_NOR_TRAD_NOR(0x1A) |\
  234. FTIM1_NOR_TSEQRAD_NOR(0x13))
  235. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  236. FTIM2_NOR_TCH(0x4) | \
  237. FTIM2_NOR_TWPH(0x0E) | \
  238. FTIM2_NOR_TWP(0x1c))
  239. #define CONFIG_SYS_NOR_FTIM3 0x0
  240. #define CONFIG_SYS_FLASH_QUIET_TEST
  241. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  242. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  243. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  244. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  245. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  246. #define CONFIG_SYS_FLASH_EMPTY_INFO
  247. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  248. /* CPLD on IFC */
  249. #define CPLD_LBMAP_MASK 0x3F
  250. #define CPLD_BANK_SEL_MASK 0x07
  251. #define CPLD_BANK_OVERRIDE 0x40
  252. #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
  253. #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
  254. #define CPLD_LBMAP_RESET 0xFF
  255. #define CPLD_LBMAP_SHIFT 0x03
  256. #if defined(CONFIG_TARGET_T1042RDB_PI)
  257. #define CPLD_DIU_SEL_DFP 0x80
  258. #elif defined(CONFIG_TARGET_T1042D4RDB)
  259. #define CPLD_DIU_SEL_DFP 0xc0
  260. #endif
  261. #if defined(CONFIG_TARGET_T1040D4RDB)
  262. #define CPLD_INT_MASK_ALL 0xFF
  263. #define CPLD_INT_MASK_THERM 0x80
  264. #define CPLD_INT_MASK_DVI_DFP 0x40
  265. #define CPLD_INT_MASK_QSGMII1 0x20
  266. #define CPLD_INT_MASK_QSGMII2 0x10
  267. #define CPLD_INT_MASK_SGMI1 0x08
  268. #define CPLD_INT_MASK_SGMI2 0x04
  269. #define CPLD_INT_MASK_TDMR1 0x02
  270. #define CPLD_INT_MASK_TDMR2 0x01
  271. #endif
  272. #define CONFIG_SYS_CPLD_BASE 0xffdf0000
  273. #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
  274. #define CONFIG_SYS_CSPR2_EXT (0xf)
  275. #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
  276. | CSPR_PORT_SIZE_8 \
  277. | CSPR_MSEL_GPCM \
  278. | CSPR_V)
  279. #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
  280. #define CONFIG_SYS_CSOR2 0x0
  281. /* CPLD Timing parameters for IFC CS2 */
  282. #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  283. FTIM0_GPCM_TEADC(0x0e) | \
  284. FTIM0_GPCM_TEAHC(0x0e))
  285. #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  286. FTIM1_GPCM_TRAD(0x1f))
  287. #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  288. FTIM2_GPCM_TCH(0x8) | \
  289. FTIM2_GPCM_TWP(0x1f))
  290. #define CONFIG_SYS_CS2_FTIM3 0x0
  291. /* NAND Flash on IFC */
  292. #define CONFIG_NAND_FSL_IFC
  293. #define CONFIG_SYS_NAND_BASE 0xff800000
  294. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  295. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  296. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  297. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  298. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  299. | CSPR_V)
  300. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  301. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  302. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  303. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  304. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  305. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  306. | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
  307. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  308. #define CONFIG_SYS_NAND_ONFI_DETECTION
  309. /* ONFI NAND Flash mode0 Timing Params */
  310. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  311. FTIM0_NAND_TWP(0x18) | \
  312. FTIM0_NAND_TWCHT(0x07) | \
  313. FTIM0_NAND_TWH(0x0a))
  314. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  315. FTIM1_NAND_TWBE(0x39) | \
  316. FTIM1_NAND_TRR(0x0e) | \
  317. FTIM1_NAND_TRP(0x18))
  318. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  319. FTIM2_NAND_TREH(0x0a) | \
  320. FTIM2_NAND_TWHRE(0x1e))
  321. #define CONFIG_SYS_NAND_FTIM3 0x0
  322. #define CONFIG_SYS_NAND_DDR_LAW 11
  323. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  324. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  325. #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  326. #if defined(CONFIG_NAND)
  327. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  328. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  329. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  330. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  331. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  332. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  333. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  334. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  335. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
  336. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
  337. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  338. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  339. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  340. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  341. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  342. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  343. #else
  344. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
  345. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
  346. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  347. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  348. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  349. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  350. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  351. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  352. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  353. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  354. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  355. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  356. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  357. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  358. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  359. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  360. #endif
  361. #ifdef CONFIG_SPL_BUILD
  362. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  363. #else
  364. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  365. #endif
  366. #if defined(CONFIG_RAMBOOT_PBL)
  367. #define CONFIG_SYS_RAMBOOT
  368. #endif
  369. #ifdef CONFIG_SYS_FSL_ERRATUM_A008044
  370. #if defined(CONFIG_NAND)
  371. #define CONFIG_A008044_WORKAROUND
  372. #endif
  373. #endif
  374. #define CONFIG_HWCONFIG
  375. /* define to use L1 as initial stack */
  376. #define CONFIG_L1_INIT_RAM
  377. #define CONFIG_SYS_INIT_RAM_LOCK
  378. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  379. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  380. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  381. /* The assembler doesn't like typecast */
  382. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  383. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  384. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  385. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  386. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  387. GENERATED_GBL_DATA_SIZE)
  388. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  389. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  390. #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  391. /* Serial Port - controlled on board with jumper J8
  392. * open - index 2
  393. * shorted - index 1
  394. */
  395. #define CONFIG_SYS_NS16550_SERIAL
  396. #define CONFIG_SYS_NS16550_REG_SIZE 1
  397. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  398. #define CONFIG_SYS_BAUDRATE_TABLE \
  399. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  400. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  401. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  402. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  403. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  404. #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
  405. /* Video */
  406. #define CONFIG_FSL_DIU_FB
  407. #ifdef CONFIG_FSL_DIU_FB
  408. #define CONFIG_FSL_DIU_CH7301
  409. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
  410. #define CONFIG_VIDEO_LOGO
  411. #define CONFIG_VIDEO_BMP_LOGO
  412. #endif
  413. #endif
  414. /* I2C */
  415. #define CONFIG_SYS_I2C
  416. #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
  417. #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
  418. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  419. #define CONFIG_SYS_FSL_I2C3_SPEED 400000
  420. #define CONFIG_SYS_FSL_I2C4_SPEED 400000
  421. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  422. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  423. #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  424. #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  425. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  426. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  427. #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  428. #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  429. /* I2C bus multiplexer */
  430. #define I2C_MUX_PCA_ADDR 0x70
  431. #define I2C_MUX_CH_DEFAULT 0x8
  432. #if defined(CONFIG_TARGET_T1042RDB_PI) || \
  433. defined(CONFIG_TARGET_T1040D4RDB) || \
  434. defined(CONFIG_TARGET_T1042D4RDB)
  435. /* LDI/DVI Encoder for display */
  436. #define CONFIG_SYS_I2C_LDI_ADDR 0x38
  437. #define CONFIG_SYS_I2C_DVI_ADDR 0x75
  438. /*
  439. * RTC configuration
  440. */
  441. #define RTC
  442. #define CONFIG_RTC_DS1337 1
  443. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  444. /*DVI encoder*/
  445. #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
  446. #endif
  447. /*
  448. * eSPI - Enhanced SPI
  449. */
  450. /*
  451. * General PCI
  452. * Memory space is mapped 1-1, but I/O space must start from 0.
  453. */
  454. #ifdef CONFIG_PCI
  455. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  456. #ifdef CONFIG_PCIE1
  457. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  458. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  459. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  460. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  461. #endif
  462. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  463. #ifdef CONFIG_PCIE2
  464. #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
  465. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
  466. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  467. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  468. #endif
  469. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  470. #ifdef CONFIG_PCIE3
  471. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
  472. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
  473. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  474. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  475. #endif
  476. /* controller 4, Base address 203000 */
  477. #ifdef CONFIG_PCIE4
  478. #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
  479. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
  480. #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
  481. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  482. #endif
  483. #if !defined(CONFIG_DM_PCI)
  484. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  485. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  486. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  487. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  488. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  489. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  490. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  491. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  492. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  493. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  494. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  495. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  496. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  497. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  498. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
  499. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  500. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  501. #define CONFIG_PCI_INDIRECT_BRIDGE
  502. #endif
  503. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  504. #endif /* CONFIG_PCI */
  505. /* SATA */
  506. #define CONFIG_FSL_SATA_V2
  507. #ifdef CONFIG_FSL_SATA_V2
  508. #define CONFIG_SYS_SATA_MAX_DEVICE 1
  509. #define CONFIG_SATA1
  510. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  511. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  512. #define CONFIG_LBA48
  513. #endif
  514. /*
  515. * USB
  516. */
  517. #define CONFIG_HAS_FSL_DR_USB
  518. #ifdef CONFIG_HAS_FSL_DR_USB
  519. #ifdef CONFIG_USB_EHCI_HCD
  520. #define CONFIG_USB_EHCI_FSL
  521. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  522. #endif
  523. #endif
  524. #ifdef CONFIG_MMC
  525. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  526. #endif
  527. /* Qman/Bman */
  528. #ifndef CONFIG_NOBQFMAN
  529. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  530. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  531. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  532. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  533. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  534. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  535. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  536. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  537. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  538. CONFIG_SYS_BMAN_CENA_SIZE)
  539. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  540. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  541. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  542. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  543. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  544. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  545. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  546. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  547. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  548. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  549. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  550. CONFIG_SYS_QMAN_CENA_SIZE)
  551. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  552. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  553. #define CONFIG_SYS_DPAA_FMAN
  554. #define CONFIG_SYS_DPAA_PME
  555. #define CONFIG_U_QE
  556. /* Default address of microcode for the Linux Fman driver */
  557. #if defined(CONFIG_SPIFLASH)
  558. /*
  559. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  560. * env, so we got 0x110000.
  561. */
  562. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  563. #elif defined(CONFIG_SDCARD)
  564. /*
  565. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  566. * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  567. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  568. */
  569. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
  570. #elif defined(CONFIG_NAND)
  571. #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
  572. #else
  573. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  574. #endif
  575. #if defined(CONFIG_SPIFLASH)
  576. #define CONFIG_SYS_QE_FW_ADDR 0x130000
  577. #elif defined(CONFIG_SDCARD)
  578. #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
  579. #elif defined(CONFIG_NAND)
  580. #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  581. #else
  582. #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
  583. #endif
  584. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  585. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  586. #endif /* CONFIG_NOBQFMAN */
  587. #ifdef CONFIG_SYS_DPAA_FMAN
  588. #define CONFIG_PHY_VITESSE
  589. #define CONFIG_PHY_REALTEK
  590. #endif
  591. #ifdef CONFIG_FMAN_ENET
  592. #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
  593. #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
  594. #elif defined(CONFIG_TARGET_T1040D4RDB)
  595. #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
  596. #elif defined(CONFIG_TARGET_T1042D4RDB)
  597. #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
  598. #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
  599. #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
  600. #endif
  601. #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
  602. #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
  603. #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
  604. #else
  605. #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
  606. #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
  607. #endif
  608. /* Enable VSC9953 L2 Switch driver on T1040 SoC */
  609. #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
  610. #define CONFIG_VSC9953
  611. #ifdef CONFIG_TARGET_T1040RDB
  612. #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
  613. #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
  614. #else
  615. #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
  616. #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
  617. #endif
  618. #endif
  619. #define CONFIG_ETHPRIME "FM1@DTSEC4"
  620. #endif
  621. /*
  622. * Environment
  623. */
  624. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  625. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  626. /*
  627. * Miscellaneous configurable options
  628. */
  629. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  630. /*
  631. * For booting Linux, the board info and command line data
  632. * have to be in the first 64 MB of memory, since this is
  633. * the maximum mapped by the Linux kernel during initialization.
  634. */
  635. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  636. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  637. #ifdef CONFIG_CMD_KGDB
  638. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  639. #endif
  640. /*
  641. * Dynamic MTD Partition support with mtdparts
  642. */
  643. /*
  644. * Environment Configuration
  645. */
  646. #define CONFIG_ROOTPATH "/opt/nfsroot"
  647. #define CONFIG_BOOTFILE "uImage"
  648. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
  649. /* default location for tftp and bootm */
  650. #define CONFIG_LOADADDR 1000000
  651. #define __USB_PHY_TYPE utmi
  652. #define RAMDISKFILE "t104xrdb/ramdisk.uboot"
  653. #ifdef CONFIG_TARGET_T1040RDB
  654. #define FDTFILE "t1040rdb/t1040rdb.dtb"
  655. #elif defined(CONFIG_TARGET_T1042RDB_PI)
  656. #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
  657. #elif defined(CONFIG_TARGET_T1042RDB)
  658. #define FDTFILE "t1042rdb/t1042rdb.dtb"
  659. #elif defined(CONFIG_TARGET_T1040D4RDB)
  660. #define FDTFILE "t1042rdb/t1040d4rdb.dtb"
  661. #elif defined(CONFIG_TARGET_T1042D4RDB)
  662. #define FDTFILE "t1042rdb/t1042d4rdb.dtb"
  663. #endif
  664. #ifdef CONFIG_FSL_DIU_FB
  665. #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
  666. #else
  667. #define DIU_ENVIRONMENT
  668. #endif
  669. #define CONFIG_EXTRA_ENV_SETTINGS \
  670. "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
  671. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
  672. "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  673. "netdev=eth0\0" \
  674. "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
  675. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  676. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  677. "tftpflash=tftpboot $loadaddr $uboot && " \
  678. "protect off $ubootaddr +$filesize && " \
  679. "erase $ubootaddr +$filesize && " \
  680. "cp.b $loadaddr $ubootaddr $filesize && " \
  681. "protect on $ubootaddr +$filesize && " \
  682. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  683. "consoledev=ttyS0\0" \
  684. "ramdiskaddr=2000000\0" \
  685. "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
  686. "fdtaddr=1e00000\0" \
  687. "fdtfile=" __stringify(FDTFILE) "\0" \
  688. "bdev=sda3\0"
  689. #define CONFIG_LINUX \
  690. "setenv bootargs root=/dev/ram rw " \
  691. "console=$consoledev,$baudrate $othbootargs;" \
  692. "setenv ramdiskaddr 0x02000000;" \
  693. "setenv fdtaddr 0x00c00000;" \
  694. "setenv loadaddr 0x1000000;" \
  695. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  696. #define CONFIG_HDBOOT \
  697. "setenv bootargs root=/dev/$bdev rw " \
  698. "console=$consoledev,$baudrate $othbootargs;" \
  699. "tftp $loadaddr $bootfile;" \
  700. "tftp $fdtaddr $fdtfile;" \
  701. "bootm $loadaddr - $fdtaddr"
  702. #define CONFIG_NFSBOOTCOMMAND \
  703. "setenv bootargs root=/dev/nfs rw " \
  704. "nfsroot=$serverip:$rootpath " \
  705. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  706. "console=$consoledev,$baudrate $othbootargs;" \
  707. "tftp $loadaddr $bootfile;" \
  708. "tftp $fdtaddr $fdtfile;" \
  709. "bootm $loadaddr - $fdtaddr"
  710. #define CONFIG_RAMBOOTCOMMAND \
  711. "setenv bootargs root=/dev/ram rw " \
  712. "console=$consoledev,$baudrate $othbootargs;" \
  713. "tftp $ramdiskaddr $ramdiskfile;" \
  714. "tftp $loadaddr $bootfile;" \
  715. "tftp $fdtaddr $fdtfile;" \
  716. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  717. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  718. #include <asm/fsl_secure_boot.h>
  719. #endif /* __CONFIG_H */