fsl_secure_boot.h 4.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __FSL_SECURE_BOOT_H
  6. #define __FSL_SECURE_BOOT_H
  7. #include <asm/config_mpc85xx.h>
  8. #ifdef CONFIG_NXP_ESBC
  9. #if defined(CONFIG_FSL_CORENET)
  10. #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
  11. #elif defined(CONFIG_TARGET_BSC9132QDS)
  12. #define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
  13. #elif defined(CONFIG_TARGET_C29XPCIE)
  14. #define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
  15. #else
  16. #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
  17. #endif
  18. #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
  19. #if defined(CONFIG_TARGET_B4860QDS) || \
  20. defined(CONFIG_TARGET_B4420QDS) || \
  21. defined(CONFIG_TARGET_T4160QDS) || \
  22. defined(CONFIG_TARGET_T4240QDS) || \
  23. defined(CONFIG_TARGET_T2080QDS) || \
  24. defined(CONFIG_TARGET_T2080RDB) || \
  25. defined(CONFIG_TARGET_T1040QDS) || \
  26. defined(CONFIG_TARGET_T1040RDB) || \
  27. defined(CONFIG_TARGET_T1040D4RDB) || \
  28. defined(CONFIG_TARGET_T1042RDB) || \
  29. defined(CONFIG_TARGET_T1042D4RDB) || \
  30. defined(CONFIG_TARGET_T1042RDB_PI) || \
  31. defined(CONFIG_ARCH_T1023) || \
  32. defined(CONFIG_ARCH_T1024)
  33. #ifndef CONFIG_SYS_RAMBOOT
  34. #define CONFIG_SYS_CPC_REINIT_F
  35. #endif
  36. #define CONFIG_KEY_REVOCATION
  37. #undef CONFIG_SYS_INIT_L3_ADDR
  38. #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
  39. #endif
  40. #if defined(CONFIG_RAMBOOT_PBL)
  41. #undef CONFIG_SYS_INIT_L3_ADDR
  42. #ifdef CONFIG_SYS_INIT_L3_VADDR
  43. #define CONFIG_SYS_INIT_L3_ADDR \
  44. (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
  45. 0xbff00000
  46. #else
  47. #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
  48. #endif
  49. #endif
  50. #if defined(CONFIG_TARGET_C29XPCIE)
  51. #define CONFIG_KEY_REVOCATION
  52. #endif
  53. #if defined(CONFIG_ARCH_P3041) || \
  54. defined(CONFIG_ARCH_P4080) || \
  55. defined(CONFIG_ARCH_P5020) || \
  56. defined(CONFIG_ARCH_P5040) || \
  57. defined(CONFIG_ARCH_P2041)
  58. #define CONFIG_FSL_TRUST_ARCH_v1
  59. #endif
  60. #if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
  61. /* The key used for verification of next level images
  62. * is picked up from an Extension Table which has
  63. * been verified by the ISBC (Internal Secure boot Code)
  64. * in boot ROM of the SoC.
  65. * The feature is only applicable in case of NOR boot and is
  66. * not applicable in case of RAMBOOT (NAND, SD, SPI).
  67. */
  68. #define CONFIG_FSL_ISBC_KEY_EXT
  69. #endif
  70. #endif /* #ifdef CONFIG_NXP_ESBC */
  71. #ifdef CONFIG_CHAIN_OF_TRUST
  72. #ifdef CONFIG_SPL_BUILD
  73. /*
  74. * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
  75. * due to space crunch on CPC and thus malloc will not work.
  76. */
  77. #define CONFIG_SPL_PPAACT_ADDR 0x2e000000
  78. #define CONFIG_SPL_SPAACT_ADDR 0x2f000000
  79. #define CONFIG_SPL_JR0_LIODN_S 454
  80. #define CONFIG_SPL_JR0_LIODN_NS 458
  81. /*
  82. * Define the key hash for U-Boot here if public/private key pair used to
  83. * sign U-boot are different from the SRK hash put in the fuse
  84. * Example of defining KEY_HASH is
  85. * #define CONFIG_SPL_UBOOT_KEY_HASH \
  86. * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
  87. * else leave it defined as NULL
  88. */
  89. #define CONFIG_SPL_UBOOT_KEY_HASH NULL
  90. #endif /* ifdef CONFIG_SPL_BUILD */
  91. #define CONFIG_FSL_SEC_MON
  92. #ifndef CONFIG_SPL_BUILD
  93. /*
  94. * fsl_setenv_chain_of_trust() must be called from
  95. * board_late_init()
  96. */
  97. /* If Boot Script is not on NOR and is required to be copied on RAM */
  98. #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
  99. #define CONFIG_BS_HDR_ADDR_RAM 0x00010000
  100. #define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000
  101. #define CONFIG_BS_HDR_SIZE 0x00002000
  102. #define CONFIG_BS_ADDR_RAM 0x00012000
  103. #define CONFIG_BS_ADDR_DEVICE 0x00802000
  104. #define CONFIG_BS_SIZE 0x00001000
  105. #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
  106. #else
  107. /* The bootscript header address is different for B4860 because the NOR
  108. * mapping is different on B4 due to reduced NOR size.
  109. */
  110. #if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
  111. #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000
  112. #elif defined(CONFIG_FSL_CORENET)
  113. #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000
  114. #elif defined(CONFIG_TARGET_BSC9132QDS)
  115. #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000
  116. #elif defined(CONFIG_TARGET_C29XPCIE)
  117. #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000
  118. #else
  119. #define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
  120. #endif
  121. #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
  122. #include <config_fsl_chain_trust.h>
  123. #endif /* #ifndef CONFIG_SPL_BUILD */
  124. #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
  125. #endif