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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2003 Motorola,Inc.
  5. */
  6. /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
  7. *
  8. * The processor starts at 0xfffffffc and the code is first executed in the
  9. * last 4K page(0xfffff000-0xffffffff) in flash/rom.
  10. *
  11. */
  12. #include <asm-offsets.h>
  13. #include <config.h>
  14. #include <mpc85xx.h>
  15. #include <version.h>
  16. #include <ppc_asm.tmpl>
  17. #include <ppc_defs.h>
  18. #include <asm/cache.h>
  19. #include <asm/mmu.h>
  20. #undef MSR_KERNEL
  21. #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
  22. #define LAW_EN 0x80000000
  23. #if defined(CONFIG_NAND_SPL) || \
  24. (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
  25. #define MINIMAL_SPL
  26. #endif
  27. #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
  28. !defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  29. #define NOR_BOOT
  30. #endif
  31. /*
  32. * Set up GOT: Global Offset Table
  33. *
  34. * Use r12 to access the GOT
  35. */
  36. START_GOT
  37. GOT_ENTRY(_GOT2_TABLE_)
  38. GOT_ENTRY(_FIXUP_TABLE_)
  39. #ifndef MINIMAL_SPL
  40. GOT_ENTRY(_start)
  41. GOT_ENTRY(_start_of_vectors)
  42. GOT_ENTRY(_end_of_vectors)
  43. GOT_ENTRY(transfer_to_handler)
  44. #endif
  45. GOT_ENTRY(__init_end)
  46. GOT_ENTRY(__bss_end)
  47. GOT_ENTRY(__bss_start)
  48. END_GOT
  49. /*
  50. * e500 Startup -- after reset only the last 4KB of the effective
  51. * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
  52. * section is located at THIS LAST page and basically does three
  53. * things: clear some registers, set up exception tables and
  54. * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
  55. * continue the boot procedure.
  56. * Once the boot rom is mapped by TLB entries we can proceed
  57. * with normal startup.
  58. *
  59. */
  60. .section .bootpg,"ax"
  61. .globl _start_e500
  62. _start_e500:
  63. /* Enable debug exception */
  64. li r1,MSR_DE
  65. mtmsr r1
  66. /*
  67. * If we got an ePAPR device tree pointer passed in as r3, we need that
  68. * later in cpu_init_early_f(). Save it to a safe register before we
  69. * clobber it so that we can fetch it from there later.
  70. */
  71. mr r24, r3
  72. #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
  73. mfspr r3,SPRN_SVR
  74. rlwinm r3,r3,0,0xff
  75. li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
  76. cmpw r3,r4
  77. beq 1f
  78. #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
  79. li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
  80. cmpw r3,r4
  81. beq 1f
  82. #endif
  83. /* Not a supported revision affected by erratum */
  84. li r27,0
  85. b 2f
  86. 1: li r27,1 /* Remember for later that we have the erratum */
  87. /* Erratum says set bits 55:60 to 001001 */
  88. msync
  89. isync
  90. mfspr r3,SPRN_HDBCR0
  91. li r4,0x48
  92. rlwimi r3,r4,0,0x1f8
  93. mtspr SPRN_HDBCR0,r3
  94. isync
  95. 2:
  96. #endif
  97. #ifdef CONFIG_SYS_FSL_ERRATUM_A005125
  98. msync
  99. isync
  100. mfspr r3, SPRN_HDBCR0
  101. oris r3, r3, 0x0080
  102. mtspr SPRN_HDBCR0, r3
  103. #endif
  104. #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_E500MC) && \
  105. !defined(CONFIG_E6500)
  106. /* ISBC uses L2 as stack.
  107. * Disable L2 cache here so that u-boot can enable it later
  108. * as part of it's normal flow
  109. */
  110. /* Check if L2 is enabled */
  111. mfspr r3, SPRN_L2CSR0
  112. lis r2, L2CSR0_L2E@h
  113. ori r2, r2, L2CSR0_L2E@l
  114. and. r4, r3, r2
  115. beq l2_disabled
  116. mfspr r3, SPRN_L2CSR0
  117. /* Flush L2 cache */
  118. lis r2,(L2CSR0_L2FL)@h
  119. ori r2, r2, (L2CSR0_L2FL)@l
  120. or r3, r2, r3
  121. sync
  122. isync
  123. mtspr SPRN_L2CSR0,r3
  124. isync
  125. 1:
  126. mfspr r3, SPRN_L2CSR0
  127. and. r1, r3, r2
  128. bne 1b
  129. mfspr r3, SPRN_L2CSR0
  130. lis r2, L2CSR0_L2E@h
  131. ori r2, r2, L2CSR0_L2E@l
  132. andc r4, r3, r2
  133. sync
  134. isync
  135. mtspr SPRN_L2CSR0,r4
  136. isync
  137. l2_disabled:
  138. #endif
  139. /* clear registers/arrays not reset by hardware */
  140. /* L1 */
  141. li r0,2
  142. mtspr L1CSR0,r0 /* invalidate d-cache */
  143. mtspr L1CSR1,r0 /* invalidate i-cache */
  144. mfspr r1,DBSR
  145. mtspr DBSR,r1 /* Clear all valid bits */
  146. .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
  147. lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
  148. ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
  149. mtspr MAS0, \scratch
  150. lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
  151. ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
  152. mtspr MAS1, \scratch
  153. lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
  154. ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
  155. mtspr MAS2, \scratch
  156. lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
  157. ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
  158. mtspr MAS3, \scratch
  159. lis \scratch, \phy_high@h
  160. ori \scratch, \scratch, \phy_high@l
  161. mtspr MAS7, \scratch
  162. isync
  163. msync
  164. tlbwe
  165. isync
  166. .endm
  167. .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
  168. lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
  169. ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
  170. mtspr MAS0, \scratch
  171. lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
  172. ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
  173. mtspr MAS1, \scratch
  174. lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
  175. ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
  176. mtspr MAS2, \scratch
  177. lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
  178. ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
  179. mtspr MAS3, \scratch
  180. lis \scratch, \phy_high@h
  181. ori \scratch, \scratch, \phy_high@l
  182. mtspr MAS7, \scratch
  183. isync
  184. msync
  185. tlbwe
  186. isync
  187. .endm
  188. .macro delete_tlb1_entry esel scratch
  189. lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
  190. ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
  191. mtspr MAS0, \scratch
  192. li \scratch, 0
  193. mtspr MAS1, \scratch
  194. isync
  195. msync
  196. tlbwe
  197. isync
  198. .endm
  199. .macro delete_tlb0_entry esel epn wimg scratch
  200. lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
  201. ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
  202. mtspr MAS0, \scratch
  203. li \scratch, 0
  204. mtspr MAS1, \scratch
  205. lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
  206. ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
  207. mtspr MAS2, \scratch
  208. isync
  209. msync
  210. tlbwe
  211. isync
  212. .endm
  213. /* Interrupt vectors do not fit in minimal SPL. */
  214. #if !defined(MINIMAL_SPL)
  215. /* Setup interrupt vectors */
  216. lis r1,CONFIG_SYS_MONITOR_BASE@h
  217. mtspr IVPR,r1
  218. li r4,CriticalInput@l
  219. mtspr IVOR0,r4 /* 0: Critical input */
  220. li r4,MachineCheck@l
  221. mtspr IVOR1,r4 /* 1: Machine check */
  222. li r4,DataStorage@l
  223. mtspr IVOR2,r4 /* 2: Data storage */
  224. li r4,InstStorage@l
  225. mtspr IVOR3,r4 /* 3: Instruction storage */
  226. li r4,ExtInterrupt@l
  227. mtspr IVOR4,r4 /* 4: External interrupt */
  228. li r4,Alignment@l
  229. mtspr IVOR5,r4 /* 5: Alignment */
  230. li r4,ProgramCheck@l
  231. mtspr IVOR6,r4 /* 6: Program check */
  232. li r4,FPUnavailable@l
  233. mtspr IVOR7,r4 /* 7: floating point unavailable */
  234. li r4,SystemCall@l
  235. mtspr IVOR8,r4 /* 8: System call */
  236. /* 9: Auxiliary processor unavailable(unsupported) */
  237. li r4,Decrementer@l
  238. mtspr IVOR10,r4 /* 10: Decrementer */
  239. li r4,IntervalTimer@l
  240. mtspr IVOR11,r4 /* 11: Interval timer */
  241. li r4,WatchdogTimer@l
  242. mtspr IVOR12,r4 /* 12: Watchdog timer */
  243. li r4,DataTLBError@l
  244. mtspr IVOR13,r4 /* 13: Data TLB error */
  245. li r4,InstructionTLBError@l
  246. mtspr IVOR14,r4 /* 14: Instruction TLB error */
  247. li r4,DebugBreakpoint@l
  248. mtspr IVOR15,r4 /* 15: Debug */
  249. #endif
  250. /* Clear and set up some registers. */
  251. li r0,0x0000
  252. lis r1,0xffff
  253. mtspr DEC,r0 /* prevent dec exceptions */
  254. mttbl r0 /* prevent fit & wdt exceptions */
  255. mttbu r0
  256. mtspr TSR,r1 /* clear all timer exception status */
  257. mtspr TCR,r0 /* disable all */
  258. mtspr ESR,r0 /* clear exception syndrome register */
  259. mtspr MCSR,r0 /* machine check syndrome register */
  260. mtxer r0 /* clear integer exception register */
  261. #ifdef CONFIG_SYS_BOOK3E_HV
  262. mtspr MAS8,r0 /* make sure MAS8 is clear */
  263. #endif
  264. /* Enable Time Base and Select Time Base Clock */
  265. lis r0,HID0_EMCP@h /* Enable machine check */
  266. #if defined(CONFIG_ENABLE_36BIT_PHYS)
  267. ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
  268. #endif
  269. #ifndef CONFIG_E500MC
  270. ori r0,r0,HID0_TBEN@l /* Enable Timebase */
  271. #endif
  272. mtspr HID0,r0
  273. #if !defined(CONFIG_E500MC) && !defined(CONFIG_ARCH_QEMU_E500)
  274. li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
  275. mfspr r3,PVR
  276. andi. r3,r3, 0xff
  277. cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
  278. blt 1f
  279. /* Set MBDD bit also */
  280. ori r0, r0, HID1_MBDD@l
  281. 1:
  282. mtspr HID1,r0
  283. #endif
  284. #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
  285. mfspr r3,SPRN_HDBCR1
  286. oris r3,r3,0x0100
  287. mtspr SPRN_HDBCR1,r3
  288. #endif
  289. /* Enable Branch Prediction */
  290. #if defined(CONFIG_BTB)
  291. lis r0,BUCSR_ENABLE@h
  292. ori r0,r0,BUCSR_ENABLE@l
  293. mtspr SPRN_BUCSR,r0
  294. #endif
  295. #if defined(CONFIG_SYS_INIT_DBCR)
  296. lis r1,0xffff
  297. ori r1,r1,0xffff
  298. mtspr DBSR,r1 /* Clear all status bits */
  299. lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
  300. ori r0,r0,CONFIG_SYS_INIT_DBCR@l
  301. mtspr DBCR0,r0
  302. #endif
  303. #ifdef CONFIG_ARCH_MPC8569
  304. #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
  305. #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
  306. /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
  307. * use address space which is more than 12bits, and it must be done in
  308. * the 4K boot page. So we set this bit here.
  309. */
  310. /* create a temp mapping TLB0[0] for LBCR */
  311. create_tlb0_entry 0, \
  312. 0, BOOKE_PAGESZ_4K, \
  313. CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
  314. CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
  315. 0, r6
  316. /* Set LBCR register */
  317. lis r4,CONFIG_SYS_LBCR_ADDR@h
  318. ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
  319. lis r5,CONFIG_SYS_LBC_LBCR@h
  320. ori r5,r5,CONFIG_SYS_LBC_LBCR@l
  321. stw r5,0(r4)
  322. isync
  323. /* invalidate this temp TLB */
  324. lis r4,CONFIG_SYS_LBC_ADDR@h
  325. ori r4,r4,CONFIG_SYS_LBC_ADDR@l
  326. tlbivax 0,r4
  327. isync
  328. #endif /* CONFIG_ARCH_MPC8569 */
  329. /*
  330. * Search for the TLB that covers the code we're executing, and shrink it
  331. * so that it covers only this 4K page. That will ensure that any other
  332. * TLB we create won't interfere with it. We assume that the TLB exists,
  333. * which is why we don't check the Valid bit of MAS1. We also assume
  334. * it is in TLB1.
  335. *
  336. * This is necessary, for example, when booting from the on-chip ROM,
  337. * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
  338. */
  339. bl nexti /* Find our address */
  340. nexti: mflr r1 /* R1 = our PC */
  341. li r2, 0
  342. mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
  343. isync
  344. msync
  345. tlbsx 0, r1 /* This must succeed */
  346. mfspr r14, MAS0 /* Save ESEL for later */
  347. rlwinm r14, r14, 16, 0xfff
  348. /* Set the size of the TLB to 4KB */
  349. mfspr r3, MAS1
  350. li r2, 0xF80
  351. andc r3, r3, r2 /* Clear the TSIZE bits */
  352. ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
  353. oris r3, r3, MAS1_IPROT@h
  354. mtspr MAS1, r3
  355. /*
  356. * Set the base address of the TLB to our PC. We assume that
  357. * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
  358. */
  359. lis r3, MAS2_EPN@h
  360. ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
  361. and r1, r1, r3 /* Our PC, rounded down to the nearest page */
  362. mfspr r2, MAS2
  363. andc r2, r2, r3
  364. or r2, r2, r1
  365. #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
  366. cmpwi r27,0
  367. beq 1f
  368. andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */
  369. rlwinm r2, r2, 0, ~MAS2_I
  370. ori r2, r2, MAS2_G
  371. 1:
  372. #endif
  373. mtspr MAS2, r2 /* Set the EPN to our PC base address */
  374. mfspr r2, MAS3
  375. andc r2, r2, r3
  376. or r2, r2, r1
  377. mtspr MAS3, r2 /* Set the RPN to our PC base address */
  378. isync
  379. msync
  380. tlbwe
  381. /*
  382. * Clear out any other TLB entries that may exist, to avoid conflicts.
  383. * Our TLB entry is in r14.
  384. */
  385. li r0, TLBIVAX_ALL | TLBIVAX_TLB0
  386. tlbivax 0, r0
  387. tlbsync
  388. mfspr r4, SPRN_TLB1CFG
  389. rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
  390. li r3, 0
  391. mtspr MAS1, r3
  392. 1: cmpw r3, r14
  393. rlwinm r5, r3, 16, MAS0_ESEL_MSK
  394. addi r3, r3, 1
  395. beq 2f /* skip the entry we're executing from */
  396. oris r5, r5, MAS0_TLBSEL(1)@h
  397. mtspr MAS0, r5
  398. isync
  399. tlbwe
  400. isync
  401. msync
  402. 2: cmpw r3, r4
  403. blt 1b
  404. #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \
  405. !defined(CONFIG_NXP_ESBC)
  406. /*
  407. * TLB entry for debuggging in AS1
  408. * Create temporary TLB entry in AS0 to handle debug exception
  409. * As on debug exception MSR is cleared i.e. Address space is changed
  410. * to 0. A TLB entry (in AS0) is required to handle debug exception generated
  411. * in AS1.
  412. */
  413. #ifdef NOR_BOOT
  414. /*
  415. * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
  416. * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
  417. * and this window is outside of 4K boot window.
  418. */
  419. create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
  420. 0, BOOKE_PAGESZ_4M, \
  421. CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
  422. 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
  423. 0, r6
  424. #else
  425. /*
  426. * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
  427. * because "nexti" will resize TLB to 4K
  428. */
  429. create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
  430. 0, BOOKE_PAGESZ_256K, \
  431. CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
  432. CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
  433. 0, r6
  434. #endif
  435. #endif
  436. /*
  437. * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
  438. * location is not where we want it. This typically happens on a 36-bit
  439. * system, where we want to move CCSR to near the top of 36-bit address space.
  440. *
  441. * To move CCSR, we create two temporary TLBs, one for the old location, and
  442. * another for the new location. On CoreNet systems, we also need to create
  443. * a special, temporary LAW.
  444. *
  445. * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
  446. * long-term TLBs, so we use TLB0 here.
  447. */
  448. #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
  449. #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
  450. #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
  451. #endif
  452. create_ccsr_new_tlb:
  453. /*
  454. * Create a TLB for the new location of CCSR. Register R8 is reserved
  455. * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
  456. */
  457. lis r8, CONFIG_SYS_CCSRBAR@h
  458. ori r8, r8, CONFIG_SYS_CCSRBAR@l
  459. lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
  460. ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
  461. create_tlb0_entry 0, \
  462. 0, BOOKE_PAGESZ_4K, \
  463. CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
  464. CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
  465. CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
  466. /*
  467. * Create a TLB for the current location of CCSR. Register R9 is reserved
  468. * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
  469. */
  470. create_ccsr_old_tlb:
  471. create_tlb0_entry 1, \
  472. 0, BOOKE_PAGESZ_4K, \
  473. CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
  474. CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
  475. 0, r3 /* The default CCSR address is always a 32-bit number */
  476. /*
  477. * We have a TLB for what we think is the current (old) CCSR. Let's
  478. * verify that, otherwise we won't be able to move it.
  479. * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
  480. * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
  481. */
  482. verify_old_ccsr:
  483. lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
  484. ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
  485. #ifdef CONFIG_FSL_CORENET
  486. lwz r1, 4(r9) /* CCSRBARL */
  487. #else
  488. lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
  489. slwi r1, r1, 12
  490. #endif
  491. cmpl 0, r0, r1
  492. /*
  493. * If the value we read from CCSRBARL is not what we expect, then
  494. * enter an infinite loop. This will at least allow a debugger to
  495. * halt execution and examine TLBs, etc. There's no point in going
  496. * on.
  497. */
  498. infinite_debug_loop:
  499. bne infinite_debug_loop
  500. #ifdef CONFIG_FSL_CORENET
  501. #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
  502. #define LAW_SIZE_4K 0xb
  503. #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
  504. #define CCSRAR_C 0x80000000 /* Commit */
  505. create_temp_law:
  506. /*
  507. * On CoreNet systems, we create the temporary LAW using a special LAW
  508. * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
  509. */
  510. lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
  511. ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
  512. lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
  513. ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
  514. lis r2, CCSRBAR_LAWAR@h
  515. ori r2, r2, CCSRBAR_LAWAR@l
  516. stw r0, 0xc00(r9) /* LAWBARH0 */
  517. stw r1, 0xc04(r9) /* LAWBARL0 */
  518. sync
  519. stw r2, 0xc08(r9) /* LAWAR0 */
  520. /*
  521. * Read back from LAWAR to ensure the update is complete. e500mc
  522. * cores also require an isync.
  523. */
  524. lwz r0, 0xc08(r9) /* LAWAR0 */
  525. isync
  526. /*
  527. * Read the current CCSRBARH and CCSRBARL using load word instructions.
  528. * Follow this with an isync instruction. This forces any outstanding
  529. * accesses to configuration space to completion.
  530. */
  531. read_old_ccsrbar:
  532. lwz r0, 0(r9) /* CCSRBARH */
  533. lwz r0, 4(r9) /* CCSRBARL */
  534. isync
  535. /*
  536. * Write the new values for CCSRBARH and CCSRBARL to their old
  537. * locations. The CCSRBARH has a shadow register. When the CCSRBARH
  538. * has a new value written it loads a CCSRBARH shadow register. When
  539. * the CCSRBARL is written, the CCSRBARH shadow register contents
  540. * along with the CCSRBARL value are loaded into the CCSRBARH and
  541. * CCSRBARL registers, respectively. Follow this with a sync
  542. * instruction.
  543. */
  544. write_new_ccsrbar:
  545. lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
  546. ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
  547. lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
  548. ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
  549. lis r2, CCSRAR_C@h
  550. ori r2, r2, CCSRAR_C@l
  551. stw r0, 0(r9) /* Write to CCSRBARH */
  552. sync /* Make sure we write to CCSRBARH first */
  553. stw r1, 4(r9) /* Write to CCSRBARL */
  554. sync
  555. /*
  556. * Write a 1 to the commit bit (C) of CCSRAR at the old location.
  557. * Follow this with a sync instruction.
  558. */
  559. stw r2, 8(r9)
  560. sync
  561. /* Delete the temporary LAW */
  562. delete_temp_law:
  563. li r1, 0
  564. stw r1, 0xc08(r8)
  565. sync
  566. stw r1, 0xc00(r8)
  567. stw r1, 0xc04(r8)
  568. sync
  569. #else /* #ifdef CONFIG_FSL_CORENET */
  570. write_new_ccsrbar:
  571. /*
  572. * Read the current value of CCSRBAR using a load word instruction
  573. * followed by an isync. This forces all accesses to configuration
  574. * space to complete.
  575. */
  576. sync
  577. lwz r0, 0(r9)
  578. isync
  579. /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
  580. #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
  581. (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
  582. /* Write the new value to CCSRBAR. */
  583. lis r0, CCSRBAR_PHYS_RS12@h
  584. ori r0, r0, CCSRBAR_PHYS_RS12@l
  585. stw r0, 0(r9)
  586. sync
  587. /*
  588. * The manual says to perform a load of an address that does not
  589. * access configuration space or the on-chip SRAM using an existing TLB,
  590. * but that doesn't appear to be necessary. We will do the isync,
  591. * though.
  592. */
  593. isync
  594. /*
  595. * Read the contents of CCSRBAR from its new location, followed by
  596. * another isync.
  597. */
  598. lwz r0, 0(r8)
  599. isync
  600. #endif /* #ifdef CONFIG_FSL_CORENET */
  601. /* Delete the temporary TLBs */
  602. delete_temp_tlbs:
  603. delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
  604. delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
  605. #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
  606. #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  607. create_ccsr_l2_tlb:
  608. /*
  609. * Create a TLB for the MMR location of CCSR
  610. * to access L2CSR0 register
  611. */
  612. create_tlb0_entry 0, \
  613. 0, BOOKE_PAGESZ_4K, \
  614. CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
  615. CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
  616. CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
  617. enable_l2_cluster_l2:
  618. /* enable L2 cache */
  619. lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
  620. ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
  621. li r4, 33 /* stash id */
  622. stw r4, 4(r3)
  623. lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
  624. ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
  625. sync
  626. stw r4, 0(r3) /* invalidate L2 */
  627. /* Poll till the bits are cleared */
  628. 1: sync
  629. lwz r0, 0(r3)
  630. twi 0, r0, 0
  631. isync
  632. and. r1, r0, r4
  633. bne 1b
  634. /* L2PE must be set before L2 cache is enabled */
  635. lis r4, (L2CSR0_L2PE)@h
  636. ori r4, r4, (L2CSR0_L2PE)@l
  637. sync
  638. stw r4, 0(r3) /* enable L2 parity/ECC error checking */
  639. /* Poll till the bit is set */
  640. 1: sync
  641. lwz r0, 0(r3)
  642. twi 0, r0, 0
  643. isync
  644. and. r1, r0, r4
  645. beq 1b
  646. lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
  647. ori r4, r4, (L2CSR0_L2REP_MODE)@l
  648. sync
  649. stw r4, 0(r3) /* enable L2 */
  650. /* Poll till the bit is set */
  651. 1: sync
  652. lwz r0, 0(r3)
  653. twi 0, r0, 0
  654. isync
  655. and. r1, r0, r4
  656. beq 1b
  657. delete_ccsr_l2_tlb:
  658. delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
  659. #endif
  660. /*
  661. * Enable the L1. On e6500, this has to be done
  662. * after the L2 is up.
  663. */
  664. #ifdef CONFIG_SYS_CACHE_STASHING
  665. /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
  666. li r2,(32 + 0)
  667. mtspr L1CSR2,r2
  668. #endif
  669. /* Enable/invalidate the I-Cache */
  670. lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
  671. ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
  672. mtspr SPRN_L1CSR1,r2
  673. 1:
  674. mfspr r3,SPRN_L1CSR1
  675. and. r1,r3,r2
  676. bne 1b
  677. lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
  678. ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
  679. mtspr SPRN_L1CSR1,r3
  680. isync
  681. 2:
  682. mfspr r3,SPRN_L1CSR1
  683. andi. r1,r3,L1CSR1_ICE@l
  684. beq 2b
  685. /* Enable/invalidate the D-Cache */
  686. lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
  687. ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
  688. mtspr SPRN_L1CSR0,r2
  689. 1:
  690. mfspr r3,SPRN_L1CSR0
  691. and. r1,r3,r2
  692. bne 1b
  693. lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
  694. ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
  695. mtspr SPRN_L1CSR0,r3
  696. isync
  697. 2:
  698. mfspr r3,SPRN_L1CSR0
  699. andi. r1,r3,L1CSR0_DCE@l
  700. beq 2b
  701. #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
  702. #define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
  703. #define LAW_SIZE_1M 0x13
  704. #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
  705. cmpwi r27,0
  706. beq 9f
  707. /*
  708. * Create a TLB entry for CCSR
  709. *
  710. * We're executing out of TLB1 entry in r14, and that's the only
  711. * TLB entry that exists. To allocate some TLB entries for our
  712. * own use, flip a bit high enough that we won't flip it again
  713. * via incrementing.
  714. */
  715. xori r8, r14, 32
  716. lis r0, MAS0_TLBSEL(1)@h
  717. rlwimi r0, r8, 16, MAS0_ESEL_MSK
  718. lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
  719. ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
  720. lis r7, CONFIG_SYS_CCSRBAR@h
  721. ori r7, r7, CONFIG_SYS_CCSRBAR@l
  722. ori r2, r7, MAS2_I|MAS2_G
  723. lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
  724. ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
  725. lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
  726. ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
  727. mtspr MAS0, r0
  728. mtspr MAS1, r1
  729. mtspr MAS2, r2
  730. mtspr MAS3, r3
  731. mtspr MAS7, r4
  732. isync
  733. tlbwe
  734. isync
  735. msync
  736. /* Map DCSR temporarily to physical address zero */
  737. li r0, 0
  738. lis r3, DCSRBAR_LAWAR@h
  739. ori r3, r3, DCSRBAR_LAWAR@l
  740. stw r0, 0xc00(r7) /* LAWBARH0 */
  741. stw r0, 0xc04(r7) /* LAWBARL0 */
  742. sync
  743. stw r3, 0xc08(r7) /* LAWAR0 */
  744. /* Read back from LAWAR to ensure the update is complete. */
  745. lwz r3, 0xc08(r7) /* LAWAR0 */
  746. isync
  747. /* Create a TLB entry for DCSR at zero */
  748. addi r9, r8, 1
  749. lis r0, MAS0_TLBSEL(1)@h
  750. rlwimi r0, r9, 16, MAS0_ESEL_MSK
  751. lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
  752. ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
  753. li r6, 0 /* DCSR effective address */
  754. ori r2, r6, MAS2_I|MAS2_G
  755. li r3, MAS3_SW|MAS3_SR
  756. li r4, 0
  757. mtspr MAS0, r0
  758. mtspr MAS1, r1
  759. mtspr MAS2, r2
  760. mtspr MAS3, r3
  761. mtspr MAS7, r4
  762. isync
  763. tlbwe
  764. isync
  765. msync
  766. /* enable the timebase */
  767. #define CTBENR 0xe2084
  768. li r3, 1
  769. addis r4, r7, CTBENR@ha
  770. stw r3, CTBENR@l(r4)
  771. lwz r3, CTBENR@l(r4)
  772. twi 0,r3,0
  773. isync
  774. .macro erratum_set_ccsr offset value
  775. addis r3, r7, \offset@ha
  776. lis r4, \value@h
  777. addi r3, r3, \offset@l
  778. ori r4, r4, \value@l
  779. bl erratum_set_value
  780. .endm
  781. .macro erratum_set_dcsr offset value
  782. addis r3, r6, \offset@ha
  783. lis r4, \value@h
  784. addi r3, r3, \offset@l
  785. ori r4, r4, \value@l
  786. bl erratum_set_value
  787. .endm
  788. erratum_set_dcsr 0xb0e08 0xe0201800
  789. erratum_set_dcsr 0xb0e18 0xe0201800
  790. erratum_set_dcsr 0xb0e38 0xe0400000
  791. erratum_set_dcsr 0xb0008 0x00900000
  792. erratum_set_dcsr 0xb0e40 0xe00a0000
  793. erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
  794. #ifdef CONFIG_RAMBOOT_PBL
  795. erratum_set_ccsr 0x10f00 0x495e5000
  796. #else
  797. erratum_set_ccsr 0x10f00 0x415e5000
  798. #endif
  799. erratum_set_ccsr 0x11f00 0x415e5000
  800. /* Make temp mapping uncacheable again, if it was initially */
  801. bl 2f
  802. 2: mflr r3
  803. tlbsx 0, r3
  804. mfspr r4, MAS2
  805. rlwimi r4, r15, 0, MAS2_I
  806. rlwimi r4, r15, 0, MAS2_G
  807. mtspr MAS2, r4
  808. isync
  809. tlbwe
  810. isync
  811. msync
  812. /* Clear the cache */
  813. lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
  814. ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
  815. sync
  816. isync
  817. mtspr SPRN_L1CSR1,r3
  818. isync
  819. 2: sync
  820. mfspr r4,SPRN_L1CSR1
  821. and. r4,r4,r3
  822. bne 2b
  823. lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
  824. ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
  825. sync
  826. isync
  827. mtspr SPRN_L1CSR1,r3
  828. isync
  829. 2: sync
  830. mfspr r4,SPRN_L1CSR1
  831. and. r4,r4,r3
  832. beq 2b
  833. /* Remove temporary mappings */
  834. lis r0, MAS0_TLBSEL(1)@h
  835. rlwimi r0, r9, 16, MAS0_ESEL_MSK
  836. li r3, 0
  837. mtspr MAS0, r0
  838. mtspr MAS1, r3
  839. isync
  840. tlbwe
  841. isync
  842. msync
  843. li r3, 0
  844. stw r3, 0xc08(r7) /* LAWAR0 */
  845. lwz r3, 0xc08(r7)
  846. isync
  847. lis r0, MAS0_TLBSEL(1)@h
  848. rlwimi r0, r8, 16, MAS0_ESEL_MSK
  849. li r3, 0
  850. mtspr MAS0, r0
  851. mtspr MAS1, r3
  852. isync
  853. tlbwe
  854. isync
  855. msync
  856. b 9f
  857. /* r3 = addr, r4 = value, clobbers r5, r11, r12 */
  858. erratum_set_value:
  859. /* Lock two cache lines into I-Cache */
  860. sync
  861. mfspr r11, SPRN_L1CSR1
  862. rlwinm r11, r11, 0, ~L1CSR1_ICUL
  863. sync
  864. isync
  865. mtspr SPRN_L1CSR1, r11
  866. isync
  867. mflr r12
  868. bl 5f
  869. 5: mflr r5
  870. addi r5, r5, 2f - 5b
  871. icbtls 0, 0, r5
  872. addi r5, r5, 64
  873. sync
  874. mfspr r11, SPRN_L1CSR1
  875. 3: andi. r11, r11, L1CSR1_ICUL
  876. bne 3b
  877. icbtls 0, 0, r5
  878. addi r5, r5, 64
  879. sync
  880. mfspr r11, SPRN_L1CSR1
  881. 3: andi. r11, r11, L1CSR1_ICUL
  882. bne 3b
  883. b 2f
  884. .align 6
  885. /* Inside a locked cacheline, wait a while, write, then wait a while */
  886. 2: sync
  887. mfspr r5, SPRN_TBRL
  888. addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
  889. 4: mfspr r5, SPRN_TBRL
  890. subf. r5, r5, r11
  891. bgt 4b
  892. stw r4, 0(r3)
  893. mfspr r5, SPRN_TBRL
  894. addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
  895. 4: mfspr r5, SPRN_TBRL
  896. subf. r5, r5, r11
  897. bgt 4b
  898. sync
  899. /*
  900. * Fill out the rest of this cache line and the next with nops,
  901. * to ensure that nothing outside the locked area will be
  902. * fetched due to a branch.
  903. */
  904. .rept 19
  905. nop
  906. .endr
  907. sync
  908. mfspr r11, SPRN_L1CSR1
  909. rlwinm r11, r11, 0, ~L1CSR1_ICUL
  910. sync
  911. isync
  912. mtspr SPRN_L1CSR1, r11
  913. isync
  914. mtlr r12
  915. blr
  916. 9:
  917. #endif
  918. create_init_ram_area:
  919. lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
  920. ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
  921. #ifdef NOR_BOOT
  922. /* create a temp mapping in AS=1 to the 4M boot window */
  923. create_tlb1_entry 15, \
  924. 1, BOOKE_PAGESZ_4M, \
  925. CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
  926. 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
  927. 0, r6
  928. #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC)
  929. /* create a temp mapping in AS = 1 for Flash mapping
  930. * created by PBL for ISBC code
  931. */
  932. create_tlb1_entry 15, \
  933. 1, BOOKE_PAGESZ_1M, \
  934. CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
  935. CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
  936. 0, r6
  937. /*
  938. * For Targets without CONFIG_SPL like P3, P5
  939. * and for targets with CONFIG_SPL like T1, T2, T4, only for
  940. * u-boot-spl i.e. CONFIG_SPL_BUILD
  941. */
  942. #elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_NXP_ESBC) && \
  943. (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  944. /* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE
  945. * to L3 Address configured by PBL for ISBC code
  946. */
  947. create_tlb1_entry 15, \
  948. 1, BOOKE_PAGESZ_1M, \
  949. CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
  950. CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
  951. 0, r6
  952. #else
  953. /*
  954. * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
  955. * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
  956. */
  957. create_tlb1_entry 15, \
  958. 1, BOOKE_PAGESZ_1M, \
  959. CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
  960. CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
  961. 0, r6
  962. #endif
  963. /* create a temp mapping in AS=1 to the stack */
  964. #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
  965. defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
  966. create_tlb1_entry 14, \
  967. 1, BOOKE_PAGESZ_16K, \
  968. CONFIG_SYS_INIT_RAM_ADDR, 0, \
  969. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
  970. CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
  971. #else
  972. create_tlb1_entry 14, \
  973. 1, BOOKE_PAGESZ_16K, \
  974. CONFIG_SYS_INIT_RAM_ADDR, 0, \
  975. CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
  976. 0, r6
  977. #endif
  978. lis r6,MSR_IS|MSR_DS|MSR_DE@h
  979. ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
  980. lis r7,switch_as@h
  981. ori r7,r7,switch_as@l
  982. mtspr SPRN_SRR0,r7
  983. mtspr SPRN_SRR1,r6
  984. rfi
  985. switch_as:
  986. /* L1 DCache is used for initial RAM */
  987. /* Allocate Initial RAM in data cache.
  988. */
  989. lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
  990. ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
  991. mfspr r2, L1CFG0
  992. andi. r2, r2, 0x1ff
  993. /* cache size * 1024 / (2 * L1 line size) */
  994. slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
  995. mtctr r2
  996. li r0,0
  997. 1:
  998. dcbz r0,r3
  999. #ifdef CONFIG_E6500 /* Lock/unlock L2 cache long with L1 */
  1000. dcbtls 2, r0, r3
  1001. dcbtls 0, r0, r3
  1002. #else
  1003. dcbtls 0, r0, r3
  1004. #endif
  1005. addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
  1006. bdnz 1b
  1007. /* Jump out the last 4K page and continue to 'normal' start */
  1008. #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
  1009. /* We assume that we're already running at the address we're linked at */
  1010. b _start_cont
  1011. #else
  1012. /* Calculate absolute address in FLASH and jump there */
  1013. /*--------------------------------------------------------------*/
  1014. lis r3,CONFIG_SYS_MONITOR_BASE@h
  1015. ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
  1016. addi r3,r3,_start_cont - _start
  1017. mtlr r3
  1018. blr
  1019. #endif
  1020. .text
  1021. .globl _start
  1022. _start:
  1023. .long 0x27051956 /* U-BOOT Magic Number */
  1024. .globl version_string
  1025. version_string:
  1026. .ascii U_BOOT_VERSION_STRING, "\0"
  1027. .align 4
  1028. .globl _start_cont
  1029. _start_cont:
  1030. /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
  1031. lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
  1032. ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
  1033. #if CONFIG_VAL(SYS_MALLOC_F_LEN)
  1034. #if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
  1035. #error "SYS_MALLOC_F_LEN too large to fit into initial RAM."
  1036. #endif
  1037. /* Leave 16+ byte for back chain termination and NULL return address */
  1038. subi r3,r3,((CONFIG_VAL(SYS_MALLOC_F_LEN)+16+15)&~0xf)
  1039. #endif
  1040. /* End of RAM */
  1041. lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
  1042. ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
  1043. li r0,0
  1044. 1: subi r4,r4,4
  1045. stw r0,0(r4)
  1046. cmplw r4,r3
  1047. bne 1b
  1048. #if CONFIG_VAL(SYS_MALLOC_F_LEN)
  1049. lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
  1050. ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
  1051. addi r3,r3,16 /* Pre-relocation malloc area */
  1052. stw r3,GD_MALLOC_BASE(r4)
  1053. subi r3,r3,16
  1054. #endif
  1055. li r0,0
  1056. stw r0,0(r3) /* Terminate Back Chain */
  1057. stw r0,+4(r3) /* NULL return address. */
  1058. mr r1,r3 /* Transfer to SP(r1) */
  1059. GET_GOT
  1060. /* Needed for -msingle-pic-base */
  1061. bl _GLOBAL_OFFSET_TABLE_@local-4
  1062. mflr r30
  1063. /* Pass our potential ePAPR device tree pointer to cpu_init_early_f */
  1064. mr r3, r24
  1065. bl cpu_init_early_f
  1066. /* switch back to AS = 0 */
  1067. lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
  1068. ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
  1069. mtmsr r3
  1070. isync
  1071. bl cpu_init_f /* return boot_flag for calling board_init_f */
  1072. bl board_init_f
  1073. isync
  1074. /* NOTREACHED - board_init_f() does not return */
  1075. #ifndef MINIMAL_SPL
  1076. .globl _start_of_vectors
  1077. _start_of_vectors:
  1078. /* Critical input. */
  1079. CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
  1080. /* Machine check */
  1081. MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  1082. /* Data Storage exception. */
  1083. STD_EXCEPTION(0x0300, DataStorage, UnknownException)
  1084. /* Instruction Storage exception. */
  1085. STD_EXCEPTION(0x0400, InstStorage, UnknownException)
  1086. /* External Interrupt exception. */
  1087. STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
  1088. /* Alignment exception. */
  1089. Alignment:
  1090. EXCEPTION_PROLOG(SRR0, SRR1)
  1091. mfspr r4,DAR
  1092. stw r4,_DAR(r21)
  1093. mfspr r5,DSISR
  1094. stw r5,_DSISR(r21)
  1095. addi r3,r1,STACK_FRAME_OVERHEAD
  1096. EXC_XFER_TEMPLATE(0x600, Alignment, AlignmentException,
  1097. MSR_KERNEL, COPY_EE)
  1098. /* Program check exception */
  1099. ProgramCheck:
  1100. EXCEPTION_PROLOG(SRR0, SRR1)
  1101. addi r3,r1,STACK_FRAME_OVERHEAD
  1102. EXC_XFER_TEMPLATE(0x700, ProgramCheck, ProgramCheckException,
  1103. MSR_KERNEL, COPY_EE)
  1104. /* No FPU on MPC85xx. This exception is not supposed to happen.
  1105. */
  1106. STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
  1107. STD_EXCEPTION(0x0900, SystemCall, UnknownException)
  1108. STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
  1109. STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
  1110. STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
  1111. STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
  1112. STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
  1113. CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
  1114. .globl _end_of_vectors
  1115. _end_of_vectors:
  1116. . = . + (0x100 - ( . & 0xff )) /* align for debug */
  1117. /*
  1118. * This code finishes saving the registers to the exception frame
  1119. * and jumps to the appropriate handler for the exception.
  1120. * Register r21 is pointer into trap frame, r1 has new stack pointer.
  1121. * r23 is the address of the handler.
  1122. */
  1123. .globl transfer_to_handler
  1124. transfer_to_handler:
  1125. SAVE_GPR(7, r21)
  1126. SAVE_4GPRS(8, r21)
  1127. SAVE_8GPRS(12, r21)
  1128. SAVE_8GPRS(24, r21)
  1129. li r22,0
  1130. stw r22,RESULT(r21)
  1131. mtspr SPRG2,r22 /* r1 is now kernel sp */
  1132. mtctr r23 /* virtual address of handler */
  1133. mtmsr r20
  1134. bctrl
  1135. int_return:
  1136. mfmsr r28 /* Disable interrupts */
  1137. li r4,0
  1138. ori r4,r4,MSR_EE
  1139. andc r28,r28,r4
  1140. SYNC /* Some chip revs need this... */
  1141. mtmsr r28
  1142. SYNC
  1143. lwz r2,_CTR(r1)
  1144. lwz r0,_LINK(r1)
  1145. mtctr r2
  1146. mtlr r0
  1147. lwz r2,_XER(r1)
  1148. lwz r0,_CCR(r1)
  1149. mtspr XER,r2
  1150. mtcrf 0xFF,r0
  1151. REST_10GPRS(3, r1)
  1152. REST_10GPRS(13, r1)
  1153. REST_8GPRS(23, r1)
  1154. REST_GPR(31, r1)
  1155. lwz r2,_NIP(r1) /* Restore environment */
  1156. lwz r0,_MSR(r1)
  1157. mtspr SRR0,r2
  1158. mtspr SRR1,r0
  1159. lwz r0,GPR0(r1)
  1160. lwz r2,GPR2(r1)
  1161. lwz r1,GPR1(r1)
  1162. SYNC
  1163. rfi
  1164. /* Cache functions.
  1165. */
  1166. .globl flush_icache
  1167. flush_icache:
  1168. .globl invalidate_icache
  1169. invalidate_icache:
  1170. mfspr r0,L1CSR1
  1171. ori r0,r0,L1CSR1_ICFI
  1172. msync
  1173. isync
  1174. mtspr L1CSR1,r0
  1175. isync
  1176. blr /* entire I cache */
  1177. .globl invalidate_dcache
  1178. invalidate_dcache:
  1179. mfspr r0,L1CSR0
  1180. ori r0,r0,L1CSR0_DCFI
  1181. msync
  1182. isync
  1183. mtspr L1CSR0,r0
  1184. isync
  1185. blr
  1186. .globl icache_enable
  1187. icache_enable:
  1188. mflr r8
  1189. bl invalidate_icache
  1190. mtlr r8
  1191. isync
  1192. mfspr r4,L1CSR1
  1193. ori r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@l
  1194. oris r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@h
  1195. mtspr L1CSR1,r4
  1196. isync
  1197. blr
  1198. .globl icache_disable
  1199. icache_disable:
  1200. mfspr r0,L1CSR1
  1201. lis r3,0
  1202. ori r3,r3,L1CSR1_ICE
  1203. andc r0,r0,r3
  1204. mtspr L1CSR1,r0
  1205. isync
  1206. blr
  1207. .globl icache_status
  1208. icache_status:
  1209. mfspr r3,L1CSR1
  1210. andi. r3,r3,L1CSR1_ICE
  1211. blr
  1212. .globl dcache_enable
  1213. dcache_enable:
  1214. mflr r8
  1215. bl invalidate_dcache
  1216. mtlr r8
  1217. isync
  1218. mfspr r0,L1CSR0
  1219. ori r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@l
  1220. oris r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@h
  1221. msync
  1222. isync
  1223. mtspr L1CSR0,r0
  1224. isync
  1225. blr
  1226. .globl dcache_disable
  1227. dcache_disable:
  1228. mfspr r3,L1CSR0
  1229. lis r4,0
  1230. ori r4,r4,L1CSR0_DCE
  1231. andc r3,r3,r4
  1232. mtspr L1CSR0,r3
  1233. isync
  1234. blr
  1235. .globl dcache_status
  1236. dcache_status:
  1237. mfspr r3,L1CSR0
  1238. andi. r3,r3,L1CSR0_DCE
  1239. blr
  1240. /*------------------------------------------------------------------------------- */
  1241. /* Function: in8 */
  1242. /* Description: Input 8 bits */
  1243. /*------------------------------------------------------------------------------- */
  1244. .globl in8
  1245. in8:
  1246. lbz r3,0x0000(r3)
  1247. blr
  1248. /*------------------------------------------------------------------------------- */
  1249. /* Function: out8 */
  1250. /* Description: Output 8 bits */
  1251. /*------------------------------------------------------------------------------- */
  1252. .globl out8
  1253. out8:
  1254. stb r4,0x0000(r3)
  1255. sync
  1256. blr
  1257. /*------------------------------------------------------------------------------- */
  1258. /* Function: out16 */
  1259. /* Description: Output 16 bits */
  1260. /*------------------------------------------------------------------------------- */
  1261. .globl out16
  1262. out16:
  1263. sth r4,0x0000(r3)
  1264. sync
  1265. blr
  1266. /*------------------------------------------------------------------------------- */
  1267. /* Function: out16r */
  1268. /* Description: Byte reverse and output 16 bits */
  1269. /*------------------------------------------------------------------------------- */
  1270. .globl out16r
  1271. out16r:
  1272. sthbrx r4,r0,r3
  1273. sync
  1274. blr
  1275. /*------------------------------------------------------------------------------- */
  1276. /* Function: out32 */
  1277. /* Description: Output 32 bits */
  1278. /*------------------------------------------------------------------------------- */
  1279. .globl out32
  1280. out32:
  1281. stw r4,0x0000(r3)
  1282. sync
  1283. blr
  1284. /*------------------------------------------------------------------------------- */
  1285. /* Function: out32r */
  1286. /* Description: Byte reverse and output 32 bits */
  1287. /*------------------------------------------------------------------------------- */
  1288. .globl out32r
  1289. out32r:
  1290. stwbrx r4,r0,r3
  1291. sync
  1292. blr
  1293. /*------------------------------------------------------------------------------- */
  1294. /* Function: in16 */
  1295. /* Description: Input 16 bits */
  1296. /*------------------------------------------------------------------------------- */
  1297. .globl in16
  1298. in16:
  1299. lhz r3,0x0000(r3)
  1300. blr
  1301. /*------------------------------------------------------------------------------- */
  1302. /* Function: in16r */
  1303. /* Description: Input 16 bits and byte reverse */
  1304. /*------------------------------------------------------------------------------- */
  1305. .globl in16r
  1306. in16r:
  1307. lhbrx r3,r0,r3
  1308. blr
  1309. /*------------------------------------------------------------------------------- */
  1310. /* Function: in32 */
  1311. /* Description: Input 32 bits */
  1312. /*------------------------------------------------------------------------------- */
  1313. .globl in32
  1314. in32:
  1315. lwz 3,0x0000(3)
  1316. blr
  1317. /*------------------------------------------------------------------------------- */
  1318. /* Function: in32r */
  1319. /* Description: Input 32 bits and byte reverse */
  1320. /*------------------------------------------------------------------------------- */
  1321. .globl in32r
  1322. in32r:
  1323. lwbrx r3,r0,r3
  1324. blr
  1325. #endif /* !MINIMAL_SPL */
  1326. /*------------------------------------------------------------------------------*/
  1327. /*
  1328. * void write_tlb(mas0, mas1, mas2, mas3, mas7)
  1329. */
  1330. .globl write_tlb
  1331. write_tlb:
  1332. mtspr MAS0,r3
  1333. mtspr MAS1,r4
  1334. mtspr MAS2,r5
  1335. mtspr MAS3,r6
  1336. #ifdef CONFIG_ENABLE_36BIT_PHYS
  1337. mtspr MAS7,r7
  1338. #endif
  1339. li r3,0
  1340. #ifdef CONFIG_SYS_BOOK3E_HV
  1341. mtspr MAS8,r3
  1342. #endif
  1343. isync
  1344. tlbwe
  1345. msync
  1346. isync
  1347. blr
  1348. /*
  1349. * void relocate_code (addr_sp, gd, addr_moni)
  1350. *
  1351. * This "function" does not return, instead it continues in RAM
  1352. * after relocating the monitor code.
  1353. *
  1354. * r3 = dest
  1355. * r4 = src
  1356. * r5 = length in bytes
  1357. * r6 = cachelinesize
  1358. */
  1359. .globl relocate_code
  1360. relocate_code:
  1361. mr r1,r3 /* Set new stack pointer */
  1362. mr r9,r4 /* Save copy of Init Data pointer */
  1363. mr r10,r5 /* Save copy of Destination Address */
  1364. GET_GOT
  1365. #ifndef CONFIG_SPL_SKIP_RELOCATE
  1366. mr r3,r5 /* Destination Address */
  1367. lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
  1368. ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
  1369. lwz r5,GOT(__init_end)
  1370. sub r5,r5,r4
  1371. li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
  1372. /*
  1373. * Fix GOT pointer:
  1374. *
  1375. * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
  1376. *
  1377. * Offset:
  1378. */
  1379. sub r15,r10,r4
  1380. /* First our own GOT */
  1381. add r12,r12,r15
  1382. /* the the one used by the C code */
  1383. add r30,r30,r15
  1384. /*
  1385. * Now relocate code
  1386. */
  1387. cmplw cr1,r3,r4
  1388. addi r0,r5,3
  1389. srwi. r0,r0,2
  1390. beq cr1,4f /* In place copy is not necessary */
  1391. beq 7f /* Protect against 0 count */
  1392. mtctr r0
  1393. bge cr1,2f
  1394. la r8,-4(r4)
  1395. la r7,-4(r3)
  1396. 1: lwzu r0,4(r8)
  1397. stwu r0,4(r7)
  1398. bdnz 1b
  1399. b 4f
  1400. 2: slwi r0,r0,2
  1401. add r8,r4,r0
  1402. add r7,r3,r0
  1403. 3: lwzu r0,-4(r8)
  1404. stwu r0,-4(r7)
  1405. bdnz 3b
  1406. /*
  1407. * Now flush the cache: note that we must start from a cache aligned
  1408. * address. Otherwise we might miss one cache line.
  1409. */
  1410. 4: cmpwi r6,0
  1411. add r5,r3,r5
  1412. beq 7f /* Always flush prefetch queue in any case */
  1413. subi r0,r6,1
  1414. andc r3,r3,r0
  1415. mr r4,r3
  1416. 5: dcbst 0,r4
  1417. add r4,r4,r6
  1418. cmplw r4,r5
  1419. blt 5b
  1420. sync /* Wait for all dcbst to complete on bus */
  1421. mr r4,r3
  1422. 6: icbi 0,r4
  1423. add r4,r4,r6
  1424. cmplw r4,r5
  1425. blt 6b
  1426. 7: sync /* Wait for all icbi to complete on bus */
  1427. isync
  1428. /*
  1429. * We are done. Do not return, instead branch to second part of board
  1430. * initialization, now running from RAM.
  1431. */
  1432. addi r0,r10,in_ram - _start
  1433. /*
  1434. * As IVPR is going to point RAM address,
  1435. * Make sure IVOR15 has valid opcode to support debugger
  1436. */
  1437. mtspr IVOR15,r0
  1438. /*
  1439. * Re-point the IVPR at RAM
  1440. */
  1441. mtspr IVPR,r10
  1442. mtlr r0
  1443. blr /* NEVER RETURNS! */
  1444. #endif
  1445. .globl in_ram
  1446. in_ram:
  1447. /*
  1448. * Relocation Function, r12 point to got2+0x8000
  1449. *
  1450. * Adjust got2 pointers, no need to check for 0, this code
  1451. * already puts a few entries in the table.
  1452. */
  1453. li r0,__got2_entries@sectoff@l
  1454. la r3,GOT(_GOT2_TABLE_)
  1455. lwz r11,GOT(_GOT2_TABLE_)
  1456. mtctr r0
  1457. sub r11,r3,r11
  1458. addi r3,r3,-4
  1459. 1: lwzu r0,4(r3)
  1460. cmpwi r0,0
  1461. beq- 2f
  1462. add r0,r0,r11
  1463. stw r0,0(r3)
  1464. 2: bdnz 1b
  1465. /*
  1466. * Now adjust the fixups and the pointers to the fixups
  1467. * in case we need to move ourselves again.
  1468. */
  1469. li r0,__fixup_entries@sectoff@l
  1470. lwz r3,GOT(_FIXUP_TABLE_)
  1471. cmpwi r0,0
  1472. mtctr r0
  1473. addi r3,r3,-4
  1474. beq 4f
  1475. 3: lwzu r4,4(r3)
  1476. lwzux r0,r4,r11
  1477. cmpwi r0,0
  1478. add r0,r0,r11
  1479. stw r4,0(r3)
  1480. beq- 5f
  1481. stw r0,0(r4)
  1482. 5: bdnz 3b
  1483. 4:
  1484. clear_bss:
  1485. /*
  1486. * Now clear BSS segment
  1487. */
  1488. lwz r3,GOT(__bss_start)
  1489. lwz r4,GOT(__bss_end)
  1490. cmplw 0,r3,r4
  1491. beq 6f
  1492. li r0,0
  1493. 5:
  1494. stw r0,0(r3)
  1495. addi r3,r3,4
  1496. cmplw 0,r3,r4
  1497. blt 5b
  1498. 6:
  1499. mr r3,r9 /* Init Data pointer */
  1500. mr r4,r10 /* Destination Address */
  1501. bl board_init_r
  1502. #ifndef MINIMAL_SPL
  1503. /*
  1504. * Copy exception vector code to low memory
  1505. *
  1506. * r3: dest_addr
  1507. * r7: source address, r8: end address, r9: target address
  1508. */
  1509. .globl trap_init
  1510. trap_init:
  1511. mflr r11
  1512. bl _GLOBAL_OFFSET_TABLE_-4
  1513. mflr r12
  1514. /* Update IVORs as per relocation */
  1515. mtspr IVPR,r3
  1516. lwz r4,CriticalInput@got(r12)
  1517. mtspr IVOR0,r4 /* 0: Critical input */
  1518. lwz r4,MachineCheck@got(r12)
  1519. mtspr IVOR1,r4 /* 1: Machine check */
  1520. lwz r4,DataStorage@got(r12)
  1521. mtspr IVOR2,r4 /* 2: Data storage */
  1522. lwz r4,InstStorage@got(r12)
  1523. mtspr IVOR3,r4 /* 3: Instruction storage */
  1524. lwz r4,ExtInterrupt@got(r12)
  1525. mtspr IVOR4,r4 /* 4: External interrupt */
  1526. lwz r4,Alignment@got(r12)
  1527. mtspr IVOR5,r4 /* 5: Alignment */
  1528. lwz r4,ProgramCheck@got(r12)
  1529. mtspr IVOR6,r4 /* 6: Program check */
  1530. lwz r4,FPUnavailable@got(r12)
  1531. mtspr IVOR7,r4 /* 7: floating point unavailable */
  1532. lwz r4,SystemCall@got(r12)
  1533. mtspr IVOR8,r4 /* 8: System call */
  1534. /* 9: Auxiliary processor unavailable(unsupported) */
  1535. lwz r4,Decrementer@got(r12)
  1536. mtspr IVOR10,r4 /* 10: Decrementer */
  1537. lwz r4,IntervalTimer@got(r12)
  1538. mtspr IVOR11,r4 /* 11: Interval timer */
  1539. lwz r4,WatchdogTimer@got(r12)
  1540. mtspr IVOR12,r4 /* 12: Watchdog timer */
  1541. lwz r4,DataTLBError@got(r12)
  1542. mtspr IVOR13,r4 /* 13: Data TLB error */
  1543. lwz r4,InstructionTLBError@got(r12)
  1544. mtspr IVOR14,r4 /* 14: Instruction TLB error */
  1545. lwz r4,DebugBreakpoint@got(r12)
  1546. mtspr IVOR15,r4 /* 15: Debug */
  1547. mtlr r11
  1548. blr
  1549. .globl unlock_ram_in_cache
  1550. unlock_ram_in_cache:
  1551. /* invalidate the INIT_RAM section */
  1552. lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
  1553. ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
  1554. mfspr r4,L1CFG0
  1555. andi. r4,r4,0x1ff
  1556. slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
  1557. mtctr r4
  1558. 1: dcbi r0,r3
  1559. #ifdef CONFIG_E6500 /* lock/unlock L2 cache long with L1 */
  1560. dcblc 2, r0, r3
  1561. dcblc 0, r0, r3
  1562. #else
  1563. dcblc r0,r3
  1564. #endif
  1565. addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
  1566. bdnz 1b
  1567. sync
  1568. /* Invalidate the TLB entries for the cache */
  1569. lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
  1570. ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
  1571. tlbivax 0,r3
  1572. addi r3,r3,0x1000
  1573. tlbivax 0,r3
  1574. addi r3,r3,0x1000
  1575. tlbivax 0,r3
  1576. addi r3,r3,0x1000
  1577. tlbivax 0,r3
  1578. isync
  1579. blr
  1580. .globl flush_dcache
  1581. flush_dcache:
  1582. mfspr r3,SPRN_L1CFG0
  1583. rlwinm r5,r3,9,3 /* Extract cache block size */
  1584. twlgti r5,1 /* Only 32 and 64 byte cache blocks
  1585. * are currently defined.
  1586. */
  1587. li r4,32
  1588. subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
  1589. * log2(number of ways)
  1590. */
  1591. slw r5,r4,r5 /* r5 = cache block size */
  1592. rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
  1593. mulli r7,r7,13 /* An 8-way cache will require 13
  1594. * loads per set.
  1595. */
  1596. slw r7,r7,r6
  1597. /* save off HID0 and set DCFA */
  1598. mfspr r8,SPRN_HID0
  1599. ori r9,r8,HID0_DCFA@l
  1600. mtspr SPRN_HID0,r9
  1601. isync
  1602. lis r4,0
  1603. mtctr r7
  1604. 1: lwz r3,0(r4) /* Load... */
  1605. add r4,r4,r5
  1606. bdnz 1b
  1607. msync
  1608. lis r4,0
  1609. mtctr r7
  1610. 1: dcbf 0,r4 /* ...and flush. */
  1611. add r4,r4,r5
  1612. bdnz 1b
  1613. /* restore HID0 */
  1614. mtspr SPRN_HID0,r8
  1615. isync
  1616. blr
  1617. #endif /* !MINIMAL_SPL */