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@@ -31,7 +31,8 @@
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#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
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-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
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+#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || \
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+ defined(CONFIG_IMX8M)
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#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
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#else
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#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
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@@ -55,21 +56,21 @@ struct nand_ecclayout fake_ecc_layout;
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
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{
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- uint32_t addr = (uint32_t)info->data_buf;
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+ uint32_t addr = (uintptr_t)info->data_buf;
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flush_dcache_range(addr, addr + info->data_buf_size);
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}
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static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
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{
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- uint32_t addr = (uint32_t)info->data_buf;
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+ uint32_t addr = (uintptr_t)info->data_buf;
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invalidate_dcache_range(addr, addr + info->data_buf_size);
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}
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static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
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{
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- uint32_t addr = (uint32_t)info->cmd_buf;
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+ uint32_t addr = (uintptr_t)info->cmd_buf;
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flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
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}
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@@ -773,7 +774,7 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
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if (status[i] == 0xff) {
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if (is_mx6dqp() || is_mx7() ||
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- is_mx6ul() || is_imx8m())
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+ is_mx6ul() || is_imx8() || is_imx8m())
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if (readl(&bch_regs->hw_bch_debug1))
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flag = 1;
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continue;
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@@ -1172,7 +1173,7 @@ int mxs_nand_setup_ecc(struct mtd_info *mtd)
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/* Set erase threshold to ecc strength for mx6ul, mx6qp and mx7 */
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if (is_mx6dqp() || is_mx7() ||
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- is_mx6ul() || is_imx8m())
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+ is_mx6ul() || is_imx8() || is_imx8m())
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writel(BCH_MODE_ERASE_THRESHOLD(geo->ecc_strength),
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&bch_regs->hw_bch_mode);
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@@ -1311,7 +1312,7 @@ int mxs_nand_init_spl(struct nand_chip *nand)
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nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
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nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
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- if (is_mx6sx() || is_mx7() || is_imx8m())
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+ if (is_mx6sx() || is_mx7() || is_imx8() || is_imx8m())
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nand_info->max_ecc_strength_supported = 62;
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else
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nand_info->max_ecc_strength_supported = 40;
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