regs-apbh.h 22 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Freescale i.MX28 APBH Register Definitions
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. *
  8. * Based on code from LTIB:
  9. * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  10. * Copyright 2020 NXP
  11. */
  12. #ifndef __REGS_APBH_H__
  13. #define __REGS_APBH_H__
  14. #include <asm/mach-imx/regs-common.h>
  15. #ifndef __ASSEMBLY__
  16. #if defined(CONFIG_MX23)
  17. struct mxs_apbh_regs {
  18. mxs_reg_32(hw_apbh_ctrl0)
  19. mxs_reg_32(hw_apbh_ctrl1)
  20. mxs_reg_32(hw_apbh_ctrl2)
  21. mxs_reg_32(hw_apbh_channel_ctrl)
  22. union {
  23. struct {
  24. mxs_reg_32(hw_apbh_ch_curcmdar)
  25. mxs_reg_32(hw_apbh_ch_nxtcmdar)
  26. mxs_reg_32(hw_apbh_ch_cmd)
  27. mxs_reg_32(hw_apbh_ch_bar)
  28. mxs_reg_32(hw_apbh_ch_sema)
  29. mxs_reg_32(hw_apbh_ch_debug1)
  30. mxs_reg_32(hw_apbh_ch_debug2)
  31. } ch[8];
  32. struct {
  33. mxs_reg_32(hw_apbh_ch0_curcmdar)
  34. mxs_reg_32(hw_apbh_ch0_nxtcmdar)
  35. mxs_reg_32(hw_apbh_ch0_cmd)
  36. mxs_reg_32(hw_apbh_ch0_bar)
  37. mxs_reg_32(hw_apbh_ch0_sema)
  38. mxs_reg_32(hw_apbh_ch0_debug1)
  39. mxs_reg_32(hw_apbh_ch0_debug2)
  40. mxs_reg_32(hw_apbh_ch1_curcmdar)
  41. mxs_reg_32(hw_apbh_ch1_nxtcmdar)
  42. mxs_reg_32(hw_apbh_ch1_cmd)
  43. mxs_reg_32(hw_apbh_ch1_bar)
  44. mxs_reg_32(hw_apbh_ch1_sema)
  45. mxs_reg_32(hw_apbh_ch1_debug1)
  46. mxs_reg_32(hw_apbh_ch1_debug2)
  47. mxs_reg_32(hw_apbh_ch2_curcmdar)
  48. mxs_reg_32(hw_apbh_ch2_nxtcmdar)
  49. mxs_reg_32(hw_apbh_ch2_cmd)
  50. mxs_reg_32(hw_apbh_ch2_bar)
  51. mxs_reg_32(hw_apbh_ch2_sema)
  52. mxs_reg_32(hw_apbh_ch2_debug1)
  53. mxs_reg_32(hw_apbh_ch2_debug2)
  54. mxs_reg_32(hw_apbh_ch3_curcmdar)
  55. mxs_reg_32(hw_apbh_ch3_nxtcmdar)
  56. mxs_reg_32(hw_apbh_ch3_cmd)
  57. mxs_reg_32(hw_apbh_ch3_bar)
  58. mxs_reg_32(hw_apbh_ch3_sema)
  59. mxs_reg_32(hw_apbh_ch3_debug1)
  60. mxs_reg_32(hw_apbh_ch3_debug2)
  61. mxs_reg_32(hw_apbh_ch4_curcmdar)
  62. mxs_reg_32(hw_apbh_ch4_nxtcmdar)
  63. mxs_reg_32(hw_apbh_ch4_cmd)
  64. mxs_reg_32(hw_apbh_ch4_bar)
  65. mxs_reg_32(hw_apbh_ch4_sema)
  66. mxs_reg_32(hw_apbh_ch4_debug1)
  67. mxs_reg_32(hw_apbh_ch4_debug2)
  68. mxs_reg_32(hw_apbh_ch5_curcmdar)
  69. mxs_reg_32(hw_apbh_ch5_nxtcmdar)
  70. mxs_reg_32(hw_apbh_ch5_cmd)
  71. mxs_reg_32(hw_apbh_ch5_bar)
  72. mxs_reg_32(hw_apbh_ch5_sema)
  73. mxs_reg_32(hw_apbh_ch5_debug1)
  74. mxs_reg_32(hw_apbh_ch5_debug2)
  75. mxs_reg_32(hw_apbh_ch6_curcmdar)
  76. mxs_reg_32(hw_apbh_ch6_nxtcmdar)
  77. mxs_reg_32(hw_apbh_ch6_cmd)
  78. mxs_reg_32(hw_apbh_ch6_bar)
  79. mxs_reg_32(hw_apbh_ch6_sema)
  80. mxs_reg_32(hw_apbh_ch6_debug1)
  81. mxs_reg_32(hw_apbh_ch6_debug2)
  82. mxs_reg_32(hw_apbh_ch7_curcmdar)
  83. mxs_reg_32(hw_apbh_ch7_nxtcmdar)
  84. mxs_reg_32(hw_apbh_ch7_cmd)
  85. mxs_reg_32(hw_apbh_ch7_bar)
  86. mxs_reg_32(hw_apbh_ch7_sema)
  87. mxs_reg_32(hw_apbh_ch7_debug1)
  88. mxs_reg_32(hw_apbh_ch7_debug2)
  89. };
  90. };
  91. mxs_reg_32(hw_apbh_version)
  92. };
  93. #else
  94. struct mxs_apbh_regs {
  95. mxs_reg_32(hw_apbh_ctrl0)
  96. mxs_reg_32(hw_apbh_ctrl1)
  97. mxs_reg_32(hw_apbh_ctrl2)
  98. mxs_reg_32(hw_apbh_channel_ctrl)
  99. mxs_reg_32(hw_apbh_devsel)
  100. mxs_reg_32(hw_apbh_dma_burst_size)
  101. mxs_reg_32(hw_apbh_debug)
  102. uint32_t reserved[36];
  103. union {
  104. struct {
  105. mxs_reg_32(hw_apbh_ch_curcmdar)
  106. mxs_reg_32(hw_apbh_ch_nxtcmdar)
  107. mxs_reg_32(hw_apbh_ch_cmd)
  108. mxs_reg_32(hw_apbh_ch_bar)
  109. mxs_reg_32(hw_apbh_ch_sema)
  110. mxs_reg_32(hw_apbh_ch_debug1)
  111. mxs_reg_32(hw_apbh_ch_debug2)
  112. } ch[16];
  113. struct {
  114. mxs_reg_32(hw_apbh_ch0_curcmdar)
  115. mxs_reg_32(hw_apbh_ch0_nxtcmdar)
  116. mxs_reg_32(hw_apbh_ch0_cmd)
  117. mxs_reg_32(hw_apbh_ch0_bar)
  118. mxs_reg_32(hw_apbh_ch0_sema)
  119. mxs_reg_32(hw_apbh_ch0_debug1)
  120. mxs_reg_32(hw_apbh_ch0_debug2)
  121. mxs_reg_32(hw_apbh_ch1_curcmdar)
  122. mxs_reg_32(hw_apbh_ch1_nxtcmdar)
  123. mxs_reg_32(hw_apbh_ch1_cmd)
  124. mxs_reg_32(hw_apbh_ch1_bar)
  125. mxs_reg_32(hw_apbh_ch1_sema)
  126. mxs_reg_32(hw_apbh_ch1_debug1)
  127. mxs_reg_32(hw_apbh_ch1_debug2)
  128. mxs_reg_32(hw_apbh_ch2_curcmdar)
  129. mxs_reg_32(hw_apbh_ch2_nxtcmdar)
  130. mxs_reg_32(hw_apbh_ch2_cmd)
  131. mxs_reg_32(hw_apbh_ch2_bar)
  132. mxs_reg_32(hw_apbh_ch2_sema)
  133. mxs_reg_32(hw_apbh_ch2_debug1)
  134. mxs_reg_32(hw_apbh_ch2_debug2)
  135. mxs_reg_32(hw_apbh_ch3_curcmdar)
  136. mxs_reg_32(hw_apbh_ch3_nxtcmdar)
  137. mxs_reg_32(hw_apbh_ch3_cmd)
  138. mxs_reg_32(hw_apbh_ch3_bar)
  139. mxs_reg_32(hw_apbh_ch3_sema)
  140. mxs_reg_32(hw_apbh_ch3_debug1)
  141. mxs_reg_32(hw_apbh_ch3_debug2)
  142. mxs_reg_32(hw_apbh_ch4_curcmdar)
  143. mxs_reg_32(hw_apbh_ch4_nxtcmdar)
  144. mxs_reg_32(hw_apbh_ch4_cmd)
  145. mxs_reg_32(hw_apbh_ch4_bar)
  146. mxs_reg_32(hw_apbh_ch4_sema)
  147. mxs_reg_32(hw_apbh_ch4_debug1)
  148. mxs_reg_32(hw_apbh_ch4_debug2)
  149. mxs_reg_32(hw_apbh_ch5_curcmdar)
  150. mxs_reg_32(hw_apbh_ch5_nxtcmdar)
  151. mxs_reg_32(hw_apbh_ch5_cmd)
  152. mxs_reg_32(hw_apbh_ch5_bar)
  153. mxs_reg_32(hw_apbh_ch5_sema)
  154. mxs_reg_32(hw_apbh_ch5_debug1)
  155. mxs_reg_32(hw_apbh_ch5_debug2)
  156. mxs_reg_32(hw_apbh_ch6_curcmdar)
  157. mxs_reg_32(hw_apbh_ch6_nxtcmdar)
  158. mxs_reg_32(hw_apbh_ch6_cmd)
  159. mxs_reg_32(hw_apbh_ch6_bar)
  160. mxs_reg_32(hw_apbh_ch6_sema)
  161. mxs_reg_32(hw_apbh_ch6_debug1)
  162. mxs_reg_32(hw_apbh_ch6_debug2)
  163. mxs_reg_32(hw_apbh_ch7_curcmdar)
  164. mxs_reg_32(hw_apbh_ch7_nxtcmdar)
  165. mxs_reg_32(hw_apbh_ch7_cmd)
  166. mxs_reg_32(hw_apbh_ch7_bar)
  167. mxs_reg_32(hw_apbh_ch7_sema)
  168. mxs_reg_32(hw_apbh_ch7_debug1)
  169. mxs_reg_32(hw_apbh_ch7_debug2)
  170. mxs_reg_32(hw_apbh_ch8_curcmdar)
  171. mxs_reg_32(hw_apbh_ch8_nxtcmdar)
  172. mxs_reg_32(hw_apbh_ch8_cmd)
  173. mxs_reg_32(hw_apbh_ch8_bar)
  174. mxs_reg_32(hw_apbh_ch8_sema)
  175. mxs_reg_32(hw_apbh_ch8_debug1)
  176. mxs_reg_32(hw_apbh_ch8_debug2)
  177. mxs_reg_32(hw_apbh_ch9_curcmdar)
  178. mxs_reg_32(hw_apbh_ch9_nxtcmdar)
  179. mxs_reg_32(hw_apbh_ch9_cmd)
  180. mxs_reg_32(hw_apbh_ch9_bar)
  181. mxs_reg_32(hw_apbh_ch9_sema)
  182. mxs_reg_32(hw_apbh_ch9_debug1)
  183. mxs_reg_32(hw_apbh_ch9_debug2)
  184. mxs_reg_32(hw_apbh_ch10_curcmdar)
  185. mxs_reg_32(hw_apbh_ch10_nxtcmdar)
  186. mxs_reg_32(hw_apbh_ch10_cmd)
  187. mxs_reg_32(hw_apbh_ch10_bar)
  188. mxs_reg_32(hw_apbh_ch10_sema)
  189. mxs_reg_32(hw_apbh_ch10_debug1)
  190. mxs_reg_32(hw_apbh_ch10_debug2)
  191. mxs_reg_32(hw_apbh_ch11_curcmdar)
  192. mxs_reg_32(hw_apbh_ch11_nxtcmdar)
  193. mxs_reg_32(hw_apbh_ch11_cmd)
  194. mxs_reg_32(hw_apbh_ch11_bar)
  195. mxs_reg_32(hw_apbh_ch11_sema)
  196. mxs_reg_32(hw_apbh_ch11_debug1)
  197. mxs_reg_32(hw_apbh_ch11_debug2)
  198. mxs_reg_32(hw_apbh_ch12_curcmdar)
  199. mxs_reg_32(hw_apbh_ch12_nxtcmdar)
  200. mxs_reg_32(hw_apbh_ch12_cmd)
  201. mxs_reg_32(hw_apbh_ch12_bar)
  202. mxs_reg_32(hw_apbh_ch12_sema)
  203. mxs_reg_32(hw_apbh_ch12_debug1)
  204. mxs_reg_32(hw_apbh_ch12_debug2)
  205. mxs_reg_32(hw_apbh_ch13_curcmdar)
  206. mxs_reg_32(hw_apbh_ch13_nxtcmdar)
  207. mxs_reg_32(hw_apbh_ch13_cmd)
  208. mxs_reg_32(hw_apbh_ch13_bar)
  209. mxs_reg_32(hw_apbh_ch13_sema)
  210. mxs_reg_32(hw_apbh_ch13_debug1)
  211. mxs_reg_32(hw_apbh_ch13_debug2)
  212. mxs_reg_32(hw_apbh_ch14_curcmdar)
  213. mxs_reg_32(hw_apbh_ch14_nxtcmdar)
  214. mxs_reg_32(hw_apbh_ch14_cmd)
  215. mxs_reg_32(hw_apbh_ch14_bar)
  216. mxs_reg_32(hw_apbh_ch14_sema)
  217. mxs_reg_32(hw_apbh_ch14_debug1)
  218. mxs_reg_32(hw_apbh_ch14_debug2)
  219. mxs_reg_32(hw_apbh_ch15_curcmdar)
  220. mxs_reg_32(hw_apbh_ch15_nxtcmdar)
  221. mxs_reg_32(hw_apbh_ch15_cmd)
  222. mxs_reg_32(hw_apbh_ch15_bar)
  223. mxs_reg_32(hw_apbh_ch15_sema)
  224. mxs_reg_32(hw_apbh_ch15_debug1)
  225. mxs_reg_32(hw_apbh_ch15_debug2)
  226. };
  227. };
  228. mxs_reg_32(hw_apbh_version)
  229. };
  230. #endif
  231. #endif
  232. #define APBH_CTRL0_SFTRST (1 << 31)
  233. #define APBH_CTRL0_CLKGATE (1 << 30)
  234. #define APBH_CTRL0_AHB_BURST8_EN (1 << 29)
  235. #define APBH_CTRL0_APB_BURST_EN (1 << 28)
  236. #if defined(CONFIG_MX23)
  237. #define APBH_CTRL0_RSVD0_MASK (0xf << 24)
  238. #define APBH_CTRL0_RSVD0_OFFSET 24
  239. #define APBH_CTRL0_RESET_CHANNEL_MASK (0xff << 16)
  240. #define APBH_CTRL0_RESET_CHANNEL_OFFSET 16
  241. #define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xff << 8)
  242. #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 8
  243. #define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x02
  244. #define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x04
  245. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x10
  246. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x20
  247. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x40
  248. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x80
  249. #elif defined(CONFIG_MX28)
  250. #define APBH_CTRL0_RSVD0_MASK (0xfff << 16)
  251. #define APBH_CTRL0_RSVD0_OFFSET 16
  252. #define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff
  253. #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
  254. #define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001
  255. #define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002
  256. #define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004
  257. #define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008
  258. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010
  259. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020
  260. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040
  261. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080
  262. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100
  263. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200
  264. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400
  265. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
  266. #define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
  267. #define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
  268. #elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
  269. #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
  270. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
  271. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
  272. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0004
  273. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0008
  274. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0010
  275. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0020
  276. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0040
  277. #define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0080
  278. #define APBH_CTRL0_CLKGATE_CHANNEL_SSP 0x0100
  279. #endif
  280. #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31)
  281. #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30)
  282. #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29)
  283. #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28)
  284. #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27)
  285. #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26)
  286. #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25)
  287. #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24)
  288. #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23)
  289. #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22)
  290. #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21)
  291. #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20)
  292. #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19)
  293. #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18)
  294. #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17)
  295. #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16)
  296. #define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16
  297. #define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16)
  298. #define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15)
  299. #define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14)
  300. #define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13)
  301. #define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12)
  302. #define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11)
  303. #define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10)
  304. #define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9)
  305. #define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8)
  306. #define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7)
  307. #define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6)
  308. #define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5)
  309. #define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4)
  310. #define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3)
  311. #define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2)
  312. #define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1)
  313. #define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0)
  314. #define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31)
  315. #define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30)
  316. #define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29)
  317. #define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28)
  318. #define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27)
  319. #define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26)
  320. #define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25)
  321. #define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24)
  322. #define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23)
  323. #define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22)
  324. #define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21)
  325. #define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20)
  326. #define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19)
  327. #define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18)
  328. #define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17)
  329. #define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16)
  330. #define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15)
  331. #define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14)
  332. #define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13)
  333. #define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12)
  334. #define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11)
  335. #define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10)
  336. #define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9)
  337. #define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8)
  338. #define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7)
  339. #define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6)
  340. #define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5)
  341. #define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4)
  342. #define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3)
  343. #define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2)
  344. #define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1)
  345. #define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0)
  346. #if defined(CONFIG_MX28)
  347. #define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16)
  348. #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16)
  349. #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16)
  350. #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16)
  351. #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16)
  352. #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16)
  353. #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16)
  354. #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16)
  355. #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16)
  356. #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16)
  357. #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16)
  358. #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16)
  359. #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16)
  360. #define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16)
  361. #define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16)
  362. #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff
  363. #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0
  364. #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001
  365. #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002
  366. #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004
  367. #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008
  368. #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010
  369. #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020
  370. #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040
  371. #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080
  372. #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100
  373. #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200
  374. #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400
  375. #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800
  376. #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000
  377. #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
  378. #endif
  379. /* Not on i.MX23 */
  380. #define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
  381. #if defined(CONFIG_MX23)
  382. #define APBH_DEVSEL_CH7_MASK (0xf << 28)
  383. #define APBH_DEVSEL_CH7_OFFSET 28
  384. #define APBH_DEVSEL_CH6_MASK (0xf << 24)
  385. #define APBH_DEVSEL_CH6_OFFSET 24
  386. #define APBH_DEVSEL_CH5_MASK (0xf << 20)
  387. #define APBH_DEVSEL_CH5_OFFSET 20
  388. #define APBH_DEVSEL_CH4_MASK (0xf << 16)
  389. #define APBH_DEVSEL_CH4_OFFSET 16
  390. #define APBH_DEVSEL_CH3_MASK (0xf << 12)
  391. #define APBH_DEVSEL_CH3_OFFSET 12
  392. #define APBH_DEVSEL_CH2_MASK (0xf << 8)
  393. #define APBH_DEVSEL_CH2_OFFSET 8
  394. #define APBH_DEVSEL_CH1_MASK (0xf << 4)
  395. #define APBH_DEVSEL_CH1_OFFSET 4
  396. #define APBH_DEVSEL_CH0_MASK (0xf << 0)
  397. #define APBH_DEVSEL_CH0_OFFSET 0
  398. #elif defined(CONFIG_MX28)
  399. #define APBH_DEVSEL_CH15_MASK (0x3 << 30)
  400. #define APBH_DEVSEL_CH15_OFFSET 30
  401. #define APBH_DEVSEL_CH14_MASK (0x3 << 28)
  402. #define APBH_DEVSEL_CH14_OFFSET 28
  403. #define APBH_DEVSEL_CH13_MASK (0x3 << 26)
  404. #define APBH_DEVSEL_CH13_OFFSET 26
  405. #define APBH_DEVSEL_CH12_MASK (0x3 << 24)
  406. #define APBH_DEVSEL_CH12_OFFSET 24
  407. #define APBH_DEVSEL_CH11_MASK (0x3 << 22)
  408. #define APBH_DEVSEL_CH11_OFFSET 22
  409. #define APBH_DEVSEL_CH10_MASK (0x3 << 20)
  410. #define APBH_DEVSEL_CH10_OFFSET 20
  411. #define APBH_DEVSEL_CH9_MASK (0x3 << 18)
  412. #define APBH_DEVSEL_CH9_OFFSET 18
  413. #define APBH_DEVSEL_CH8_MASK (0x3 << 16)
  414. #define APBH_DEVSEL_CH8_OFFSET 16
  415. #define APBH_DEVSEL_CH7_MASK (0x3 << 14)
  416. #define APBH_DEVSEL_CH7_OFFSET 14
  417. #define APBH_DEVSEL_CH6_MASK (0x3 << 12)
  418. #define APBH_DEVSEL_CH6_OFFSET 12
  419. #define APBH_DEVSEL_CH5_MASK (0x3 << 10)
  420. #define APBH_DEVSEL_CH5_OFFSET 10
  421. #define APBH_DEVSEL_CH4_MASK (0x3 << 8)
  422. #define APBH_DEVSEL_CH4_OFFSET 8
  423. #define APBH_DEVSEL_CH3_MASK (0x3 << 6)
  424. #define APBH_DEVSEL_CH3_OFFSET 6
  425. #define APBH_DEVSEL_CH2_MASK (0x3 << 4)
  426. #define APBH_DEVSEL_CH2_OFFSET 4
  427. #define APBH_DEVSEL_CH1_MASK (0x3 << 2)
  428. #define APBH_DEVSEL_CH1_OFFSET 2
  429. #define APBH_DEVSEL_CH0_MASK (0x3 << 0)
  430. #define APBH_DEVSEL_CH0_OFFSET 0
  431. #endif
  432. #if defined(CONFIG_MX28)
  433. #define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30)
  434. #define APBH_DMA_BURST_SIZE_CH15_OFFSET 30
  435. #define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28)
  436. #define APBH_DMA_BURST_SIZE_CH14_OFFSET 28
  437. #define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26)
  438. #define APBH_DMA_BURST_SIZE_CH13_OFFSET 26
  439. #define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24)
  440. #define APBH_DMA_BURST_SIZE_CH12_OFFSET 24
  441. #define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22)
  442. #define APBH_DMA_BURST_SIZE_CH11_OFFSET 22
  443. #define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20)
  444. #define APBH_DMA_BURST_SIZE_CH10_OFFSET 20
  445. #define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18)
  446. #define APBH_DMA_BURST_SIZE_CH9_OFFSET 18
  447. #define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16)
  448. #define APBH_DMA_BURST_SIZE_CH8_OFFSET 16
  449. #define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16)
  450. #define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16)
  451. #define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16)
  452. #define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14)
  453. #define APBH_DMA_BURST_SIZE_CH7_OFFSET 14
  454. #define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12)
  455. #define APBH_DMA_BURST_SIZE_CH6_OFFSET 12
  456. #define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10)
  457. #define APBH_DMA_BURST_SIZE_CH5_OFFSET 10
  458. #define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8)
  459. #define APBH_DMA_BURST_SIZE_CH4_OFFSET 8
  460. #define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6)
  461. #define APBH_DMA_BURST_SIZE_CH3_OFFSET 6
  462. #define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6)
  463. #define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6)
  464. #define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6)
  465. #define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4)
  466. #define APBH_DMA_BURST_SIZE_CH2_OFFSET 4
  467. #define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4)
  468. #define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4)
  469. #define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4)
  470. #define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2)
  471. #define APBH_DMA_BURST_SIZE_CH1_OFFSET 2
  472. #define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2)
  473. #define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2)
  474. #define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2)
  475. #define APBH_DMA_BURST_SIZE_CH0_MASK 0x3
  476. #define APBH_DMA_BURST_SIZE_CH0_OFFSET 0
  477. #define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0
  478. #define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1
  479. #define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2
  480. #define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0)
  481. #endif
  482. #define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff
  483. #define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0
  484. #define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff
  485. #define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0
  486. #define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16)
  487. #define APBH_CHn_CMD_XFER_COUNT_OFFSET 16
  488. #define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12)
  489. #define APBH_CHn_CMD_CMDWORDS_OFFSET 12
  490. #define APBH_CHn_CMD_HALTONTERMINATE (1 << 8)
  491. #define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7)
  492. #define APBH_CHn_CMD_SEMAPHORE (1 << 6)
  493. #define APBH_CHn_CMD_NANDWAIT4READY (1 << 5)
  494. #define APBH_CHn_CMD_NANDLOCK (1 << 4)
  495. #define APBH_CHn_CMD_IRQONCMPLT (1 << 3)
  496. #define APBH_CHn_CMD_CHAIN (1 << 2)
  497. #define APBH_CHn_CMD_COMMAND_MASK 0x3
  498. #define APBH_CHn_CMD_COMMAND_OFFSET 0
  499. #define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0
  500. #define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1
  501. #define APBH_CHn_CMD_COMMAND_DMA_READ 0x2
  502. #define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3
  503. #define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff
  504. #define APBH_CHn_BAR_ADDRESS_OFFSET 0
  505. #define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24)
  506. #define APBH_CHn_SEMA_RSVD2_OFFSET 24
  507. #define APBH_CHn_SEMA_PHORE_MASK (0xff << 16)
  508. #define APBH_CHn_SEMA_PHORE_OFFSET 16
  509. #define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8)
  510. #define APBH_CHn_SEMA_RSVD1_OFFSET 8
  511. #define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0)
  512. #define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0
  513. #define APBH_CHn_DEBUG1_REQ (1 << 31)
  514. #define APBH_CHn_DEBUG1_BURST (1 << 30)
  515. #define APBH_CHn_DEBUG1_KICK (1 << 29)
  516. #define APBH_CHn_DEBUG1_END (1 << 28)
  517. #define APBH_CHn_DEBUG1_SENSE (1 << 27)
  518. #define APBH_CHn_DEBUG1_READY (1 << 26)
  519. #define APBH_CHn_DEBUG1_LOCK (1 << 25)
  520. #define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24)
  521. #define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23)
  522. #define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22)
  523. #define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21)
  524. #define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20)
  525. #define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5)
  526. #define APBH_CHn_DEBUG1_RSVD1_OFFSET 5
  527. #define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f
  528. #define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0
  529. #define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00
  530. #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01
  531. #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02
  532. #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03
  533. #define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04
  534. #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05
  535. #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06
  536. #define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07
  537. #define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08
  538. #define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09
  539. #define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c
  540. #define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d
  541. #define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e
  542. #define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f
  543. #define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14
  544. #define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15
  545. #define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c
  546. #define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d
  547. #define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e
  548. #define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f
  549. #define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16)
  550. #define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16
  551. #define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff
  552. #define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0
  553. #define APBH_VERSION_MAJOR_MASK (0xff << 24)
  554. #define APBH_VERSION_MAJOR_OFFSET 24
  555. #define APBH_VERSION_MINOR_MASK (0xff << 16)
  556. #define APBH_VERSION_MINOR_OFFSET 16
  557. #define APBH_VERSION_STEP_MASK 0xffff
  558. #define APBH_VERSION_STEP_OFFSET 0
  559. #endif /* __REGS_APBH_H__ */