Kconfig 12 KB

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  1. menuconfig MTD_RAW_NAND
  2. bool "Raw NAND Device Support"
  3. if MTD_RAW_NAND
  4. config SYS_NAND_SELF_INIT
  5. bool
  6. help
  7. This option, if enabled, provides more flexible and linux-like
  8. NAND initialization process.
  9. config SYS_NAND_DRIVER_ECC_LAYOUT
  10. bool
  11. help
  12. Omit standard ECC layouts to safe space. Select this if your driver
  13. is known to provide its own ECC layout.
  14. config SYS_NAND_USE_FLASH_BBT
  15. bool "Enable BBT (Bad Block Table) support"
  16. help
  17. Enable the BBT (Bad Block Table) usage.
  18. config NAND_ATMEL
  19. bool "Support Atmel NAND controller"
  20. imply SYS_NAND_USE_FLASH_BBT
  21. help
  22. Enable this driver for NAND flash platforms using an Atmel NAND
  23. controller.
  24. if NAND_ATMEL
  25. config ATMEL_NAND_HWECC
  26. bool "Atmel Hardware ECC"
  27. default n
  28. config ATMEL_NAND_HW_PMECC
  29. bool "Atmel Programmable Multibit ECC (PMECC)"
  30. select ATMEL_NAND_HWECC
  31. default n
  32. help
  33. The Programmable Multibit ECC (PMECC) controller is a programmable
  34. binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
  35. config PMECC_CAP
  36. int "PMECC Correctable ECC Bits"
  37. depends on ATMEL_NAND_HW_PMECC
  38. default 2
  39. help
  40. Correctable ECC bits, can be 2, 4, 8, 12, and 24.
  41. config PMECC_SECTOR_SIZE
  42. int "PMECC Sector Size"
  43. depends on ATMEL_NAND_HW_PMECC
  44. default 512
  45. help
  46. Sector size, in bytes, can be 512 or 1024.
  47. config SPL_GENERATE_ATMEL_PMECC_HEADER
  48. bool "Atmel PMECC Header Generation"
  49. select ATMEL_NAND_HWECC
  50. select ATMEL_NAND_HW_PMECC
  51. default n
  52. help
  53. Generate Programmable Multibit ECC (PMECC) header for SPL image.
  54. endif
  55. config NAND_BRCMNAND
  56. bool "Support Broadcom NAND controller"
  57. depends on OF_CONTROL && DM && DM_MTD
  58. help
  59. Enable the driver for NAND flash on platforms using a Broadcom NAND
  60. controller.
  61. config NAND_BRCMNAND_6368
  62. bool "Support Broadcom NAND controller on bcm6368"
  63. depends on NAND_BRCMNAND && ARCH_BMIPS
  64. help
  65. Enable support for broadcom nand driver on bcm6368.
  66. config NAND_BRCMNAND_68360
  67. bool "Support Broadcom NAND controller on bcm68360"
  68. depends on NAND_BRCMNAND && ARCH_BCM68360
  69. help
  70. Enable support for broadcom nand driver on bcm68360.
  71. config NAND_BRCMNAND_6838
  72. bool "Support Broadcom NAND controller on bcm6838"
  73. depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
  74. help
  75. Enable support for broadcom nand driver on bcm6838.
  76. config NAND_BRCMNAND_6858
  77. bool "Support Broadcom NAND controller on bcm6858"
  78. depends on NAND_BRCMNAND && ARCH_BCM6858
  79. help
  80. Enable support for broadcom nand driver on bcm6858.
  81. config NAND_BRCMNAND_63158
  82. bool "Support Broadcom NAND controller on bcm63158"
  83. depends on NAND_BRCMNAND && ARCH_BCM63158
  84. help
  85. Enable support for broadcom nand driver on bcm63158.
  86. config NAND_DAVINCI
  87. bool "Support TI Davinci NAND controller"
  88. help
  89. Enable this driver for NAND flash controllers available in TI Davinci
  90. and Keystone2 platforms
  91. config NAND_DENALI
  92. bool
  93. select SYS_NAND_SELF_INIT
  94. imply CMD_NAND
  95. config NAND_DENALI_DT
  96. bool "Support Denali NAND controller as a DT device"
  97. select NAND_DENALI
  98. depends on OF_CONTROL && DM_MTD
  99. help
  100. Enable the driver for NAND flash on platforms using a Denali NAND
  101. controller as a DT device.
  102. config NAND_DENALI_SPARE_AREA_SKIP_BYTES
  103. int "Number of bytes skipped in OOB area"
  104. depends on NAND_DENALI
  105. range 0 63
  106. help
  107. This option specifies the number of bytes to skip from the beginning
  108. of OOB area before last ECC sector data starts. This is potentially
  109. used to preserve the bad block marker in the OOB area.
  110. config NAND_LPC32XX_SLC
  111. bool "Support LPC32XX_SLC controller"
  112. help
  113. Enable the LPC32XX SLC NAND controller.
  114. config NAND_OMAP_GPMC
  115. bool "Support OMAP GPMC NAND controller"
  116. depends on ARCH_OMAP2PLUS
  117. help
  118. Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
  119. GPMC controller is used for parallel NAND flash devices, and can
  120. do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
  121. and BCH16 ECC algorithms.
  122. config NAND_OMAP_GPMC_PREFETCH
  123. bool "Enable GPMC Prefetch"
  124. depends on NAND_OMAP_GPMC
  125. default y
  126. help
  127. On OMAP platforms that use the GPMC controller
  128. (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
  129. uses the prefetch mode to speed up read operations.
  130. config NAND_OMAP_ELM
  131. bool "Enable ELM driver for OMAPxx and AMxx platforms."
  132. depends on NAND_OMAP_GPMC && !OMAP34XX
  133. help
  134. ELM controller is used for ECC error detection (not ECC calculation)
  135. of BCH4, BCH8 and BCH16 ECC algorithms.
  136. Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
  137. thus such SoC platforms need to depend on software library for ECC error
  138. detection. However ECC calculation on such plaforms would still be
  139. done by GPMC controller.
  140. config NAND_VF610_NFC
  141. bool "Support for Freescale NFC for VF610"
  142. select SYS_NAND_SELF_INIT
  143. select SYS_NAND_DRIVER_ECC_LAYOUT
  144. imply CMD_NAND
  145. help
  146. Enables support for NAND Flash Controller on some Freescale
  147. processors like the VF610, MCF54418 or Kinetis K70.
  148. The driver supports a maximum 2k page size. The driver
  149. currently does not support hardware ECC.
  150. if NAND_VF610_NFC
  151. config NAND_VF610_NFC_DT
  152. bool "Support Vybrid's vf610 NAND controller as a DT device"
  153. depends on OF_CONTROL && DM_MTD
  154. help
  155. Enable the driver for Vybrid's vf610 NAND flash on platforms
  156. using device tree.
  157. choice
  158. prompt "Hardware ECC strength"
  159. depends on NAND_VF610_NFC
  160. default SYS_NAND_VF610_NFC_45_ECC_BYTES
  161. help
  162. Select the ECC strength used in the hardware BCH ECC block.
  163. config SYS_NAND_VF610_NFC_45_ECC_BYTES
  164. bool "24-error correction (45 ECC bytes)"
  165. config SYS_NAND_VF610_NFC_60_ECC_BYTES
  166. bool "32-error correction (60 ECC bytes)"
  167. endchoice
  168. endif
  169. config NAND_PXA3XX
  170. bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
  171. select SYS_NAND_SELF_INIT
  172. imply CMD_NAND
  173. help
  174. This enables the driver for the NAND flash device found on
  175. PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
  176. config NAND_SUNXI
  177. bool "Support for NAND on Allwinner SoCs"
  178. default ARCH_SUNXI
  179. depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
  180. select SYS_NAND_SELF_INIT
  181. select SYS_NAND_U_BOOT_LOCATIONS
  182. select SPL_NAND_SUPPORT
  183. imply CMD_NAND
  184. ---help---
  185. Enable support for NAND. This option enables the standard and
  186. SPL drivers.
  187. The SPL driver only supports reading from the NAND using DMA
  188. transfers.
  189. if NAND_SUNXI
  190. config NAND_SUNXI_SPL_ECC_STRENGTH
  191. int "Allwinner NAND SPL ECC Strength"
  192. default 64
  193. config NAND_SUNXI_SPL_ECC_SIZE
  194. int "Allwinner NAND SPL ECC Step Size"
  195. default 1024
  196. config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
  197. int "Allwinner NAND SPL Usable Page Size"
  198. default 1024
  199. endif
  200. config NAND_ARASAN
  201. bool "Configure Arasan Nand"
  202. select SYS_NAND_SELF_INIT
  203. select DM_MTD
  204. imply CMD_NAND
  205. help
  206. This enables Nand driver support for Arasan nand flash
  207. controller. This uses the hardware ECC for read and
  208. write operations.
  209. config NAND_MXC
  210. bool "MXC NAND support"
  211. depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
  212. imply CMD_NAND
  213. help
  214. This enables the NAND driver for the NAND flash controller on the
  215. i.MX27 / i.MX31 / i.MX5 rocessors.
  216. config NAND_MXS
  217. bool "MXS NAND support"
  218. depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
  219. select SYS_NAND_SELF_INIT
  220. imply CMD_NAND
  221. select APBH_DMA
  222. select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
  223. select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
  224. help
  225. This enables NAND driver for the NAND flash controller on the
  226. MXS processors.
  227. if NAND_MXS
  228. config NAND_MXS_DT
  229. bool "Support MXS NAND controller as a DT device"
  230. depends on OF_CONTROL && DM_MTD
  231. help
  232. Enable the driver for MXS NAND flash on platforms using
  233. device tree.
  234. config NAND_MXS_USE_MINIMUM_ECC
  235. bool "Use minimum ECC strength supported by the controller"
  236. default false
  237. endif
  238. config NAND_ZYNQ
  239. bool "Support for Zynq Nand controller"
  240. select SYS_NAND_SELF_INIT
  241. select DM_MTD
  242. imply CMD_NAND
  243. help
  244. This enables Nand driver support for Nand flash controller
  245. found on Zynq SoC.
  246. config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
  247. bool "Enable use of 1st stage bootloader timing for NAND"
  248. depends on NAND_ZYNQ
  249. help
  250. This flag prevent U-boot reconfigure NAND flash controller and reuse
  251. the NAND timing from 1st stage bootloader.
  252. config NAND_STM32_FMC2
  253. bool "Support for NAND controller on STM32MP SoCs"
  254. depends on ARCH_STM32MP
  255. select SYS_NAND_SELF_INIT
  256. imply CMD_NAND
  257. help
  258. Enables support for NAND Flash chips on SoCs containing the FMC2
  259. NAND controller. This controller is found on STM32MP SoCs.
  260. The controller supports a maximum 8k page size and supports
  261. a maximum 8-bit correction error per sector of 512 bytes.
  262. comment "Generic NAND options"
  263. config SYS_NAND_BLOCK_SIZE
  264. hex "NAND chip eraseblock size"
  265. depends on ARCH_SUNXI
  266. help
  267. Number of data bytes in one eraseblock for the NAND chip on the
  268. board. This is the multiple of NAND_PAGE_SIZE and the number of
  269. pages.
  270. config SYS_NAND_PAGE_SIZE
  271. hex "NAND chip page size"
  272. depends on ARCH_SUNXI
  273. help
  274. Number of data bytes in one page for the NAND chip on the
  275. board, not including the OOB area.
  276. config SYS_NAND_OOBSIZE
  277. hex "NAND chip OOB size"
  278. depends on ARCH_SUNXI
  279. help
  280. Number of bytes in the Out-Of-Band area for the NAND chip on
  281. the board.
  282. # Enhance depends when converting drivers to Kconfig which use this config
  283. # option (mxc_nand, ndfc, omap_gpmc).
  284. config SYS_NAND_BUSWIDTH_16BIT
  285. bool "Use 16-bit NAND interface"
  286. depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
  287. help
  288. Indicates that NAND device has 16-bit wide data-bus. In absence of this
  289. config, bus-width of NAND device is assumed to be either 8-bit and later
  290. determined by reading ONFI params.
  291. Above config is useful when NAND device's bus-width information cannot
  292. be determined from on-chip ONFI params, like in following scenarios:
  293. - SPL boot does not support reading of ONFI parameters. This is done to
  294. keep SPL code foot-print small.
  295. - In current U-Boot flow using nand_init(), driver initialization
  296. happens in board_nand_init() which is called before any device probe
  297. (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
  298. not available while configuring controller. So a static CONFIG_NAND_xx
  299. is needed to know the device's bus-width in advance.
  300. config SYS_NAND_MAX_CHIPS
  301. int "NAND max chips"
  302. default 1
  303. depends on NAND_ARASAN
  304. help
  305. The maximum number of NAND chips per device to be supported.
  306. if SPL
  307. config SYS_NAND_U_BOOT_LOCATIONS
  308. bool "Define U-boot binaries locations in NAND"
  309. help
  310. Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
  311. This option should not be enabled when compiling U-boot for boards
  312. defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
  313. file.
  314. config SYS_NAND_U_BOOT_OFFS
  315. hex "Location in NAND to read U-Boot from"
  316. default 0x800000 if NAND_SUNXI
  317. depends on SYS_NAND_U_BOOT_LOCATIONS
  318. help
  319. Set the offset from the start of the nand where u-boot should be
  320. loaded from.
  321. config SYS_NAND_U_BOOT_OFFS_REDUND
  322. hex "Location in NAND to read U-Boot from"
  323. default SYS_NAND_U_BOOT_OFFS
  324. depends on SYS_NAND_U_BOOT_LOCATIONS
  325. help
  326. Set the offset from the start of the nand where the redundant u-boot
  327. should be loaded from.
  328. config SPL_NAND_AM33XX_BCH
  329. bool "Enables SPL-NAND driver which supports ELM based"
  330. depends on NAND_OMAP_GPMC && !OMAP34XX
  331. default y
  332. help
  333. Hardware ECC correction. This is useful for platforms which have ELM
  334. hardware engine and use NAND boot mode.
  335. Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
  336. so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
  337. SPL-NAND driver with software ECC correction support.
  338. config SPL_NAND_DENALI
  339. bool "Support Denali NAND controller for SPL"
  340. help
  341. This is a small implementation of the Denali NAND controller
  342. for use on SPL.
  343. config SPL_NAND_SIMPLE
  344. bool "Use simple SPL NAND driver"
  345. depends on !SPL_NAND_AM33XX_BCH
  346. help
  347. Support for NAND boot using simple NAND drivers that
  348. expose the cmd_ctrl() interface.
  349. endif
  350. endif # if NAND