mxs_nand.c 43 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 NAND flash driver
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. *
  8. * Based on code from LTIB:
  9. * Freescale GPMI NFC NAND Flash Driver
  10. *
  11. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  12. * Copyright (C) 2008 Embedded Alley Solutions, Inc.
  13. * Copyright 2017-2019 NXP
  14. */
  15. #include <common.h>
  16. #include <cpu_func.h>
  17. #include <dm.h>
  18. #include <linux/mtd/rawnand.h>
  19. #include <linux/sizes.h>
  20. #include <linux/types.h>
  21. #include <malloc.h>
  22. #include <linux/errno.h>
  23. #include <asm/io.h>
  24. #include <asm/arch/clock.h>
  25. #include <asm/arch/imx-regs.h>
  26. #include <asm/mach-imx/regs-bch.h>
  27. #include <asm/mach-imx/regs-gpmi.h>
  28. #include <asm/arch/sys_proto.h>
  29. #include <mxs_nand.h>
  30. #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
  31. #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || \
  32. defined(CONFIG_IMX8M)
  33. #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
  34. #else
  35. #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
  36. #endif
  37. #define MXS_NAND_METADATA_SIZE 10
  38. #define MXS_NAND_BITS_PER_ECC_LEVEL 13
  39. #if !defined(CONFIG_SYS_CACHELINE_SIZE) || CONFIG_SYS_CACHELINE_SIZE < 32
  40. #define MXS_NAND_COMMAND_BUFFER_SIZE 32
  41. #else
  42. #define MXS_NAND_COMMAND_BUFFER_SIZE CONFIG_SYS_CACHELINE_SIZE
  43. #endif
  44. #define MXS_NAND_BCH_TIMEOUT 10000
  45. struct nand_ecclayout fake_ecc_layout;
  46. /*
  47. * Cache management functions
  48. */
  49. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  50. static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
  51. {
  52. uint32_t addr = (uintptr_t)info->data_buf;
  53. flush_dcache_range(addr, addr + info->data_buf_size);
  54. }
  55. static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
  56. {
  57. uint32_t addr = (uintptr_t)info->data_buf;
  58. invalidate_dcache_range(addr, addr + info->data_buf_size);
  59. }
  60. static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
  61. {
  62. uint32_t addr = (uintptr_t)info->cmd_buf;
  63. flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
  64. }
  65. #else
  66. static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
  67. static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
  68. static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
  69. #endif
  70. static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
  71. {
  72. struct mxs_dma_desc *desc;
  73. if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
  74. printf("MXS NAND: Too many DMA descriptors requested\n");
  75. return NULL;
  76. }
  77. desc = info->desc[info->desc_index];
  78. info->desc_index++;
  79. return desc;
  80. }
  81. static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
  82. {
  83. int i;
  84. struct mxs_dma_desc *desc;
  85. for (i = 0; i < info->desc_index; i++) {
  86. desc = info->desc[i];
  87. memset(desc, 0, sizeof(struct mxs_dma_desc));
  88. desc->address = (dma_addr_t)desc;
  89. }
  90. info->desc_index = 0;
  91. }
  92. static uint32_t mxs_nand_aux_status_offset(void)
  93. {
  94. return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
  95. }
  96. static inline bool mxs_nand_bbm_in_data_chunk(struct bch_geometry *geo, struct mtd_info *mtd,
  97. unsigned int *chunk_num)
  98. {
  99. unsigned int i, j;
  100. if (geo->ecc_chunk0_size != geo->ecc_chunkn_size) {
  101. dev_err(this->dev, "The size of chunk0 must equal to chunkn\n");
  102. return false;
  103. }
  104. i = (mtd->writesize * 8 - MXS_NAND_METADATA_SIZE * 8) /
  105. (geo->gf_len * geo->ecc_strength +
  106. geo->ecc_chunkn_size * 8);
  107. j = (mtd->writesize * 8 - MXS_NAND_METADATA_SIZE * 8) -
  108. (geo->gf_len * geo->ecc_strength +
  109. geo->ecc_chunkn_size * 8) * i;
  110. if (j < geo->ecc_chunkn_size * 8) {
  111. *chunk_num = i + 1;
  112. dev_dbg(this->dev, "Set ecc to %d and bbm in chunk %d\n",
  113. geo->ecc_strength, *chunk_num);
  114. return true;
  115. }
  116. return false;
  117. }
  118. static inline int mxs_nand_calc_ecc_layout_by_info(struct bch_geometry *geo,
  119. struct mtd_info *mtd,
  120. unsigned int ecc_strength,
  121. unsigned int ecc_step)
  122. {
  123. struct nand_chip *chip = mtd_to_nand(mtd);
  124. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  125. unsigned int block_mark_bit_offset;
  126. switch (ecc_step) {
  127. case SZ_512:
  128. geo->gf_len = 13;
  129. break;
  130. case SZ_1K:
  131. geo->gf_len = 14;
  132. break;
  133. default:
  134. return -EINVAL;
  135. }
  136. geo->ecc_chunk0_size = ecc_step;
  137. geo->ecc_chunkn_size = ecc_step;
  138. geo->ecc_strength = round_up(ecc_strength, 2);
  139. /* Keep the C >= O */
  140. if (geo->ecc_chunkn_size < mtd->oobsize)
  141. return -EINVAL;
  142. if (geo->ecc_strength > nand_info->max_ecc_strength_supported)
  143. return -EINVAL;
  144. geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunkn_size;
  145. /* For bit swap. */
  146. block_mark_bit_offset = mtd->writesize * 8 -
  147. (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - 1)
  148. + MXS_NAND_METADATA_SIZE * 8);
  149. geo->block_mark_byte_offset = block_mark_bit_offset / 8;
  150. geo->block_mark_bit_offset = block_mark_bit_offset % 8;
  151. return 0;
  152. }
  153. static inline int mxs_nand_legacy_calc_ecc_layout(struct bch_geometry *geo,
  154. struct mtd_info *mtd)
  155. {
  156. struct nand_chip *chip = mtd_to_nand(mtd);
  157. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  158. unsigned int block_mark_bit_offset;
  159. /* The default for the length of Galois Field. */
  160. geo->gf_len = 13;
  161. /* The default for chunk size. */
  162. geo->ecc_chunk0_size = 512;
  163. geo->ecc_chunkn_size = 512;
  164. if (geo->ecc_chunkn_size < mtd->oobsize) {
  165. geo->gf_len = 14;
  166. geo->ecc_chunk0_size *= 2;
  167. geo->ecc_chunkn_size *= 2;
  168. }
  169. geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunkn_size;
  170. /*
  171. * Determine the ECC layout with the formula:
  172. * ECC bits per chunk = (total page spare data bits) /
  173. * (bits per ECC level) / (chunks per page)
  174. * where:
  175. * total page spare data bits =
  176. * (page oob size - meta data size) * (bits per byte)
  177. */
  178. geo->ecc_strength = ((mtd->oobsize - MXS_NAND_METADATA_SIZE) * 8)
  179. / (geo->gf_len * geo->ecc_chunk_count);
  180. geo->ecc_strength = min(round_down(geo->ecc_strength, 2),
  181. nand_info->max_ecc_strength_supported);
  182. block_mark_bit_offset = mtd->writesize * 8 -
  183. (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - 1)
  184. + MXS_NAND_METADATA_SIZE * 8);
  185. geo->block_mark_byte_offset = block_mark_bit_offset / 8;
  186. geo->block_mark_bit_offset = block_mark_bit_offset % 8;
  187. return 0;
  188. }
  189. static inline int mxs_nand_calc_ecc_for_large_oob(struct bch_geometry *geo,
  190. struct mtd_info *mtd)
  191. {
  192. struct nand_chip *chip = mtd_to_nand(mtd);
  193. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  194. unsigned int block_mark_bit_offset;
  195. unsigned int max_ecc;
  196. unsigned int bbm_chunk;
  197. unsigned int i;
  198. /* sanity check for the minimum ecc nand required */
  199. if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0))
  200. return -EINVAL;
  201. geo->ecc_strength = chip->ecc_strength_ds;
  202. /* calculate the maximum ecc platform can support*/
  203. geo->gf_len = 14;
  204. geo->ecc_chunk0_size = 1024;
  205. geo->ecc_chunkn_size = 1024;
  206. geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunkn_size;
  207. max_ecc = ((mtd->oobsize - MXS_NAND_METADATA_SIZE) * 8)
  208. / (geo->gf_len * geo->ecc_chunk_count);
  209. max_ecc = min(round_down(max_ecc, 2),
  210. nand_info->max_ecc_strength_supported);
  211. /* search a supported ecc strength that makes bbm */
  212. /* located in data chunk */
  213. geo->ecc_strength = chip->ecc_strength_ds;
  214. while (!(geo->ecc_strength > max_ecc)) {
  215. if (mxs_nand_bbm_in_data_chunk(geo, mtd, &bbm_chunk))
  216. break;
  217. geo->ecc_strength += 2;
  218. }
  219. /* if none of them works, keep using the minimum ecc */
  220. /* nand required but changing ecc page layout */
  221. if (geo->ecc_strength > max_ecc) {
  222. geo->ecc_strength = chip->ecc_strength_ds;
  223. /* add extra ecc for meta data */
  224. geo->ecc_chunk0_size = 0;
  225. geo->ecc_chunk_count = (mtd->writesize / geo->ecc_chunkn_size) + 1;
  226. geo->ecc_for_meta = 1;
  227. /* check if oob can afford this extra ecc chunk */
  228. if (mtd->oobsize * 8 < MXS_NAND_METADATA_SIZE * 8 +
  229. geo->gf_len * geo->ecc_strength
  230. * geo->ecc_chunk_count) {
  231. printf("unsupported NAND chip with new layout\n");
  232. return -EINVAL;
  233. }
  234. /* calculate in which chunk bbm located */
  235. bbm_chunk = (mtd->writesize * 8 - MXS_NAND_METADATA_SIZE * 8 -
  236. geo->gf_len * geo->ecc_strength) /
  237. (geo->gf_len * geo->ecc_strength +
  238. geo->ecc_chunkn_size * 8) + 1;
  239. }
  240. /* calculate the number of ecc chunk behind the bbm */
  241. i = (mtd->writesize / geo->ecc_chunkn_size) - bbm_chunk + 1;
  242. block_mark_bit_offset = mtd->writesize * 8 -
  243. (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - i)
  244. + MXS_NAND_METADATA_SIZE * 8);
  245. geo->block_mark_byte_offset = block_mark_bit_offset / 8;
  246. geo->block_mark_bit_offset = block_mark_bit_offset % 8;
  247. return 0;
  248. }
  249. /*
  250. * Wait for BCH complete IRQ and clear the IRQ
  251. */
  252. static int mxs_nand_wait_for_bch_complete(struct mxs_nand_info *nand_info)
  253. {
  254. int timeout = MXS_NAND_BCH_TIMEOUT;
  255. int ret;
  256. ret = mxs_wait_mask_set(&nand_info->bch_regs->hw_bch_ctrl_reg,
  257. BCH_CTRL_COMPLETE_IRQ, timeout);
  258. writel(BCH_CTRL_COMPLETE_IRQ, &nand_info->bch_regs->hw_bch_ctrl_clr);
  259. return ret;
  260. }
  261. /*
  262. * This is the function that we install in the cmd_ctrl function pointer of the
  263. * owning struct nand_chip. The only functions in the reference implementation
  264. * that use these functions pointers are cmdfunc and select_chip.
  265. *
  266. * In this driver, we implement our own select_chip, so this function will only
  267. * be called by the reference implementation's cmdfunc. For this reason, we can
  268. * ignore the chip enable bit and concentrate only on sending bytes to the NAND
  269. * Flash.
  270. */
  271. static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
  272. {
  273. struct nand_chip *nand = mtd_to_nand(mtd);
  274. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  275. struct mxs_dma_desc *d;
  276. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  277. int ret;
  278. /*
  279. * If this condition is true, something is _VERY_ wrong in MTD
  280. * subsystem!
  281. */
  282. if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
  283. printf("MXS NAND: Command queue too long\n");
  284. return;
  285. }
  286. /*
  287. * Every operation begins with a command byte and a series of zero or
  288. * more address bytes. These are distinguished by either the Address
  289. * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
  290. * asserted. When MTD is ready to execute the command, it will
  291. * deasert both latch enables.
  292. *
  293. * Rather than run a separate DMA operation for every single byte, we
  294. * queue them up and run a single DMA operation for the entire series
  295. * of command and data bytes.
  296. */
  297. if (ctrl & (NAND_ALE | NAND_CLE)) {
  298. if (data != NAND_CMD_NONE)
  299. nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
  300. return;
  301. }
  302. /*
  303. * If control arrives here, MTD has deasserted both the ALE and CLE,
  304. * which means it's ready to run an operation. Check if we have any
  305. * bytes to send.
  306. */
  307. if (nand_info->cmd_queue_len == 0)
  308. return;
  309. /* Compile the DMA descriptor -- a descriptor that sends command. */
  310. d = mxs_nand_get_dma_desc(nand_info);
  311. d->cmd.data =
  312. MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
  313. MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
  314. MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
  315. (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
  316. d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
  317. d->cmd.pio_words[0] =
  318. GPMI_CTRL0_COMMAND_MODE_WRITE |
  319. GPMI_CTRL0_WORD_LENGTH |
  320. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  321. GPMI_CTRL0_ADDRESS_NAND_CLE |
  322. GPMI_CTRL0_ADDRESS_INCREMENT |
  323. nand_info->cmd_queue_len;
  324. mxs_dma_desc_append(channel, d);
  325. /* Flush caches */
  326. mxs_nand_flush_cmd_buf(nand_info);
  327. /* Execute the DMA chain. */
  328. ret = mxs_dma_go(channel);
  329. if (ret)
  330. printf("MXS NAND: Error sending command\n");
  331. mxs_nand_return_dma_descs(nand_info);
  332. /* Reset the command queue. */
  333. nand_info->cmd_queue_len = 0;
  334. }
  335. /*
  336. * Test if the NAND flash is ready.
  337. */
  338. static int mxs_nand_device_ready(struct mtd_info *mtd)
  339. {
  340. struct nand_chip *chip = mtd_to_nand(mtd);
  341. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  342. uint32_t tmp;
  343. tmp = readl(&nand_info->gpmi_regs->hw_gpmi_stat);
  344. tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
  345. return tmp & 1;
  346. }
  347. /*
  348. * Select the NAND chip.
  349. */
  350. static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
  351. {
  352. struct nand_chip *nand = mtd_to_nand(mtd);
  353. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  354. nand_info->cur_chip = chip;
  355. }
  356. /*
  357. * Handle block mark swapping.
  358. *
  359. * Note that, when this function is called, it doesn't know whether it's
  360. * swapping the block mark, or swapping it *back* -- but it doesn't matter
  361. * because the the operation is the same.
  362. */
  363. static void mxs_nand_swap_block_mark(struct bch_geometry *geo,
  364. uint8_t *data_buf, uint8_t *oob_buf)
  365. {
  366. uint32_t bit_offset = geo->block_mark_bit_offset;
  367. uint32_t buf_offset = geo->block_mark_byte_offset;
  368. uint32_t src;
  369. uint32_t dst;
  370. /*
  371. * Get the byte from the data area that overlays the block mark. Since
  372. * the ECC engine applies its own view to the bits in the page, the
  373. * physical block mark won't (in general) appear on a byte boundary in
  374. * the data.
  375. */
  376. src = data_buf[buf_offset] >> bit_offset;
  377. src |= data_buf[buf_offset + 1] << (8 - bit_offset);
  378. dst = oob_buf[0];
  379. oob_buf[0] = src;
  380. data_buf[buf_offset] &= ~(0xff << bit_offset);
  381. data_buf[buf_offset + 1] &= 0xff << bit_offset;
  382. data_buf[buf_offset] |= dst << bit_offset;
  383. data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
  384. }
  385. /*
  386. * Read data from NAND.
  387. */
  388. static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
  389. {
  390. struct nand_chip *nand = mtd_to_nand(mtd);
  391. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  392. struct mxs_dma_desc *d;
  393. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  394. int ret;
  395. if (length > NAND_MAX_PAGESIZE) {
  396. printf("MXS NAND: DMA buffer too big\n");
  397. return;
  398. }
  399. if (!buf) {
  400. printf("MXS NAND: DMA buffer is NULL\n");
  401. return;
  402. }
  403. /* Compile the DMA descriptor - a descriptor that reads data. */
  404. d = mxs_nand_get_dma_desc(nand_info);
  405. d->cmd.data =
  406. MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
  407. MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
  408. (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
  409. (length << MXS_DMA_DESC_BYTES_OFFSET);
  410. d->cmd.address = (dma_addr_t)nand_info->data_buf;
  411. d->cmd.pio_words[0] =
  412. GPMI_CTRL0_COMMAND_MODE_READ |
  413. GPMI_CTRL0_WORD_LENGTH |
  414. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  415. GPMI_CTRL0_ADDRESS_NAND_DATA |
  416. length;
  417. mxs_dma_desc_append(channel, d);
  418. /*
  419. * A DMA descriptor that waits for the command to end and the chip to
  420. * become ready.
  421. *
  422. * I think we actually should *not* be waiting for the chip to become
  423. * ready because, after all, we don't care. I think the original code
  424. * did that and no one has re-thought it yet.
  425. */
  426. d = mxs_nand_get_dma_desc(nand_info);
  427. d->cmd.data =
  428. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
  429. MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
  430. MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  431. d->cmd.address = 0;
  432. d->cmd.pio_words[0] =
  433. GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
  434. GPMI_CTRL0_WORD_LENGTH |
  435. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  436. GPMI_CTRL0_ADDRESS_NAND_DATA;
  437. mxs_dma_desc_append(channel, d);
  438. /* Invalidate caches */
  439. mxs_nand_inval_data_buf(nand_info);
  440. /* Execute the DMA chain. */
  441. ret = mxs_dma_go(channel);
  442. if (ret) {
  443. printf("MXS NAND: DMA read error\n");
  444. goto rtn;
  445. }
  446. /* Invalidate caches */
  447. mxs_nand_inval_data_buf(nand_info);
  448. memcpy(buf, nand_info->data_buf, length);
  449. rtn:
  450. mxs_nand_return_dma_descs(nand_info);
  451. }
  452. /*
  453. * Write data to NAND.
  454. */
  455. static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
  456. int length)
  457. {
  458. struct nand_chip *nand = mtd_to_nand(mtd);
  459. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  460. struct mxs_dma_desc *d;
  461. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  462. int ret;
  463. if (length > NAND_MAX_PAGESIZE) {
  464. printf("MXS NAND: DMA buffer too big\n");
  465. return;
  466. }
  467. if (!buf) {
  468. printf("MXS NAND: DMA buffer is NULL\n");
  469. return;
  470. }
  471. memcpy(nand_info->data_buf, buf, length);
  472. /* Compile the DMA descriptor - a descriptor that writes data. */
  473. d = mxs_nand_get_dma_desc(nand_info);
  474. d->cmd.data =
  475. MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
  476. MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
  477. (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
  478. (length << MXS_DMA_DESC_BYTES_OFFSET);
  479. d->cmd.address = (dma_addr_t)nand_info->data_buf;
  480. d->cmd.pio_words[0] =
  481. GPMI_CTRL0_COMMAND_MODE_WRITE |
  482. GPMI_CTRL0_WORD_LENGTH |
  483. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  484. GPMI_CTRL0_ADDRESS_NAND_DATA |
  485. length;
  486. mxs_dma_desc_append(channel, d);
  487. /* Flush caches */
  488. mxs_nand_flush_data_buf(nand_info);
  489. /* Execute the DMA chain. */
  490. ret = mxs_dma_go(channel);
  491. if (ret)
  492. printf("MXS NAND: DMA write error\n");
  493. mxs_nand_return_dma_descs(nand_info);
  494. }
  495. /*
  496. * Read a single byte from NAND.
  497. */
  498. static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
  499. {
  500. uint8_t buf;
  501. mxs_nand_read_buf(mtd, &buf, 1);
  502. return buf;
  503. }
  504. static bool mxs_nand_erased_page(struct mtd_info *mtd, struct nand_chip *nand,
  505. u8 *buf, int chunk, int page)
  506. {
  507. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  508. struct bch_geometry *geo = &nand_info->bch_geometry;
  509. unsigned int flip_bits = 0, flip_bits_noecc = 0;
  510. unsigned int threshold;
  511. unsigned int base = geo->ecc_chunkn_size * chunk;
  512. u32 *dma_buf = (u32 *)buf;
  513. int i;
  514. threshold = geo->gf_len / 2;
  515. if (threshold > geo->ecc_strength)
  516. threshold = geo->ecc_strength;
  517. for (i = 0; i < geo->ecc_chunkn_size; i++) {
  518. flip_bits += hweight8(~buf[base + i]);
  519. if (flip_bits > threshold)
  520. return false;
  521. }
  522. nand->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
  523. nand->read_buf(mtd, buf, mtd->writesize);
  524. for (i = 0; i < mtd->writesize / 4; i++) {
  525. flip_bits_noecc += hweight32(~dma_buf[i]);
  526. if (flip_bits_noecc > threshold)
  527. return false;
  528. }
  529. mtd->ecc_stats.corrected += flip_bits;
  530. memset(buf, 0xff, mtd->writesize);
  531. printf("The page(%d) is an erased page(%d,%d,%d,%d).\n", page, chunk, threshold, flip_bits, flip_bits_noecc);
  532. return true;
  533. }
  534. /*
  535. * Read a page from NAND.
  536. */
  537. static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
  538. uint8_t *buf, int oob_required,
  539. int page)
  540. {
  541. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  542. struct bch_geometry *geo = &nand_info->bch_geometry;
  543. struct mxs_bch_regs *bch_regs = nand_info->bch_regs;
  544. struct mxs_dma_desc *d;
  545. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  546. uint32_t corrected = 0, failed = 0;
  547. uint8_t *status;
  548. int i, ret;
  549. int flag = 0;
  550. /* Compile the DMA descriptor - wait for ready. */
  551. d = mxs_nand_get_dma_desc(nand_info);
  552. d->cmd.data =
  553. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
  554. MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
  555. (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  556. d->cmd.address = 0;
  557. d->cmd.pio_words[0] =
  558. GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
  559. GPMI_CTRL0_WORD_LENGTH |
  560. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  561. GPMI_CTRL0_ADDRESS_NAND_DATA;
  562. mxs_dma_desc_append(channel, d);
  563. /* Compile the DMA descriptor - enable the BCH block and read. */
  564. d = mxs_nand_get_dma_desc(nand_info);
  565. d->cmd.data =
  566. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
  567. MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  568. d->cmd.address = 0;
  569. d->cmd.pio_words[0] =
  570. GPMI_CTRL0_COMMAND_MODE_READ |
  571. GPMI_CTRL0_WORD_LENGTH |
  572. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  573. GPMI_CTRL0_ADDRESS_NAND_DATA |
  574. (mtd->writesize + mtd->oobsize);
  575. d->cmd.pio_words[1] = 0;
  576. d->cmd.pio_words[2] =
  577. GPMI_ECCCTRL_ENABLE_ECC |
  578. GPMI_ECCCTRL_ECC_CMD_DECODE |
  579. GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
  580. d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
  581. d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
  582. d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
  583. mxs_dma_desc_append(channel, d);
  584. /* Compile the DMA descriptor - disable the BCH block. */
  585. d = mxs_nand_get_dma_desc(nand_info);
  586. d->cmd.data =
  587. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
  588. MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
  589. (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  590. d->cmd.address = 0;
  591. d->cmd.pio_words[0] =
  592. GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
  593. GPMI_CTRL0_WORD_LENGTH |
  594. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  595. GPMI_CTRL0_ADDRESS_NAND_DATA |
  596. (mtd->writesize + mtd->oobsize);
  597. d->cmd.pio_words[1] = 0;
  598. d->cmd.pio_words[2] = 0;
  599. mxs_dma_desc_append(channel, d);
  600. /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
  601. d = mxs_nand_get_dma_desc(nand_info);
  602. d->cmd.data =
  603. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
  604. MXS_DMA_DESC_DEC_SEM;
  605. d->cmd.address = 0;
  606. mxs_dma_desc_append(channel, d);
  607. /* Invalidate caches */
  608. mxs_nand_inval_data_buf(nand_info);
  609. /* Execute the DMA chain. */
  610. ret = mxs_dma_go(channel);
  611. if (ret) {
  612. printf("MXS NAND: DMA read error\n");
  613. goto rtn;
  614. }
  615. ret = mxs_nand_wait_for_bch_complete(nand_info);
  616. if (ret) {
  617. printf("MXS NAND: BCH read timeout\n");
  618. goto rtn;
  619. }
  620. mxs_nand_return_dma_descs(nand_info);
  621. /* Invalidate caches */
  622. mxs_nand_inval_data_buf(nand_info);
  623. /* Read DMA completed, now do the mark swapping. */
  624. mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf);
  625. /* Loop over status bytes, accumulating ECC status. */
  626. status = nand_info->oob_buf + mxs_nand_aux_status_offset();
  627. for (i = 0; i < geo->ecc_chunk_count; i++) {
  628. if (status[i] == 0x00)
  629. continue;
  630. if (status[i] == 0xff) {
  631. if (is_mx6dqp() || is_mx7() ||
  632. is_mx6ul() || is_imx8() || is_imx8m())
  633. if (readl(&bch_regs->hw_bch_debug1))
  634. flag = 1;
  635. continue;
  636. }
  637. if (status[i] == 0xfe) {
  638. if (mxs_nand_erased_page(mtd, nand,
  639. nand_info->data_buf, i, page))
  640. break;
  641. failed++;
  642. continue;
  643. }
  644. corrected += status[i];
  645. }
  646. /* Propagate ECC status to the owning MTD. */
  647. mtd->ecc_stats.failed += failed;
  648. mtd->ecc_stats.corrected += corrected;
  649. /*
  650. * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
  651. * details about our policy for delivering the OOB.
  652. *
  653. * We fill the caller's buffer with set bits, and then copy the block
  654. * mark to the caller's buffer. Note that, if block mark swapping was
  655. * necessary, it has already been done, so we can rely on the first
  656. * byte of the auxiliary buffer to contain the block mark.
  657. */
  658. memset(nand->oob_poi, 0xff, mtd->oobsize);
  659. nand->oob_poi[0] = nand_info->oob_buf[0];
  660. memcpy(buf, nand_info->data_buf, mtd->writesize);
  661. if (flag)
  662. memset(buf, 0xff, mtd->writesize);
  663. rtn:
  664. mxs_nand_return_dma_descs(nand_info);
  665. return ret;
  666. }
  667. /*
  668. * Write a page to NAND.
  669. */
  670. static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
  671. struct nand_chip *nand, const uint8_t *buf,
  672. int oob_required, int page)
  673. {
  674. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  675. struct bch_geometry *geo = &nand_info->bch_geometry;
  676. struct mxs_dma_desc *d;
  677. uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
  678. int ret;
  679. memcpy(nand_info->data_buf, buf, mtd->writesize);
  680. memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
  681. /* Handle block mark swapping. */
  682. mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf);
  683. /* Compile the DMA descriptor - write data. */
  684. d = mxs_nand_get_dma_desc(nand_info);
  685. d->cmd.data =
  686. MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
  687. MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
  688. (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  689. d->cmd.address = 0;
  690. d->cmd.pio_words[0] =
  691. GPMI_CTRL0_COMMAND_MODE_WRITE |
  692. GPMI_CTRL0_WORD_LENGTH |
  693. (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
  694. GPMI_CTRL0_ADDRESS_NAND_DATA;
  695. d->cmd.pio_words[1] = 0;
  696. d->cmd.pio_words[2] =
  697. GPMI_ECCCTRL_ENABLE_ECC |
  698. GPMI_ECCCTRL_ECC_CMD_ENCODE |
  699. GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
  700. d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize);
  701. d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
  702. d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
  703. if ((is_mx7() || is_imx8m()) && nand_info->en_randomizer) {
  704. d->cmd.pio_words[2] |= GPMI_ECCCTRL_RANDOMIZER_ENABLE |
  705. GPMI_ECCCTRL_RANDOMIZER_TYPE2;
  706. /*
  707. * Write NAND page number needed to be randomized
  708. * to GPMI_ECCCOUNT register.
  709. *
  710. * The value is between 0-255. For additional details
  711. * check 9.6.6.4 of i.MX7D Applications Processor reference
  712. */
  713. d->cmd.pio_words[3] |= (page % 255) << 16;
  714. }
  715. mxs_dma_desc_append(channel, d);
  716. /* Flush caches */
  717. mxs_nand_flush_data_buf(nand_info);
  718. /* Execute the DMA chain. */
  719. ret = mxs_dma_go(channel);
  720. if (ret) {
  721. printf("MXS NAND: DMA write error\n");
  722. goto rtn;
  723. }
  724. ret = mxs_nand_wait_for_bch_complete(nand_info);
  725. if (ret) {
  726. printf("MXS NAND: BCH write timeout\n");
  727. goto rtn;
  728. }
  729. rtn:
  730. mxs_nand_return_dma_descs(nand_info);
  731. return 0;
  732. }
  733. /*
  734. * Read OOB from NAND.
  735. *
  736. * This function is a veneer that replaces the function originally installed by
  737. * the NAND Flash MTD code.
  738. */
  739. static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
  740. struct mtd_oob_ops *ops)
  741. {
  742. struct nand_chip *chip = mtd_to_nand(mtd);
  743. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  744. int ret;
  745. if (ops->mode == MTD_OPS_RAW)
  746. nand_info->raw_oob_mode = 1;
  747. else
  748. nand_info->raw_oob_mode = 0;
  749. ret = nand_info->hooked_read_oob(mtd, from, ops);
  750. nand_info->raw_oob_mode = 0;
  751. return ret;
  752. }
  753. /*
  754. * Write OOB to NAND.
  755. *
  756. * This function is a veneer that replaces the function originally installed by
  757. * the NAND Flash MTD code.
  758. */
  759. static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
  760. struct mtd_oob_ops *ops)
  761. {
  762. struct nand_chip *chip = mtd_to_nand(mtd);
  763. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  764. int ret;
  765. if (ops->mode == MTD_OPS_RAW)
  766. nand_info->raw_oob_mode = 1;
  767. else
  768. nand_info->raw_oob_mode = 0;
  769. ret = nand_info->hooked_write_oob(mtd, to, ops);
  770. nand_info->raw_oob_mode = 0;
  771. return ret;
  772. }
  773. /*
  774. * Mark a block bad in NAND.
  775. *
  776. * This function is a veneer that replaces the function originally installed by
  777. * the NAND Flash MTD code.
  778. */
  779. static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
  780. {
  781. struct nand_chip *chip = mtd_to_nand(mtd);
  782. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  783. int ret;
  784. nand_info->marking_block_bad = 1;
  785. ret = nand_info->hooked_block_markbad(mtd, ofs);
  786. nand_info->marking_block_bad = 0;
  787. return ret;
  788. }
  789. /*
  790. * There are several places in this driver where we have to handle the OOB and
  791. * block marks. This is the function where things are the most complicated, so
  792. * this is where we try to explain it all. All the other places refer back to
  793. * here.
  794. *
  795. * These are the rules, in order of decreasing importance:
  796. *
  797. * 1) Nothing the caller does can be allowed to imperil the block mark, so all
  798. * write operations take measures to protect it.
  799. *
  800. * 2) In read operations, the first byte of the OOB we return must reflect the
  801. * true state of the block mark, no matter where that block mark appears in
  802. * the physical page.
  803. *
  804. * 3) ECC-based read operations return an OOB full of set bits (since we never
  805. * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
  806. * return).
  807. *
  808. * 4) "Raw" read operations return a direct view of the physical bytes in the
  809. * page, using the conventional definition of which bytes are data and which
  810. * are OOB. This gives the caller a way to see the actual, physical bytes
  811. * in the page, without the distortions applied by our ECC engine.
  812. *
  813. * What we do for this specific read operation depends on whether we're doing
  814. * "raw" read, or an ECC-based read.
  815. *
  816. * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
  817. * easy. When reading a page, for example, the NAND Flash MTD code calls our
  818. * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
  819. * ECC-based or raw view of the page is implicit in which function it calls
  820. * (there is a similar pair of ECC-based/raw functions for writing).
  821. *
  822. * Since MTD assumes the OOB is not covered by ECC, there is no pair of
  823. * ECC-based/raw functions for reading or or writing the OOB. The fact that the
  824. * caller wants an ECC-based or raw view of the page is not propagated down to
  825. * this driver.
  826. *
  827. * Since our OOB *is* covered by ECC, we need this information. So, we hook the
  828. * ecc.read_oob and ecc.write_oob function pointers in the owning
  829. * struct mtd_info with our own functions. These hook functions set the
  830. * raw_oob_mode field so that, when control finally arrives here, we'll know
  831. * what to do.
  832. */
  833. static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
  834. int page)
  835. {
  836. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  837. /*
  838. * First, fill in the OOB buffer. If we're doing a raw read, we need to
  839. * get the bytes from the physical page. If we're not doing a raw read,
  840. * we need to fill the buffer with set bits.
  841. */
  842. if (nand_info->raw_oob_mode) {
  843. /*
  844. * If control arrives here, we're doing a "raw" read. Send the
  845. * command to read the conventional OOB and read it.
  846. */
  847. nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
  848. nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
  849. } else {
  850. /*
  851. * If control arrives here, we're not doing a "raw" read. Fill
  852. * the OOB buffer with set bits and correct the block mark.
  853. */
  854. memset(nand->oob_poi, 0xff, mtd->oobsize);
  855. nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
  856. mxs_nand_read_buf(mtd, nand->oob_poi, 1);
  857. }
  858. return 0;
  859. }
  860. /*
  861. * Write OOB data to NAND.
  862. */
  863. static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
  864. int page)
  865. {
  866. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  867. uint8_t block_mark = 0;
  868. /*
  869. * There are fundamental incompatibilities between the i.MX GPMI NFC and
  870. * the NAND Flash MTD model that make it essentially impossible to write
  871. * the out-of-band bytes.
  872. *
  873. * We permit *ONE* exception. If the *intent* of writing the OOB is to
  874. * mark a block bad, we can do that.
  875. */
  876. if (!nand_info->marking_block_bad) {
  877. printf("NXS NAND: Writing OOB isn't supported\n");
  878. return -EIO;
  879. }
  880. /* Write the block mark. */
  881. nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  882. nand->write_buf(mtd, &block_mark, 1);
  883. nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  884. /* Check if it worked. */
  885. if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
  886. return -EIO;
  887. return 0;
  888. }
  889. /*
  890. * Claims all blocks are good.
  891. *
  892. * In principle, this function is *only* called when the NAND Flash MTD system
  893. * isn't allowed to keep an in-memory bad block table, so it is forced to ask
  894. * the driver for bad block information.
  895. *
  896. * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
  897. * this function is *only* called when we take it away.
  898. *
  899. * Thus, this function is only called when we want *all* blocks to look good,
  900. * so it *always* return success.
  901. */
  902. static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
  903. {
  904. return 0;
  905. }
  906. static int mxs_nand_set_geometry(struct mtd_info *mtd, struct bch_geometry *geo)
  907. {
  908. struct nand_chip *chip = mtd_to_nand(mtd);
  909. struct nand_chip *nand = mtd_to_nand(mtd);
  910. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  911. if (chip->ecc_strength_ds > nand_info->max_ecc_strength_supported) {
  912. printf("unsupported NAND chip, minimum ecc required %d\n"
  913. , chip->ecc_strength_ds);
  914. return -EINVAL;
  915. }
  916. if ((!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0) &&
  917. mtd->oobsize < 1024) || nand_info->legacy_bch_geometry) {
  918. dev_warn(this->dev, "use legacy bch geometry\n");
  919. return mxs_nand_legacy_calc_ecc_layout(geo, mtd);
  920. }
  921. if (mtd->oobsize > 1024 || chip->ecc_step_ds < mtd->oobsize)
  922. return mxs_nand_calc_ecc_for_large_oob(geo, mtd);
  923. return mxs_nand_calc_ecc_layout_by_info(geo, mtd,
  924. chip->ecc_strength_ds, chip->ecc_step_ds);
  925. return 0;
  926. }
  927. /*
  928. * At this point, the physical NAND Flash chips have been identified and
  929. * counted, so we know the physical geometry. This enables us to make some
  930. * important configuration decisions.
  931. *
  932. * The return value of this function propagates directly back to this driver's
  933. * board_nand_init(). Anything other than zero will cause this driver to
  934. * tear everything down and declare failure.
  935. */
  936. int mxs_nand_setup_ecc(struct mtd_info *mtd)
  937. {
  938. struct nand_chip *nand = mtd_to_nand(mtd);
  939. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  940. struct bch_geometry *geo = &nand_info->bch_geometry;
  941. struct mxs_bch_regs *bch_regs = nand_info->bch_regs;
  942. uint32_t tmp;
  943. int ret;
  944. nand_info->en_randomizer = 0;
  945. nand_info->oobsize = mtd->oobsize;
  946. nand_info->writesize = mtd->writesize;
  947. ret = mxs_nand_set_geometry(mtd, geo);
  948. if (ret)
  949. return ret;
  950. /* Configure BCH and set NFC geometry */
  951. mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
  952. /* Configure layout 0 */
  953. tmp = (geo->ecc_chunk_count - 1) << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
  954. tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
  955. tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT0_ECC0_OFFSET;
  956. tmp |= geo->ecc_chunk0_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
  957. tmp |= (geo->gf_len == 14 ? 1 : 0) <<
  958. BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
  959. writel(tmp, &bch_regs->hw_bch_flash0layout0);
  960. nand_info->bch_flash0layout0 = tmp;
  961. tmp = (mtd->writesize + mtd->oobsize)
  962. << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
  963. tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT1_ECCN_OFFSET;
  964. tmp |= geo->ecc_chunkn_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
  965. tmp |= (geo->gf_len == 14 ? 1 : 0) <<
  966. BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
  967. writel(tmp, &bch_regs->hw_bch_flash0layout1);
  968. nand_info->bch_flash0layout1 = tmp;
  969. /* Set erase threshold to ecc strength for mx6ul, mx6qp and mx7 */
  970. if (is_mx6dqp() || is_mx7() ||
  971. is_mx6ul() || is_imx8() || is_imx8m())
  972. writel(BCH_MODE_ERASE_THRESHOLD(geo->ecc_strength),
  973. &bch_regs->hw_bch_mode);
  974. /* Set *all* chip selects to use layout 0 */
  975. writel(0, &bch_regs->hw_bch_layoutselect);
  976. /* Enable BCH complete interrupt */
  977. writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
  978. /* Hook some operations at the MTD level. */
  979. if (mtd->_read_oob != mxs_nand_hook_read_oob) {
  980. nand_info->hooked_read_oob = mtd->_read_oob;
  981. mtd->_read_oob = mxs_nand_hook_read_oob;
  982. }
  983. if (mtd->_write_oob != mxs_nand_hook_write_oob) {
  984. nand_info->hooked_write_oob = mtd->_write_oob;
  985. mtd->_write_oob = mxs_nand_hook_write_oob;
  986. }
  987. if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
  988. nand_info->hooked_block_markbad = mtd->_block_markbad;
  989. mtd->_block_markbad = mxs_nand_hook_block_markbad;
  990. }
  991. return 0;
  992. }
  993. /*
  994. * Allocate DMA buffers
  995. */
  996. int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
  997. {
  998. uint8_t *buf;
  999. const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
  1000. nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
  1001. /* DMA buffers */
  1002. buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
  1003. if (!buf) {
  1004. printf("MXS NAND: Error allocating DMA buffers\n");
  1005. return -ENOMEM;
  1006. }
  1007. memset(buf, 0, nand_info->data_buf_size);
  1008. nand_info->data_buf = buf;
  1009. nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
  1010. /* Command buffers */
  1011. nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
  1012. MXS_NAND_COMMAND_BUFFER_SIZE);
  1013. if (!nand_info->cmd_buf) {
  1014. free(buf);
  1015. printf("MXS NAND: Error allocating command buffers\n");
  1016. return -ENOMEM;
  1017. }
  1018. memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
  1019. nand_info->cmd_queue_len = 0;
  1020. return 0;
  1021. }
  1022. /*
  1023. * Initializes the NFC hardware.
  1024. */
  1025. static int mxs_nand_init_dma(struct mxs_nand_info *info)
  1026. {
  1027. int i = 0, j, ret = 0;
  1028. info->desc = malloc(sizeof(struct mxs_dma_desc *) *
  1029. MXS_NAND_DMA_DESCRIPTOR_COUNT);
  1030. if (!info->desc) {
  1031. ret = -ENOMEM;
  1032. goto err1;
  1033. }
  1034. /* Allocate the DMA descriptors. */
  1035. for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
  1036. info->desc[i] = mxs_dma_desc_alloc();
  1037. if (!info->desc[i]) {
  1038. ret = -ENOMEM;
  1039. goto err2;
  1040. }
  1041. }
  1042. /* Init the DMA controller. */
  1043. mxs_dma_init();
  1044. for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
  1045. j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
  1046. ret = mxs_dma_init_channel(j);
  1047. if (ret)
  1048. goto err3;
  1049. }
  1050. /* Reset the GPMI block. */
  1051. mxs_reset_block(&info->gpmi_regs->hw_gpmi_ctrl0_reg);
  1052. mxs_reset_block(&info->bch_regs->hw_bch_ctrl_reg);
  1053. /*
  1054. * Choose NAND mode, set IRQ polarity, disable write protection and
  1055. * select BCH ECC.
  1056. */
  1057. clrsetbits_le32(&info->gpmi_regs->hw_gpmi_ctrl1,
  1058. GPMI_CTRL1_GPMI_MODE,
  1059. GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
  1060. GPMI_CTRL1_BCH_MODE);
  1061. return 0;
  1062. err3:
  1063. for (--j; j >= MXS_DMA_CHANNEL_AHB_APBH_GPMI0; j--)
  1064. mxs_dma_release(j);
  1065. err2:
  1066. for (--i; i >= 0; i--)
  1067. mxs_dma_desc_free(info->desc[i]);
  1068. free(info->desc);
  1069. err1:
  1070. if (ret == -ENOMEM)
  1071. printf("MXS NAND: Unable to allocate DMA descriptors\n");
  1072. return ret;
  1073. }
  1074. int mxs_nand_init_spl(struct nand_chip *nand)
  1075. {
  1076. struct mxs_nand_info *nand_info;
  1077. int err;
  1078. nand_info = malloc(sizeof(struct mxs_nand_info));
  1079. if (!nand_info) {
  1080. printf("MXS NAND: Failed to allocate private data\n");
  1081. return -ENOMEM;
  1082. }
  1083. memset(nand_info, 0, sizeof(struct mxs_nand_info));
  1084. nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
  1085. nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
  1086. if (is_mx6sx() || is_mx7() || is_imx8() || is_imx8m())
  1087. nand_info->max_ecc_strength_supported = 62;
  1088. else
  1089. nand_info->max_ecc_strength_supported = 40;
  1090. err = mxs_nand_alloc_buffers(nand_info);
  1091. if (err)
  1092. return err;
  1093. err = mxs_nand_init_dma(nand_info);
  1094. if (err)
  1095. return err;
  1096. nand_set_controller_data(nand, nand_info);
  1097. nand->options |= NAND_NO_SUBPAGE_WRITE;
  1098. nand->cmd_ctrl = mxs_nand_cmd_ctrl;
  1099. nand->dev_ready = mxs_nand_device_ready;
  1100. nand->select_chip = mxs_nand_select_chip;
  1101. nand->read_byte = mxs_nand_read_byte;
  1102. nand->read_buf = mxs_nand_read_buf;
  1103. nand->ecc.read_page = mxs_nand_ecc_read_page;
  1104. nand->ecc.mode = NAND_ECC_HW;
  1105. return 0;
  1106. }
  1107. int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info)
  1108. {
  1109. struct mtd_info *mtd;
  1110. struct nand_chip *nand;
  1111. int err;
  1112. nand = &nand_info->chip;
  1113. mtd = nand_to_mtd(nand);
  1114. err = mxs_nand_alloc_buffers(nand_info);
  1115. if (err)
  1116. return err;
  1117. err = mxs_nand_init_dma(nand_info);
  1118. if (err)
  1119. goto err_free_buffers;
  1120. memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
  1121. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  1122. nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
  1123. #endif
  1124. nand_set_controller_data(nand, nand_info);
  1125. nand->options |= NAND_NO_SUBPAGE_WRITE;
  1126. if (nand_info->dev)
  1127. nand->flash_node = dev_of_offset(nand_info->dev);
  1128. nand->cmd_ctrl = mxs_nand_cmd_ctrl;
  1129. nand->dev_ready = mxs_nand_device_ready;
  1130. nand->select_chip = mxs_nand_select_chip;
  1131. nand->block_bad = mxs_nand_block_bad;
  1132. nand->read_byte = mxs_nand_read_byte;
  1133. nand->read_buf = mxs_nand_read_buf;
  1134. nand->write_buf = mxs_nand_write_buf;
  1135. /* first scan to find the device and get the page size */
  1136. if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL))
  1137. goto err_free_buffers;
  1138. if (mxs_nand_setup_ecc(mtd))
  1139. goto err_free_buffers;
  1140. nand->ecc.read_page = mxs_nand_ecc_read_page;
  1141. nand->ecc.write_page = mxs_nand_ecc_write_page;
  1142. nand->ecc.read_oob = mxs_nand_ecc_read_oob;
  1143. nand->ecc.write_oob = mxs_nand_ecc_write_oob;
  1144. nand->ecc.layout = &fake_ecc_layout;
  1145. nand->ecc.mode = NAND_ECC_HW;
  1146. nand->ecc.size = nand_info->bch_geometry.ecc_chunkn_size;
  1147. nand->ecc.strength = nand_info->bch_geometry.ecc_strength;
  1148. /* second phase scan */
  1149. err = nand_scan_tail(mtd);
  1150. if (err)
  1151. goto err_free_buffers;
  1152. err = nand_register(0, mtd);
  1153. if (err)
  1154. goto err_free_buffers;
  1155. return 0;
  1156. err_free_buffers:
  1157. free(nand_info->data_buf);
  1158. free(nand_info->cmd_buf);
  1159. return err;
  1160. }
  1161. #ifndef CONFIG_NAND_MXS_DT
  1162. void board_nand_init(void)
  1163. {
  1164. struct mxs_nand_info *nand_info;
  1165. nand_info = malloc(sizeof(struct mxs_nand_info));
  1166. if (!nand_info) {
  1167. printf("MXS NAND: Failed to allocate private data\n");
  1168. return;
  1169. }
  1170. memset(nand_info, 0, sizeof(struct mxs_nand_info));
  1171. nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
  1172. nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
  1173. /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
  1174. if (is_mx6sx() || is_mx7())
  1175. nand_info->max_ecc_strength_supported = 62;
  1176. else
  1177. nand_info->max_ecc_strength_supported = 40;
  1178. #ifdef CONFIG_NAND_MXS_USE_MINIMUM_ECC
  1179. nand_info->use_minimum_ecc = true;
  1180. #endif
  1181. if (mxs_nand_init_ctrl(nand_info) < 0)
  1182. goto err;
  1183. return;
  1184. err:
  1185. free(nand_info);
  1186. }
  1187. #endif
  1188. /*
  1189. * Read NAND layout for FCB block generation.
  1190. */
  1191. void mxs_nand_get_layout(struct mtd_info *mtd, struct mxs_nand_layout *l)
  1192. {
  1193. struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
  1194. u32 tmp;
  1195. tmp = readl(&bch_regs->hw_bch_flash0layout0);
  1196. l->nblocks = (tmp & BCH_FLASHLAYOUT0_NBLOCKS_MASK) >>
  1197. BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
  1198. l->meta_size = (tmp & BCH_FLASHLAYOUT0_META_SIZE_MASK) >>
  1199. BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
  1200. tmp = readl(&bch_regs->hw_bch_flash0layout1);
  1201. l->data0_size = 4 * ((tmp & BCH_FLASHLAYOUT0_DATA0_SIZE_MASK) >>
  1202. BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET);
  1203. l->ecc0 = (tmp & BCH_FLASHLAYOUT0_ECC0_MASK) >>
  1204. BCH_FLASHLAYOUT0_ECC0_OFFSET;
  1205. l->datan_size = 4 * ((tmp & BCH_FLASHLAYOUT1_DATAN_SIZE_MASK) >>
  1206. BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET);
  1207. l->eccn = (tmp & BCH_FLASHLAYOUT1_ECCN_MASK) >>
  1208. BCH_FLASHLAYOUT1_ECCN_OFFSET;
  1209. l->gf_len = (tmp & BCH_FLASHLAYOUT1_GF13_0_GF14_1_MASK) >>
  1210. BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
  1211. }
  1212. /*
  1213. * Set BCH to specific layout used by ROM bootloader to read FCB.
  1214. */
  1215. void mxs_nand_mode_fcb(struct mtd_info *mtd)
  1216. {
  1217. u32 tmp;
  1218. struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
  1219. struct nand_chip *nand = mtd_to_nand(mtd);
  1220. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  1221. nand_info->en_randomizer = 1;
  1222. mtd->writesize = 1024;
  1223. mtd->oobsize = 1862 - 1024;
  1224. /* 8 ecc_chunks_*/
  1225. tmp = 7 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
  1226. /* 32 bytes for metadata */
  1227. tmp |= 32 << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
  1228. /* using ECC62 level to be performed */
  1229. tmp |= 0x1F << BCH_FLASHLAYOUT0_ECC0_OFFSET;
  1230. /* 0x20 * 4 bytes of the data0 block */
  1231. tmp |= 0x20 << BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET;
  1232. tmp |= 0 << BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
  1233. writel(tmp, &bch_regs->hw_bch_flash0layout0);
  1234. /* 1024 for data + 838 for OOB */
  1235. tmp = 1862 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
  1236. /* using ECC62 level to be performed */
  1237. tmp |= 0x1F << BCH_FLASHLAYOUT1_ECCN_OFFSET;
  1238. /* 0x20 * 4 bytes of the data0 block */
  1239. tmp |= 0x20 << BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET;
  1240. tmp |= 0 << BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
  1241. writel(tmp, &bch_regs->hw_bch_flash0layout1);
  1242. }
  1243. /*
  1244. * Restore BCH to normal settings.
  1245. */
  1246. void mxs_nand_mode_normal(struct mtd_info *mtd)
  1247. {
  1248. struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
  1249. struct nand_chip *nand = mtd_to_nand(mtd);
  1250. struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
  1251. nand_info->en_randomizer = 0;
  1252. mtd->writesize = nand_info->writesize;
  1253. mtd->oobsize = nand_info->oobsize;
  1254. writel(nand_info->bch_flash0layout0, &bch_regs->hw_bch_flash0layout0);
  1255. writel(nand_info->bch_flash0layout1, &bch_regs->hw_bch_flash0layout1);
  1256. }
  1257. uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
  1258. {
  1259. struct nand_chip *chip = mtd_to_nand(mtd);
  1260. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  1261. struct bch_geometry *geo = &nand_info->bch_geometry;
  1262. return geo->block_mark_byte_offset;
  1263. }
  1264. uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
  1265. {
  1266. struct nand_chip *chip = mtd_to_nand(mtd);
  1267. struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
  1268. struct bch_geometry *geo = &nand_info->bch_geometry;
  1269. return geo->block_mark_bit_offset;
  1270. }