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RISC-V/ProcessorPkg: Address Core CI Uncrustify errors

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Abner Chang 2 лет назад
Родитель
Сommit
9006355ddf
25 измененных файлов с 1049 добавлено и 884 удалено
  1. 78 78
      Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
  2. 14 14
      Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
  3. 3 1
      Silicon/RISC-V/ProcessorPkg/Include/Library/MachineModeTimerLib.h
  4. 54 22
      Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
  5. 61 61
      Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
  6. 3 3
      Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h
  7. 7 3
      Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatformTimerLib.h
  8. 35 34
      Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
  9. 52 51
      Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
  10. 26 26
      Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h
  11. 23 23
      Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
  12. 4 11
      Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
  13. 12 10
      Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
  14. 346 255
      Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
  15. 17 17
      Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
  16. 86 83
      Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
  17. 3 3
      Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
  18. 2 2
      Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
  19. 12 12
      Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
  20. 33 39
      Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
  21. 22 23
      Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h
  22. 42 24
      Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.c
  23. 25 22
      Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c
  24. 88 65
      Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
  25. 1 2
      Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h

+ 78 - 78
Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h

@@ -1,7 +1,7 @@
 /** @file
   RISC-V package definitions.
 
-  Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+  Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -11,36 +11,36 @@
 #define RISCV_INDUSTRY_STANDARD_H_
 
 #if defined (MDE_CPU_RISCV64)
-#define RISC_V_XLEN_BITS 64
+#define RISC_V_XLEN_BITS  64
 #else
 #endif
 
-#define RISC_V_ISA_ATOMIC_EXTENSION                 (0x00000001 << 0)
-#define RISC_V_ISA_BIT_OPERATION_EXTENSION          (0x00000001 << 1)
-#define RISC_V_ISA_COMPRESSED_EXTENSION             (0x00000001 << 2)
-#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION    (0x00000001 << 3)
-#define RISC_V_ISA_RV32E_ISA                        (0x00000001 << 4)
-#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION    (0x00000001 << 5)
-#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION    (0x00000001 << 6)
-#define RISC_V_ISA_RESERVED_1                       (0x00000001 << 7)
-#define RISC_V_ISA_INTEGER_ISA_EXTENSION            (0x00000001 << 8)
-#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION    (0x00000001 << 9)
-#define RISC_V_ISA_RESERVED_2                       (0x00000001 << 10)
-#define RISC_V_ISA_DECIMAL_FP_EXTENSION             (0x00000001 << 11)
-#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION        (0x00000001 << 12)
-#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED   (0x00000001 << 13)
-#define RISC_V_ISA_RESERVED_3                       (0x00000001 << 14)
-#define RISC_V_ISA_PACKED_SIMD_EXTENSION            (0x00000001 << 15)
-#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION      (0x00000001 << 16)
-#define RISC_V_ISA_RESERVED_4                       (0x00000001 << 17)
-#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED      (0x00000001 << 18)
-#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION    (0x00000001 << 19)
-#define RISC_V_ISA_USER_MODE_IMPLEMENTED            (0x00000001 << 20)
-#define RISC_V_ISA_VECTOR_EXTENSION                 (0x00000001 << 21)
-#define RISC_V_ISA_RESERVED_5                       (0x00000001 << 22)
-#define RISC_V_ISA_NON_STANDARD_EXTENSION           (0x00000001 << 23)
-#define RISC_V_ISA_RESERVED_6                       (0x00000001 << 24)
-#define RISC_V_ISA_RESERVED_7                       (0x00000001 << 25)
+#define RISC_V_ISA_ATOMIC_EXTENSION                           (0x00000001 << 0)
+#define RISC_V_ISA_BIT_OPERATION_EXTENSION                    (0x00000001 << 1)
+#define RISC_V_ISA_COMPRESSED_EXTENSION                       (0x00000001 << 2)
+#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION              (0x00000001 << 3)
+#define RISC_V_ISA_RV32E_ISA                                  (0x00000001 << 4)
+#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION              (0x00000001 << 5)
+#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION              (0x00000001 << 6)
+#define RISC_V_ISA_RESERVED_1                                 (0x00000001 << 7)
+#define RISC_V_ISA_INTEGER_ISA_EXTENSION                      (0x00000001 << 8)
+#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION  (0x00000001 << 9)
+#define RISC_V_ISA_RESERVED_2                                 (0x00000001 << 10)
+#define RISC_V_ISA_DECIMAL_FP_EXTENSION                       (0x00000001 << 11)
+#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION                  (0x00000001 << 12)
+#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED             (0x00000001 << 13)
+#define RISC_V_ISA_RESERVED_3                                 (0x00000001 << 14)
+#define RISC_V_ISA_PACKED_SIMD_EXTENSION                      (0x00000001 << 15)
+#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION                (0x00000001 << 16)
+#define RISC_V_ISA_RESERVED_4                                 (0x00000001 << 17)
+#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED                (0x00000001 << 18)
+#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION              (0x00000001 << 19)
+#define RISC_V_ISA_USER_MODE_IMPLEMENTED                      (0x00000001 << 20)
+#define RISC_V_ISA_VECTOR_EXTENSION                           (0x00000001 << 21)
+#define RISC_V_ISA_RESERVED_5                                 (0x00000001 << 22)
+#define RISC_V_ISA_NON_STANDARD_EXTENSION                     (0x00000001 << 23)
+#define RISC_V_ISA_RESERVED_6                                 (0x00000001 << 24)
+#define RISC_V_ISA_RESERVED_7                                 (0x00000001 << 25)
 
 //
 // RISC-V CSR definitions.
@@ -48,81 +48,81 @@
 //
 // Machine information
 //
-#define RISCV_CSR_MACHINE_MVENDORID     0xF11
-#define RISCV_CSR_MACHINE_MARCHID       0xF12
-#define RISCV_CSR_MACHINE_MIMPID        0xF13
-#define RISCV_CSR_MACHINE_HARRID        0xF14
+#define RISCV_CSR_MACHINE_MVENDORID  0xF11
+#define RISCV_CSR_MACHINE_MARCHID    0xF12
+#define RISCV_CSR_MACHINE_MIMPID     0xF13
+#define RISCV_CSR_MACHINE_HARRID     0xF14
 //
 // Machine Trap Setup.
 //
-#define RISCV_CSR_MACHINE_MSTATUS       0x300
-#define RISCV_CSR_MACHINE_MISA          0x301
-#define RISCV_CSR_MACHINE_MEDELEG       0x302
-#define RISCV_CSR_MACHINE_MIDELEG       0x303
-#define RISCV_CSR_MACHINE_MIE           0x304
-#define RISCV_CSR_MACHINE_MTVEC         0x305
+#define RISCV_CSR_MACHINE_MSTATUS  0x300
+#define RISCV_CSR_MACHINE_MISA     0x301
+#define RISCV_CSR_MACHINE_MEDELEG  0x302
+#define RISCV_CSR_MACHINE_MIDELEG  0x303
+#define RISCV_CSR_MACHINE_MIE      0x304
+#define RISCV_CSR_MACHINE_MTVEC    0x305
 
-#define RISCV_TIMER_COMPARE_BITS      32
+#define RISCV_TIMER_COMPARE_BITS  32
 //
 // Machine Timer and Counter.
 //
-//#define RISCV_CSR_MACHINE_MTIME         0x701
-//#define RISCV_CSR_MACHINE_MTIMEH        0x741
+// #define RISCV_CSR_MACHINE_MTIME         0x701
+// #define RISCV_CSR_MACHINE_MTIMEH        0x741
 //
 // Machine Trap Handling.
 //
-#define RISCV_CSR_MACHINE_MSCRATCH      0x340
-#define RISCV_CSR_MACHINE_MEPC          0x341
-#define RISCV_CSR_MACHINE_MCAUSE        0x342
-  #define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f
-  #define MACHINE_MCAUSE_INTERRUPT      (RISC_V_XLEN_BITS - 1)
-#define RISCV_CSR_MACHINE_MBADADDR      0x343
-#define RISCV_CSR_MACHINE_MIP           0x344
+#define RISCV_CSR_MACHINE_MSCRATCH  0x340
+#define RISCV_CSR_MACHINE_MEPC      0x341
+#define RISCV_CSR_MACHINE_MCAUSE    0x342
+#define MACHINE_MCAUSE_EXCEPTION_   MASK 0x0f
+#define MACHINE_MCAUSE_INTERRUPT    (RISC_V_XLEN_BITS - 1)
+#define RISCV_CSR_MACHINE_MBADADDR  0x343
+#define RISCV_CSR_MACHINE_MIP       0x344
 
 //
 // Machine Protection and Translation.
 //
-#define RISCV_CSR_MACHINE_MBASE         0x380
-#define RISCV_CSR_MACHINE_MBOUND        0x381
-#define RISCV_CSR_MACHINE_MIBASE        0x382
-#define RISCV_CSR_MACHINE_MIBOUND       0x383
-#define RISCV_CSR_MACHINE_MDBASE        0x384
-#define RISCV_CSR_MACHINE_MDBOUND       0x385
+#define RISCV_CSR_MACHINE_MBASE    0x380
+#define RISCV_CSR_MACHINE_MBOUND   0x381
+#define RISCV_CSR_MACHINE_MIBASE   0x382
+#define RISCV_CSR_MACHINE_MIBOUND  0x383
+#define RISCV_CSR_MACHINE_MDBASE   0x384
+#define RISCV_CSR_MACHINE_MDBOUND  0x385
 
 //
 // Supervisor mode CSR.
 //
 #define RISCV_CSR_SUPERVISOR_SSTATUS    0x100
-  #define SSTATUS_SIE_BIT_POSITION      1
-  #define SSTATUS_SPP_BIT_POSITION      8
+#define SSTATUS_SIE_BIT_POSITION        1
+#define SSTATUS_SPP_BIT_POSITION        8
 #define RISCV_CSR_SUPERVISOR_SIE        0x104
 #define RISCV_CSR_SUPERVISOR_STVEC      0x105
 #define RISCV_CSR_SUPERVISOR_SSCRATCH   0x140
 #define RISCV_CSR_SUPERVISOR_SEPC       0x141
 #define RISCV_CSR_SUPERVISOR_SCAUSE     0x142
-  #define SCAUSE_USER_SOFTWARE_INT        0
-  #define SCAUSE_SUPERVISOR_SOFTWARE_INT  1
-  #define SCAUSE_USER_TIMER_INT           4
-  #define SCAUSE_SUPERVISOR_TIMER_INT     5
-  #define SCAUSE_USER_EXTERNAL_INT        8
-  #define SCAUSE_SUPERVISOR_EXTERNAL_INT  9
+#define SCAUSE_USER_SOFTWARE_INT        0
+#define SCAUSE_SUPERVISOR_SOFTWARE_INT  1
+#define SCAUSE_USER_TIMER_INT           4
+#define SCAUSE_SUPERVISOR_TIMER_INT     5
+#define SCAUSE_USER_EXTERNAL_INT        8
+#define SCAUSE_SUPERVISOR_EXTERNAL_INT  9
 #define RISCV_CSR_SUPERVISOR_STVAL      0x143
 #define RISCV_CSR_SUPERVISOR_SIP        0x144
 #define RISCV_CSR_SUPERVISOR_SATP       0x180
 
 #if defined (MDE_CPU_RISCV64)
-  #define RISCV_SATP_MODE_MASK          0xF000000000000000
-  #define RISCV_SATP_MODE_BIT_POSITION  60
+#define RISCV_SATP_MODE_MASK          0xF000000000000000
+#define RISCV_SATP_MODE_BIT_POSITION  60
 #endif
-    #define RISCV_SATP_MODE_OFF         0
-    #define RISCV_SATP_MODE_SV32        1
-    #define RISCV_SATP_MODE_SV39        8
-    #define RISCV_SATP_MODE_SV48        9
-    #define RISCV_SATP_MODE_SV57        10
-    #define RISCV_SATP_MODE_SV64        11
+#define RISCV_SATP_MODE_OFF   0
+#define RISCV_SATP_MODE_SV32  1
+#define RISCV_SATP_MODE_SV39  8
+#define RISCV_SATP_MODE_SV48  9
+#define RISCV_SATP_MODE_SV57  10
+#define RISCV_SATP_MODE_SV64  11
 
-  #define SATP64_ASID_MASK              0x0FFFF00000000000
-  #define SATP64_PPN_MASK               0x00000FFFFFFFFFFF
+#define SATP64_ASID_MASK  0x0FFFF00000000000
+#define SATP64_PPN_MASK   0x00000FFFFFFFFFFF
 
 #define RISCV_CAUSE_MISALIGNED_FETCH        0x0
 #define RISCV_CAUSE_FETCH_ACCESS            0x1
@@ -146,17 +146,17 @@
 //
 // Machine Read-Write Shadow of Hypervisor Read-Only Registers
 //
-#define RISCV_CSR_HTIMEW                0xB01
-#define RISCV_CSR_HTIMEHW               0xB81
+#define RISCV_CSR_HTIMEW   0xB01
+#define RISCV_CSR_HTIMEHW  0xB81
 //
 // Machine Host-Target Interface (Non-Standard Berkeley Extension)
 //
-#define RISCV_CSR_MTOHOST               0x780
-#define RISCV_CSR_MFROMHOST             0x781
+#define RISCV_CSR_MTOHOST    0x780
+#define RISCV_CSR_MFROMHOST  0x781
 
 //
 // User mode CSR
 //
-#define RISCV_CSR_CYCLE                 0xc00
-#define RISCV_CSR_TIME                  0xc01
+#define RISCV_CSR_CYCLE  0xc00
+#define RISCV_CSR_TIME   0xc01
 #endif

+ 14 - 14
Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h

@@ -1,7 +1,7 @@
 /** @file
   SBI inline function calls.
 
-  Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+  Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -20,7 +20,7 @@
 #include <sbi/sbi_types.h>
 #include <sbi/sbi_hartmask.h>
 
-#define RISC_V_MAX_HART_SUPPORTED SBI_HARTMASK_MAX_BITS
+#define RISC_V_MAX_HART_SUPPORTED  SBI_HARTMASK_MAX_BITS
 
 typedef
 VOID
@@ -36,27 +36,27 @@ VOID
 // Keep the structure member in 64-bit alignment.
 //
 typedef struct {
-    UINT64                 IsaExtensionSupported;  // The ISA extension this core supported.
-    RISCV_UINT128          MachineVendorId;        // Machine vendor ID
-    RISCV_UINT128          MachineArchId;          // Machine Architecture ID
-    RISCV_UINT128          MachineImplId;          // Machine Implementation ID
-    RISCV_HART_SWITCH_MODE HartSwitchMode;         // OpenSBI's function to switch the mode of a hart
+  UINT64                    IsaExtensionSupported; // The ISA extension this core supported.
+  RISCV_UINT128             MachineVendorId;       // Machine vendor ID
+  RISCV_UINT128             MachineArchId;         // Machine Architecture ID
+  RISCV_UINT128             MachineImplId;         // Machine Implementation ID
+  RISCV_HART_SWITCH_MODE    HartSwitchMode;        // OpenSBI's function to switch the mode of a hart
 } EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC;
 #define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE  (64 * 8) // This is the size of EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
                                                       // structure. Referred by both C code and assembly code.
 
 typedef struct {
-  UINT64              BootHartId;
-  VOID                *PeiServiceTable;      // PEI Service table
-  UINT64              FlattenedDeviceTree;   // Pointer to Flattened Device tree
-  UINT64              SecPeiHandOffData;     // This is EFI_SEC_PEI_HAND_OFF passed to PEI Core.
-  EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC  *HartSpecific[RISC_V_MAX_HART_SUPPORTED];
+  UINT64                                      BootHartId;
+  VOID                                        *PeiServiceTable;    // PEI Service table
+  UINT64                                      FlattenedDeviceTree; // Pointer to Flattened Device tree
+  UINT64                                      SecPeiHandOffData;   // This is EFI_SEC_PEI_HAND_OFF passed to PEI Core.
+  EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC    *HartSpecific[RISC_V_MAX_HART_SUPPORTED];
 } EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;
 
 //
 // Typedefs of OpenSBI type to make them conform to EDK2 coding guidelines
 //
-typedef struct sbi_scratch SBI_SCRATCH;
-typedef struct sbi_platform SBI_PLATFORM;
+typedef struct sbi_scratch   SBI_SCRATCH;
+typedef struct sbi_platform  SBI_PLATFORM;
 
 #endif

+ 3 - 1
Silicon/RISC-V/ProcessorPkg/Include/Library/MachineModeTimerLib.h

@@ -10,6 +10,8 @@
 #define MACHINE_MODE_TIMER_LIB_H_
 
 UINT64
-RiscVReadMachineTimerInterface (VOID);
+RiscVReadMachineTimerInterface (
+  VOID
+  );
 
 #endif

+ 54 - 22
Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h

@@ -1,7 +1,7 @@
 /** @file
   RISC-V CPU library definitions.
 
-  Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+  Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -21,66 +21,98 @@ VOID
   );
 
 VOID
-RiscVSetMachineScratch (RISCV_MACHINE_MODE_CONTEXT *RiscvContext);
+RiscVSetMachineScratch (
+  RISCV_MACHINE_MODE_CONTEXT  *RiscvContext
+  );
 
 UINT32
-RiscVGetMachineScratch (VOID);
+RiscVGetMachineScratch (
+  VOID
+  );
 
 UINT32
-RiscVGetMachineTrapCause (VOID);
+RiscVGetMachineTrapCause (
+  VOID
+  );
 
 UINT64
-RiscVReadMachineTimer (VOID);
+RiscVReadMachineTimer (
+  VOID
+  );
 
 UINT64
-RiscVReadMachineTimerInterface (VOID);
+RiscVReadMachineTimerInterface (
+  VOID
+  );
 
 VOID
-RiscVSetMachineTimerCmp (UINT64);
+  RiscVSetMachineTimerCmp (UINT64);
 
 UINT64
-RiscVReadMachineTimerCmp(VOID);
+RiscVReadMachineTimerCmp (
+  VOID
+  );
 
 UINT64
-RiscVReadMachineInterruptEnable(VOID);
+RiscVReadMachineInterruptEnable (
+  VOID
+  );
 
 UINT64
-RiscVReadMachineInterruptPending(VOID);
+RiscVReadMachineInterruptPending (
+  VOID
+  );
 
 UINT64
-RiscVReadMachineStatus(VOID);
+RiscVReadMachineStatus (
+  VOID
+  );
 
 VOID
-RiscVWriteMachineStatus(UINT64);
+  RiscVWriteMachineStatus (UINT64);
 
 UINT64
-RiscVReadMachineTrapVector(VOID);
+RiscVReadMachineTrapVector (
+  VOID
+  );
 
 UINT64
-RiscVReadMachineIsa (VOID);
+RiscVReadMachineIsa (
+  VOID
+  );
 
 UINT64
-RiscVReadMachineVendorId (VOID);
+RiscVReadMachineVendorId (
+  VOID
+  );
 
 UINT64
-RiscVReadMachineArchitectureId (VOID);
+RiscVReadMachineArchitectureId (
+  VOID
+  );
 
 UINT64
-RiscVReadMachineImplementId (VOID);
+RiscVReadMachineImplementId (
+  VOID
+  );
 
 VOID
-RiscVSetSupervisorAddressTranslationRegister(UINT64);
+  RiscVSetSupervisorAddressTranslationRegister (UINT64);
 
 VOID
-RiscVSetSupervisorScratch (UINT64);
+  RiscVSetSupervisorScratch (UINT64);
 
 UINT64
-RiscVGetSupervisorScratch (VOID);
+RiscVGetSupervisorScratch (
+  VOID
+  );
 
 VOID
-RiscVSetSupervisorStvec (UINT64);
+  RiscVSetSupervisorStvec (UINT64);
 
 UINT64
-RiscVGetSupervisorStvec (VOID);
+RiscVGetSupervisorStvec (
+  VOID
+  );
 
 #endif

+ 61 - 61
Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h

@@ -21,20 +21,20 @@
 //
 // EDK2 OpenSBI Firmware extension.
 //
-#define SBI_EDK2_FW_EXT (SBI_EXT_FIRMWARE_START | SBI_OPENSBI_IMPID)
+#define SBI_EDK2_FW_EXT  (SBI_EXT_FIRMWARE_START | SBI_OPENSBI_IMPID)
 //
 // EDK2 OpenSBI Firmware extension functions.
 //
-#define SBI_EXT_FW_MSCRATCH_FUNC        0
-#define SBI_EXT_FW_MSCRATCH_HARTID_FUNC 1
+#define SBI_EXT_FW_MSCRATCH_FUNC         0
+#define SBI_EXT_FW_MSCRATCH_HARTID_FUNC  1
 
 //
 // EDK2 OpenSBI firmware extension return status.
 //
 typedef struct {
-  UINTN Error;   ///< SBI status code
-  UINTN Value;   ///< Value returned
-} SbiRet;
+  UINTN    Error; ///< SBI status code
+  UINTN    Value; ///< Value returned
+} SBI_RET;
 
 /**
   Get the implemented SBI specification version
@@ -48,7 +48,7 @@ typedef struct {
 VOID
 EFIAPI
 SbiGetSpecVersion (
-  OUT UINTN                       *SpecVersion
+  OUT UINTN  *SpecVersion
   );
 
 /**
@@ -62,7 +62,7 @@ SbiGetSpecVersion (
 VOID
 EFIAPI
 SbiGetImplId (
-  OUT UINTN                      *ImplId
+  OUT UINTN  *ImplId
   );
 
 /**
@@ -76,7 +76,7 @@ SbiGetImplId (
 VOID
 EFIAPI
 SbiGetImplVersion (
-  OUT UINTN                       *ImplVersion
+  OUT UINTN  *ImplVersion
   );
 
 /**
@@ -91,8 +91,8 @@ SbiGetImplVersion (
 VOID
 EFIAPI
 SbiProbeExtension (
-  IN  INTN                         ExtensionId,
-  OUT INTN                        *ProbeResult
+  IN  INTN  ExtensionId,
+  OUT INTN  *ProbeResult
   );
 
 /**
@@ -105,7 +105,7 @@ SbiProbeExtension (
 VOID
 EFIAPI
 SbiGetMachineVendorId (
-  OUT UINTN                       *MachineVendorId
+  OUT UINTN  *MachineVendorId
   );
 
 /**
@@ -118,7 +118,7 @@ SbiGetMachineVendorId (
 VOID
 EFIAPI
 SbiGetMachineArchId (
-  OUT UINTN                       *MachineArchId
+  OUT UINTN  *MachineArchId
   );
 
 /**
@@ -131,7 +131,7 @@ SbiGetMachineArchId (
 VOID
 EFIAPI
 SbiGetMachineImplId (
-  OUT UINTN                       *MachineImplId
+  OUT UINTN  *MachineImplId
   );
 
 /**
@@ -160,9 +160,9 @@ SbiGetMachineImplId (
 EFI_STATUS
 EFIAPI
 SbiHartStart (
-  IN  UINTN                          HartId,
-  IN  UINTN                          StartAddr,
-  IN  UINTN                          Priv
+  IN  UINTN  HartId,
+  IN  UINTN  StartAddr,
+  IN  UINTN  Priv
   );
 
 /**
@@ -199,8 +199,8 @@ SbiHartStop (
 EFI_STATUS
 EFIAPI
 SbiHartGetStatus (
-  IN  UINTN                          HartId,
-  OUT UINTN                         *HartStatus
+  IN  UINTN  HartId,
+  OUT UINTN  *HartStatus
   );
 
 ///
@@ -218,7 +218,7 @@ SbiHartGetStatus (
 VOID
 EFIAPI
 SbiSetTimer (
-  IN  UINT64                         Time
+  IN  UINT64  Time
   );
 
 ///
@@ -244,8 +244,8 @@ SbiSetTimer (
 EFI_STATUS
 EFIAPI
 SbiSendIpi (
-  IN  UINTN                         *HartMask,
-  IN  UINTN                          HartMaskBase
+  IN  UINTN  *HartMask,
+  IN  UINTN  HartMaskBase
   );
 
 ///
@@ -268,8 +268,8 @@ SbiSendIpi (
 EFI_STATUS
 EFIAPI
 SbiRemoteFenceI (
-  IN  UINTN                         *HartMask,
-  IN  UINTN                          HartMaskBase
+  IN  UINTN  *HartMask,
+  IN  UINTN  HartMaskBase
   );
 
 /**
@@ -296,10 +296,10 @@ SbiRemoteFenceI (
 EFI_STATUS
 EFIAPI
 SbiRemoteSfenceVma (
-  IN  UINTN                         *HartMask,
-  IN  UINTN                          HartMaskBase,
-  IN  UINTN                          StartAddr,
-  IN  UINTN                          Size
+  IN  UINTN  *HartMask,
+  IN  UINTN  HartMaskBase,
+  IN  UINTN  StartAddr,
+  IN  UINTN  Size
   );
 
 /**
@@ -327,11 +327,11 @@ SbiRemoteSfenceVma (
 EFI_STATUS
 EFIAPI
 SbiRemoteSfenceVmaAsid (
-  IN  UINTN                         *HartMask,
-  IN  UINTN                          HartMaskBase,
-  IN  UINTN                          StartAddr,
-  IN  UINTN                          Size,
-  IN  UINTN                          Asid
+  IN  UINTN  *HartMask,
+  IN  UINTN  HartMaskBase,
+  IN  UINTN  StartAddr,
+  IN  UINTN  Size,
+  IN  UINTN  Asid
   );
 
 /**
@@ -363,11 +363,11 @@ SbiRemoteSfenceVmaAsid (
 EFI_STATUS
 EFIAPI
 SbiRemoteHfenceGvmaVmid (
-  IN  UINTN                         *HartMask,
-  IN  UINTN                          HartMaskBase,
-  IN  UINTN                          StartAddr,
-  IN  UINTN                          Size,
-  IN  UINTN                          Vmid
+  IN  UINTN  *HartMask,
+  IN  UINTN  HartMaskBase,
+  IN  UINTN  StartAddr,
+  IN  UINTN  Size,
+  IN  UINTN  Vmid
   );
 
 /**
@@ -398,10 +398,10 @@ SbiRemoteHfenceGvmaVmid (
 EFI_STATUS
 EFIAPI
 SbiRemoteHfenceGvma (
-  IN  UINTN                         *HartMask,
-  IN  UINTN                          HartMaskBase,
-  IN  UINTN                          StartAddr,
-  IN  UINTN                          Size
+  IN  UINTN  *HartMask,
+  IN  UINTN  HartMaskBase,
+  IN  UINTN  StartAddr,
+  IN  UINTN  Size
   );
 
 /**
@@ -433,11 +433,11 @@ SbiRemoteHfenceGvma (
 EFI_STATUS
 EFIAPI
 SbiRemoteHfenceVvmaAsid (
-  IN  UINTN                         *HartMask,
-  IN  UINTN                          HartMaskBase,
-  IN  UINTN                          StartAddr,
-  IN  UINTN                          Size,
-  IN  UINTN                          Asid
+  IN  UINTN  *HartMask,
+  IN  UINTN  HartMaskBase,
+  IN  UINTN  StartAddr,
+  IN  UINTN  Size,
+  IN  UINTN  Asid
   );
 
 /**
@@ -468,10 +468,10 @@ SbiRemoteHfenceVvmaAsid (
 EFI_STATUS
 EFIAPI
 SbiRemoteHfenceVvma (
-  IN  UINTN                         *HartMask,
-  IN  UINTN                          HartMaskBase,
-  IN  UINTN                          StartAddr,
-  IN  UINTN                          Size
+  IN  UINTN  *HartMask,
+  IN  UINTN  HartMaskBase,
+  IN  UINTN  StartAddr,
+  IN  UINTN  Size
   );
 
 ///
@@ -506,8 +506,8 @@ SbiRemoteHfenceVvma (
 EFI_STATUS
 EFIAPI
 SbiSystemReset (
-  IN  UINTN                          ResetType,
-  IN  UINTN                          ResetReason
+  IN  UINTN  ResetType,
+  IN  UINTN  ResetReason
   );
 
 ///
@@ -531,9 +531,9 @@ SbiSystemReset (
 EFI_STATUS
 EFIAPI
 SbiVendorCall (
-  IN  UINTN                          ExtensionId,
-  IN  UINTN                          FunctionId,
-  IN  UINTN                          NumArgs,
+  IN  UINTN  ExtensionId,
+  IN  UINTN  FunctionId,
+  IN  UINTN  NumArgs,
   ...
   );
 
@@ -555,7 +555,7 @@ SbiVendorCall (
 VOID
 EFIAPI
 SbiGetMscratch (
-  OUT SBI_SCRATCH                    **ScratchSpace
+  OUT SBI_SCRATCH  **ScratchSpace
   );
 
 /**
@@ -567,8 +567,8 @@ SbiGetMscratch (
 VOID
 EFIAPI
 SbiGetMscratchHartid (
-  IN  UINTN                            HartId,
-  OUT SBI_SCRATCH                    **ScratchSpace
+  IN  UINTN        HartId,
+  OUT SBI_SCRATCH  **ScratchSpace
   );
 
 /**
@@ -579,7 +579,7 @@ SbiGetMscratchHartid (
 VOID
 EFIAPI
 SbiGetFirmwareContext (
-  OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContext
+  OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT  **FirmwareContext
   );
 
 /**
@@ -590,7 +590,7 @@ SbiGetFirmwareContext (
 VOID
 EFIAPI
 SbiSetFirmwareContext (
-  IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext
+  IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT  *FirmwareContext
   );
 
 #endif

+ 3 - 3
Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h

@@ -1,7 +1,7 @@
 /** @file
   Library to get/set Firmware Context.
 
-  Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
+  Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -24,7 +24,7 @@
 VOID
 EFIAPI
 GetFirmwareContextPointer (
-  IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+  IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT  **FirmwareContextPtr
   );
 
 /**
@@ -37,7 +37,7 @@ GetFirmwareContextPointer (
 VOID
 EFIAPI
 SetFirmwareContextPointer (
-  IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+  IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT  *FirmwareContextPtr
   );
 
 #endif

+ 7 - 3
Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVPlatformTimerLib.h

@@ -10,12 +10,16 @@
 #define RISCV_PLATFORM_TIMER_LIB_H_
 
 UINT64
-RiscVReadMachineTimer (VOID);
+RiscVReadMachineTimer (
+  VOID
+  );
 
 VOID
-RiscVSetMachineTimerCmp (UINT64);
+  RiscVSetMachineTimerCmp (UINT64);
 
 UINT64
-RiscVReadMachineTimerCmp(VOID);
+RiscVReadMachineTimerCmp (
+  VOID
+  );
 
 #endif

+ 35 - 34
Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h

@@ -6,14 +6,15 @@
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
+
 #ifndef EDK2_SBI_TYPES_H_
 #define EDK2_SBI_TYPES_H_
 
 #include <Base.h>
 
-typedef INT8    s8;
-typedef UINT8   u8;
-typedef UINT8   uint8_t;
+typedef INT8   s8;
+typedef UINT8  u8;
+typedef UINT8  uint8_t;
 
 typedef INT16   s16;
 typedef UINT16  u16;
@@ -32,49 +33,49 @@ typedef UINT64  uint64_t;
 
 // PRILX is not used in EDK2 but we need to define it here because when
 // defining our own types, this constant is not defined but used by OpenSBI.
-#define PRILX   "016lx"
-
-typedef BOOLEAN  bool;
-typedef unsigned long   ulong;
-typedef UINT64   uintptr_t;
-typedef UINT64   size_t;
-typedef INT64    ssize_t;
-typedef UINT64   virtual_addr_t;
-typedef UINT64   virtual_size_t;
-typedef UINT64   physical_addr_t;
-typedef UINT64   physical_size_t;
-
-#define true            TRUE
-#define false           FALSE
-
-#define __packed        __attribute__((packed))
-#define __noreturn      __attribute__((noreturn))
-#define __aligned(x)    __attribute__((aligned(x)))
-
-#if defined(__GNUC__) || defined(__clang__)
-  #define likely(x) __builtin_expect((x), 1)
-  #define unlikely(x) __builtin_expect((x), 0)
+#define PRILX  "016lx"
+
+typedef BOOLEAN        bool;
+typedef unsigned long  ulong;
+typedef UINT64         uintptr_t;
+typedef UINT64         size_t;
+typedef INT64          ssize_t;
+typedef UINT64         virtual_addr_t;
+typedef UINT64         virtual_size_t;
+typedef UINT64         physical_addr_t;
+typedef UINT64         physical_size_t;
+
+#define true   TRUE
+#define false  FALSE
+
+#define __packed    __attribute__((packed))
+#define __noreturn  __attribute__((noreturn))
+#define __aligned(x)  __attribute__((aligned(x)))
+
+#if defined (__GNUC__) || defined (__clang__)
+#define likely(x)    __builtin_expect((x), 1)
+#define unlikely(x)  __builtin_expect((x), 0)
 #else
-  #define likely(x) (x)
-  #define unlikely(x) (x)
+#define likely(x)    (x)
+#define unlikely(x)  (x)
 #endif
 
 #undef offsetof
 #ifdef __compiler_offsetof
-#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE,MEMBER)
+#define offsetof(TYPE, MEMBER)  __compiler_offsetof(TYPE,MEMBER)
 #else
-#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+#define offsetof(TYPE, MEMBER)  ((size_t) &((TYPE *)0)->MEMBER)
 #endif
 
-#define container_of(ptr, type, member) ({            \
+#define container_of(ptr, type, member)  ({           \
   const typeof(((type *)0)->member) * __mptr = (ptr); \
   (type *)((char *)__mptr - offsetof(type, member)); })
 
-#define array_size(x)   (sizeof(x) / sizeof((x)[0]))
+#define array_size(x)  (sizeof(x) / sizeof((x)[0]))
 
-#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
-#define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b))
-#define ROUNDDOWN(a, b) ((a) / (b) * (b))
+#define CLAMP(a, lo, hi)  MIN(MAX(a, lo), hi)
+#define ROUNDUP(a, b)     ((((a)-1) / (b) + 1) * (b))
+#define ROUNDDOWN(a, b)   ((a) / (b) * (b))
 
 /* clang-format on */
 

+ 52 - 51
Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h

@@ -6,6 +6,7 @@
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
+
 #ifndef RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_
 #define RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_
 
@@ -13,10 +14,10 @@
 #include <IndustryStandard/SmBios.h>
 #include <SmbiosProcessorSpecificData.h>
 
-#define TO_BE_FILLED 0
-#define TO_BE_FILLED_BY_VENDOR 0
-#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0
-#define TO_BE_FILLED_BY_CODE 0
+#define TO_BE_FILLED                              0
+#define TO_BE_FILLED_BY_VENDOR                    0
+#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER  0
+#define TO_BE_FILLED_BY_CODE                      0
 
 #pragma pack(1)
 
@@ -24,71 +25,71 @@
 /// RISC-V processor specific data HOB
 ///
 typedef struct {
-  EFI_GUID ParentProcessorGuid;
-  UINTN    ParentProcessorUid;
-  EFI_GUID CoreGuid;
-  VOID     *Context;        // The additional information of this core which
-                            // built in PEI phase and carried to DXE phase.
-                            // The content is processor or platform specific.
-  SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;
+  EFI_GUID                                 ParentProcessorGuid;
+  UINTN                                    ParentProcessorUid;
+  EFI_GUID                                 CoreGuid;
+  VOID                                     *Context; // The additional information of this core which
+                                                     // built in PEI phase and carried to DXE phase.
+                                                     // The content is processor or platform specific.
+  SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA    ProcessorSpecificData;
 } RISC_V_PROCESSOR_SPECIFIC_HOB_DATA;
 
 ///
 /// RISC-V SMBIOS type 4 (Processor) GUID data HOB
 ///
 typedef struct {
-  EFI_GUID           ProcessorGuid;
-  UINTN              ProcessorUid;
-  SMBIOS_TABLE_TYPE4 SmbiosType4Processor;
-  UINT16             EndingZero;
+  EFI_GUID              ProcessorGuid;
+  UINTN                 ProcessorUid;
+  SMBIOS_TABLE_TYPE4    SmbiosType4Processor;
+  UINT16                EndingZero;
 } RISC_V_PROCESSOR_TYPE4_HOB_DATA;
 
-#define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF
-
-#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7
-   #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01
-   #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02
-   #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03
-
-#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3
-#define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
-  #define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
-
-#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5
-#define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
-  #define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
-  #define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
-  #define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
-  #define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN  (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
-
-#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7
-#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK       (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
-  #define RISC_V_CACHE_CONFIGURATION_ENABLED           (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
-
-#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8
-#define RISC_V_CACHE_CONFIGURATION_MODE_MASK       (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
-  #define RISC_V_CACHE_CONFIGURATION_MODE_WT       (0x0 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
-  #define RISC_V_CACHE_CONFIGURATION_MODE_WB       (0x1 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
-  #define RISC_V_CACHE_CONFIGURATION_MODE_VARIES   (0x2 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
-  #define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN  (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+#define RISC_V_CACHE_INFO_NOT_PROVIDED  0xFFFF
+
+#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK  0x7
+#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1     0x01
+#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2     0x02
+#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3     0x03
+
+#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION  3
+#define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK          (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED      (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION  5
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK          (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL      (0x0 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL      (0x1 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED      (0x2 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN       (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION  7
+#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK          (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_ENABLED              (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION  8
+#define RISC_V_CACHE_CONFIGURATION_MODE_MASK          (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_MODE_WT            (0x0 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_MODE_WB            (0x1 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_MODE_VARIES        (0x2 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+#define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN       (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
 ///
 /// RISC-V SMBIOS type 7 (Cache) GUID data HOB
 ///
 typedef struct {
-  EFI_GUID           ProcessorGuid;
-  UINTN              ProcessorUid;
-  SMBIOS_TABLE_TYPE7 SmbiosType7Cache;
-  UINT16             EndingZero;
+  EFI_GUID              ProcessorGuid;
+  UINTN                 ProcessorUid;
+  SMBIOS_TABLE_TYPE7    SmbiosType7Cache;
+  UINT16                EndingZero;
 } RISC_V_PROCESSOR_TYPE7_HOB_DATA;
 
 ///
 /// RISC-V SMBIOS type 7 (Cache) GUID data HOB
 ///
 typedef struct {
-  RISC_V_PROCESSOR_TYPE4_HOB_DATA *Processor;
-  RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1Cache;
-  RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2Cache;
-  RISC_V_PROCESSOR_TYPE7_HOB_DATA *L3Cache;
+  RISC_V_PROCESSOR_TYPE4_HOB_DATA    *Processor;
+  RISC_V_PROCESSOR_TYPE7_HOB_DATA    *L1Cache;
+  RISC_V_PROCESSOR_TYPE7_HOB_DATA    *L2Cache;
+  RISC_V_PROCESSOR_TYPE7_HOB_DATA    *L3Cache;
 } RISC_V_PROCESSOR_SMBIOS_HOB_DATA;
 
 #pragma pack()

+ 26 - 26
Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h

@@ -1,7 +1,7 @@
 /** @file
   RISC-V package definitions.
 
-  Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+  Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -20,7 +20,7 @@
   .p2align  2                     ; \
   Name:
 
-#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
+#define ASM_FUNC(Name)  _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
 
 #if defined (MDE_CPU_RISCV64)
 typedef UINT64 RISC_V_REGS_PROTOTYPE;
@@ -31,8 +31,8 @@ typedef UINT64 RISC_V_REGS_PROTOTYPE;
 // Structure for 128-bit value
 //
 typedef struct {
-  UINT64            Value64_L;
-  UINT64            Value64_H;
+  UINT64    Value64_L;
+  UINT64    Value64_H;
 } RISCV_UINT128;
 
 #define RISCV_MACHINE_CONTEXT_SIZE  0x1000
@@ -42,46 +42,46 @@ typedef struct _RISCV_MACHINE_MODE_CONTEXT RISCV_MACHINE_MODE_CONTEXT;
 /// Exception handlers in context.
 ///
 typedef struct _EXCEPTION_HANDLER_CONTEXT {
-  EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander;
-  EFI_PHYSICAL_ADDRESS InstAccessFaultHander;
-  EFI_PHYSICAL_ADDRESS IllegalInstHander;
-  EFI_PHYSICAL_ADDRESS BreakpointHander;
-  EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander;
-  EFI_PHYSICAL_ADDRESS LoadAccessFaultHander;
-  EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander;
-  EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander;
-  EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander;
-  EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander;
-  EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander;
-  EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander;
+  EFI_PHYSICAL_ADDRESS    InstAddressMisalignedHander;
+  EFI_PHYSICAL_ADDRESS    InstAccessFaultHander;
+  EFI_PHYSICAL_ADDRESS    IllegalInstHander;
+  EFI_PHYSICAL_ADDRESS    BreakpointHander;
+  EFI_PHYSICAL_ADDRESS    LoadAddrMisalignedHander;
+  EFI_PHYSICAL_ADDRESS    LoadAccessFaultHander;
+  EFI_PHYSICAL_ADDRESS    StoreAmoAddrMisalignedHander;
+  EFI_PHYSICAL_ADDRESS    StoreAmoAccessFaultHander;
+  EFI_PHYSICAL_ADDRESS    EnvCallFromUModeHander;
+  EFI_PHYSICAL_ADDRESS    EnvCallFromSModeHander;
+  EFI_PHYSICAL_ADDRESS    EnvCallFromHModeHander;
+  EFI_PHYSICAL_ADDRESS    EnvCallFromMModeHander;
 } EXCEPTION_HANDLER_CONTEXT;
 
 ///
 /// Exception handlers in context.
 ///
 typedef struct _INTERRUPT_HANDLER_CONTEXT {
-  EFI_PHYSICAL_ADDRESS SoftwareIntHandler;
-  EFI_PHYSICAL_ADDRESS TimerIntHandler;
+  EFI_PHYSICAL_ADDRESS    SoftwareIntHandler;
+  EFI_PHYSICAL_ADDRESS    TimerIntHandler;
 } INTERRUPT_HANDLER_CONTEXT;
 
 ///
 /// Interrupt handlers in context.
 ///
 typedef struct _TRAP_HANDLER_CONTEXT {
-  EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext;
-  INTERRUPT_HANDLER_CONTEXT IntHandlerContext;
+  EXCEPTION_HANDLER_CONTEXT    ExceptionHandlerContext;
+  INTERRUPT_HANDLER_CONTEXT    IntHandlerContext;
 } TRAP_HANDLER_CONTEXT;
 
 ///
 /// Machine mode context used for saveing hart-local context.
 ///
 typedef struct _RISCV_MACHINE_MODE_CONTEXT {
-  EFI_PHYSICAL_ADDRESS PeiService;                /// PEI service.
-  EFI_PHYSICAL_ADDRESS MachineModeTrapHandler;    /// Machine mode trap handler.
-  EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor mode trap handler.
-  EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor mode trap handler.
-  EFI_PHYSICAL_ADDRESS UserModeTrapHandler;       /// USer mode trap handler.
-  TRAP_HANDLER_CONTEXT MModeHandler;              /// Handler for machine mode.
+  EFI_PHYSICAL_ADDRESS    PeiService;                /// PEI service.
+  EFI_PHYSICAL_ADDRESS    MachineModeTrapHandler;    /// Machine mode trap handler.
+  EFI_PHYSICAL_ADDRESS    HypervisorModeTrapHandler; /// Hypervisor mode trap handler.
+  EFI_PHYSICAL_ADDRESS    SupervisorModeTrapHandler; /// Supervisor mode trap handler.
+  EFI_PHYSICAL_ADDRESS    UserModeTrapHandler;       /// USer mode trap handler.
+  TRAP_HANDLER_CONTEXT    MModeHandler;              /// Handler for machine mode.
 } RISCV_MACHINE_MODE_CONTEXT;
 
 #endif

+ 23 - 23
Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h

@@ -8,6 +8,7 @@
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
+
 #ifndef SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_
 #define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_
 
@@ -16,42 +17,41 @@
 
 #pragma pack(1)
 
-typedef enum{
+typedef enum {
   RegisterUnsupported = 0x00,
   RegisterLen32       = 0x01,
   RegisterLen64       = 0x02,
   RegisterLen128      = 0x03
 } RISC_V_REGISTER_LENGTH;
 
-#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION 0x100
+#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION  0x100
 
-#define SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED    (0x01 << 0)
-#define SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED (0x01 << 2)
-#define SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED       (0x01 << 3)
-#define SMBIOS_RISC_V_PSD_DEBUG_MODE_SUPPORTED      (0x01 << 7)
+#define SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED     (0x01 << 0)
+#define SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED  (0x01 << 2)
+#define SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED        (0x01 << 3)
+#define SMBIOS_RISC_V_PSD_DEBUG_MODE_SUPPORTED       (0x01 << 7)
 
 ///
 /// RISC-V processor specific data for SMBIOS type 44
 ///
 typedef struct {
-  UINT16            Revision;
-  UINT8             Length;
-  RISCV_UINT128     HartId;
-  UINT8             BootHartId;
-  RISCV_UINT128     MachineVendorId;
-  RISCV_UINT128     MachineArchId;
-  RISCV_UINT128     MachineImplId;
-  UINT32            InstSetSupported;
-  UINT8             PrivilegeModeSupported;
-  RISCV_UINT128     MModeExcepDelegation;
-  RISCV_UINT128     MModeInterruptDelegation;
-  UINT8             HartXlen;
-  UINT8             MachineModeXlen;
-  UINT8             Reserved;
-  UINT8             SupervisorModeXlen;
-  UINT8             UserModeXlen;
+  UINT16           Revision;
+  UINT8            Length;
+  RISCV_UINT128    HartId;
+  UINT8            BootHartId;
+  RISCV_UINT128    MachineVendorId;
+  RISCV_UINT128    MachineArchId;
+  RISCV_UINT128    MachineImplId;
+  UINT32           InstSetSupported;
+  UINT8            PrivilegeModeSupported;
+  RISCV_UINT128    MModeExcepDelegation;
+  RISCV_UINT128    MModeInterruptDelegation;
+  UINT8            HartXlen;
+  UINT8            MachineModeXlen;
+  UINT8            Reserved;
+  UINT8            SupervisorModeXlen;
+  UINT8            UserModeXlen;
 } SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA;
 
 #pragma pack()
 #endif
-

+ 4 - 11
Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni

@@ -1,23 +1,16 @@
 // /** @file
 //
 // Instance of PEI Services Table Pointer Library using RISC-V OpenSBI FirmwareContext.
-//
 // PEI Services Table Pointer Library implementation that retrieves a pointer to the
 // PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context structure.
 //
-// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2029-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 //
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php.
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+// SPDX-License-Identifier: BSD-2-Clause-Patent
 //
 // **/
 
-
 #string STR_MODULE_ABSTRACT             #language en-US "Instance of PEI Services Table Pointer Library using global variable for the table pointer"
-
-#string STR_MODULE_DESCRIPTION          #language en-US "The PEI Services Table Pointer Library implementation that retrieves a pointer to the PEI Services Table from a global variable. Not available to modules that execute from read-only memory."
+#string STR_MODULE_DESCRIPTION          #language en-US "The PEI Services Table Pointer Library implementation that retrieves a pointer to the PEI Services Table from a global variable."
+                                                        "Not available to modules that execute from read-only memory."
 

+ 12 - 10
Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c

@@ -1,7 +1,7 @@
 /** @file
   PEI Services Table Pointer Library.
 
-  Copyright (c) 2019 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+  Copyright (c) 2019 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -28,18 +28,20 @@
 VOID
 EFIAPI
 SetPeiServicesTablePointer (
-  IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer
+  IN CONST EFI_PEI_SERVICES  **PeiServicesTablePointer
   )
 {
-  EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+  EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT  *FirmwareContext;
 
   GetFirmwareContextPointer (&FirmwareContext);
   FirmwareContext->PeiServiceTable = (VOID *)(UINTN)PeiServicesTablePointer;
 
-  DEBUG ((DEBUG_INFO, "Set PEI Service 0x%x at OpenSBI Firmware Context at 0x%x\n",
-         PeiServicesTablePointer,
-         FirmwareContext
-         ));
+  DEBUG ((
+    DEBUG_INFO,
+    "Set PEI Service 0x%x at OpenSBI Firmware Context at 0x%x\n",
+    PeiServicesTablePointer,
+    FirmwareContext
+    ));
 }
 
 /**
@@ -60,7 +62,7 @@ GetPeiServicesTablePointer (
   VOID
   )
 {
-  EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+  EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT  *FirmwareContext;
 
   GetFirmwareContextPointer (&FirmwareContext);
   return (CONST EFI_PEI_SERVICES **)FirmwareContext->PeiServiceTable;
@@ -81,8 +83,8 @@ GetPeiServicesTablePointer (
 EFI_STATUS
 EFIAPI
 PeiServicesTablePointerLibOpenSbiConstructor (
-  IN EFI_PEI_FILE_HANDLE        FileHandle,
-  IN CONST EFI_PEI_SERVICES     **PeiServices
+  IN EFI_PEI_FILE_HANDLE     FileHandle,
+  IN CONST EFI_PEI_SERVICES  **PeiServices
   )
 {
   SetPeiServicesTablePointer (PeiServices);

+ 346 - 255
Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c

@@ -31,14 +31,13 @@
 #include <sbi/sbi_types.h>
 #include <sbi/sbi_init.h>
 
-
 //
 // Maximum arguments for SBI ecall
 // It's possible to pass more but no SBI call uses more as of SBI 0.2.
 // The additional arguments would have to be passed on the stack instead of as
 // registers, like it's done now.
 //
-#define SBI_CALL_MAX_ARGS 6
+#define SBI_CALL_MAX_ARGS  6
 
 /**
   Call SBI call using ecall instruction.
@@ -50,53 +49,55 @@
   @param[in] NumArgs  Number of arguments to pass to the ecall.
   @param[in] ...      Argument list for the ecall.
 
-  @retval  Returns SbiRet structure with value and error code.
+  @retval  Returns SBI_RET structure with value and error code.
 
 **/
 STATIC
-SbiRet
+SBI_RET
 EFIAPI
-SbiCall(
-  IN  UINTN ExtId,
-  IN  UINTN FuncId,
-  IN  UINTN NumArgs,
+SbiCall (
+  IN  UINTN  ExtId,
+  IN  UINTN  FuncId,
+  IN  UINTN  NumArgs,
   ...
   )
 {
-    UINTN I;
-    SbiRet Ret;
-    UINTN Args[SBI_CALL_MAX_ARGS];
-    VA_LIST ArgList;
-    VA_START (ArgList, NumArgs);
-
-    ASSERT (NumArgs <= SBI_CALL_MAX_ARGS);
-
-    for (I = 0; I < SBI_CALL_MAX_ARGS; I++) {
-      if (I < NumArgs) {
-        Args[I] = VA_ARG (ArgList, UINTN);
-      } else {
-        // Default to 0 for all arguments that are not given
-        Args[I] = 0;
-      }
+  UINTN    I;
+  SBI_RET  Ret;
+  UINTN    Args[SBI_CALL_MAX_ARGS];
+  VA_LIST  ArgList;
+
+  VA_START (ArgList, NumArgs);
+
+  ASSERT (NumArgs <= SBI_CALL_MAX_ARGS);
+
+  for (I = 0; I < SBI_CALL_MAX_ARGS; I++) {
+    if (I < NumArgs) {
+      Args[I] = VA_ARG (ArgList, UINTN);
+    } else {
+      // Default to 0 for all arguments that are not given
+      Args[I] = 0;
     }
+  }
 
-    VA_END(ArgList);
-
-    register UINTN a0 asm ("a0") = Args[0];
-    register UINTN a1 asm ("a1") = Args[1];
-    register UINTN a2 asm ("a2") = Args[2];
-    register UINTN a3 asm ("a3") = Args[3];
-    register UINTN a4 asm ("a4") = Args[4];
-    register UINTN a5 asm ("a5") = Args[5];
-    register UINTN a6 asm ("a6") = (UINTN)(FuncId);
-    register UINTN a7 asm ("a7") = (UINTN)(ExtId);
-    asm volatile ("ecall" \
-         : "+r" (a0), "+r" (a1) \
-         : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) \
-         : "memory"); \
-    Ret.Error = a0;
-    Ret.Value = a1;
-    return Ret;
+  VA_END (ArgList);
+
+  register UINTN  a0 asm ("a0") = Args[0];
+  register UINTN  a1 asm ("a1") = Args[1];
+  register UINTN  a2 asm ("a2") = Args[2];
+  register UINTN  a3 asm ("a3") = Args[3];
+  register UINTN  a4 asm ("a4") = Args[4];
+  register UINTN  a5 asm ("a5") = Args[5];
+  register UINTN  a6 asm ("a6") = (UINTN)(FuncId);
+  register UINTN  a7 asm ("a7") = (UINTN)(ExtId);
+
+  asm volatile ("ecall" \
+       : "+r" (a0), "+r" (a1) \
+       : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) \
+       : "memory"); \
+  Ret.Error = a0;
+  Ret.Value = a1;
+  return Ret;
 }
 
 /**
@@ -105,12 +106,11 @@ SbiCall(
   @param[in] SbiError   SBI error code
   @retval EFI_STATUS
 **/
-
 STATIC
 EFI_STATUS
 EFIAPI
-TranslateError(
-  IN  UINTN SbiError
+TranslateError (
+  IN  UINTN  SbiError
   )
 {
   switch (SbiError) {
@@ -160,10 +160,12 @@ TranslateError(
 VOID
 EFIAPI
 SbiGetSpecVersion (
-  OUT UINTN                       *SpecVersion
+  OUT UINTN  *SpecVersion
   )
 {
-  SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0);
+  SBI_RET  Ret;
+
+  Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0);
 
   if (!Ret.Error) {
     *SpecVersion = (UINTN)Ret.Value;
@@ -181,10 +183,13 @@ SbiGetSpecVersion (
 VOID
 EFIAPI
 SbiGetImplId (
-  OUT UINTN                       *ImplId
+  OUT UINTN  *ImplId
   )
 {
-  SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID, 0);
+  SBI_RET  Ret;
+
+  Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_ID, 0);
+
   *ImplId = (UINTN)Ret.Value;
 }
 
@@ -199,10 +204,13 @@ SbiGetImplId (
 VOID
 EFIAPI
 SbiGetImplVersion (
-  OUT UINTN                       *ImplVersion
+  OUT UINTN  *ImplVersion
   )
 {
-  SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_VERSION, 0);
+  SBI_RET  Ret;
+
+  Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_IMP_VERSION, 0);
+
   *ImplVersion = (UINTN)Ret.Value;
 }
 
@@ -218,11 +226,14 @@ SbiGetImplVersion (
 VOID
 EFIAPI
 SbiProbeExtension (
-  IN  INTN                         ExtensionId,
-  OUT INTN                        *ProbeResult
+  IN  INTN  ExtensionId,
+  OUT INTN  *ProbeResult
   )
 {
-  SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, 0);
+  SBI_RET  Ret;
+
+  Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, 0);
+
   *ProbeResult = (UINTN)Ret.Value;
 }
 
@@ -236,10 +247,13 @@ SbiProbeExtension (
 VOID
 EFIAPI
 SbiGetMachineVendorId (
-  OUT UINTN                       *MachineVendorId
+  OUT UINTN  *MachineVendorId
   )
 {
-  SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MVENDORID, 0);
+  SBI_RET  Ret;
+
+  Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MVENDORID, 0);
+
   *MachineVendorId = (UINTN)Ret.Value;
 }
 
@@ -253,10 +267,13 @@ SbiGetMachineVendorId (
 VOID
 EFIAPI
 SbiGetMachineArchId (
-  OUT UINTN                       *MachineArchId
+  OUT UINTN  *MachineArchId
   )
 {
-  SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MARCHID, 0);
+  SBI_RET  Ret;
+
+  Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MARCHID, 0);
+
   *MachineArchId = (UINTN)Ret.Value;
 }
 
@@ -270,10 +287,13 @@ SbiGetMachineArchId (
 VOID
 EFIAPI
 SbiGetMachineImplId (
-  OUT UINTN                       *MachineImplId
+  OUT UINTN  *MachineImplId
   )
 {
-  SbiRet Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MIMPID, 0);
+  SBI_RET  Ret;
+
+  Ret = SbiCall (SBI_EXT_BASE, SBI_EXT_BASE_GET_MIMPID, 0);
+
   *MachineImplId = (UINTN)Ret.Value;
 }
 
@@ -307,19 +327,22 @@ SbiGetMachineImplId (
 EFI_STATUS
 EFIAPI
 SbiHartStart (
-  IN  UINTN                          HartId,
-  IN  UINTN                          StartAddr,
-  IN  UINTN                          Priv
+  IN  UINTN  HartId,
+  IN  UINTN  StartAddr,
+  IN  UINTN  Priv
   )
 {
-  SbiRet Ret = SbiCall (
-                 SBI_EXT_HSM,
-                 SBI_EXT_HSM_HART_START,
-                 3,
-                 HartId,
-                 StartAddr,
-                 Priv
-                 );
+  SBI_RET  Ret;
+
+  Ret = SbiCall (
+          SBI_EXT_HSM,
+          SBI_EXT_HSM_HART_START,
+          3,
+          HartId,
+          StartAddr,
+          Priv
+          );
+
   return TranslateError (Ret.Error);
 }
 
@@ -337,7 +360,10 @@ EFIAPI
 SbiHartStop (
   )
 {
-  SbiRet Ret = SbiCall (SBI_EXT_HSM, SBI_EXT_HSM_HART_STOP, 0);
+  SBI_RET  Ret;
+
+  Ret = SbiCall (SBI_EXT_HSM, SBI_EXT_HSM_HART_STOP, 0);
+
   return TranslateError (Ret.Error);
 }
 
@@ -361,11 +387,13 @@ SbiHartStop (
 EFI_STATUS
 EFIAPI
 SbiHartGetStatus (
-  IN  UINTN                          HartId,
-  OUT UINTN                         *HartStatus
+  IN  UINTN  HartId,
+  OUT UINTN  *HartStatus
   )
 {
-  SbiRet Ret = SbiCall (SBI_EXT_HSM, SBI_EXT_HSM_HART_GET_STATUS, 1, HartId);
+  SBI_RET  Ret;
+
+  Ret = SbiCall (SBI_EXT_HSM, SBI_EXT_HSM_HART_GET_STATUS, 1, HartId);
 
   if (!Ret.Error) {
     *HartStatus = (UINTN)Ret.Value;
@@ -385,7 +413,7 @@ SbiHartGetStatus (
 VOID
 EFIAPI
 SbiSetTimer (
-  IN  UINT64                         Time
+  IN  UINT64  Time
   )
 {
   SbiCall (SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, 1, Time);
@@ -394,17 +422,20 @@ SbiSetTimer (
 EFI_STATUS
 EFIAPI
 SbiSendIpi (
-  IN  UINTN                         *HartMask,
-  IN  UINTN                          HartMaskBase
+  IN  UINTN  *HartMask,
+  IN  UINTN  HartMaskBase
   )
 {
-  SbiRet Ret = SbiCall (
-                 SBI_EXT_IPI,
-                 SBI_EXT_IPI_SEND_IPI,
-                 2,
-                 (UINTN)HartMask,
-                 HartMaskBase
-                 );
+  SBI_RET  Ret;
+
+  Ret = SbiCall (
+          SBI_EXT_IPI,
+          SBI_EXT_IPI_SEND_IPI,
+          2,
+          (UINTN)HartMask,
+          HartMaskBase
+          );
+
   return TranslateError (Ret.Error);
 }
 
@@ -424,17 +455,20 @@ SbiSendIpi (
 EFI_STATUS
 EFIAPI
 SbiRemoteFenceI (
-  IN  UINTN                         *HartMask,
-  IN  UINTN                          HartMaskBase
+  IN  UINTN  *HartMask,
+  IN  UINTN  HartMaskBase
   )
 {
-  SbiRet Ret = SbiCall (
-                 SBI_EXT_RFENCE,
-                 SBI_EXT_RFENCE_REMOTE_FENCE_I,
-                 2,
-                 (UINTN)HartMask,
-                 HartMaskBase
-                 );
+  SBI_RET  Ret;
+
+  Ret = SbiCall (
+          SBI_EXT_RFENCE,
+          SBI_EXT_RFENCE_REMOTE_FENCE_I,
+          2,
+          (UINTN)HartMask,
+          HartMaskBase
+          );
+
   return TranslateError (Ret.Error);
 }
 
@@ -462,21 +496,24 @@ SbiRemoteFenceI (
 EFI_STATUS
 EFIAPI
 SbiRemoteSfenceVma (
-  IN  UINTN                         *HartMask,
-  IN  UINTN                          HartMaskBase,
-  IN  UINTN                          StartAddr,
-  IN  UINTN                          Size
+  IN  UINTN  *HartMask,
+  IN  UINTN  HartMaskBase,
+  IN  UINTN  StartAddr,
+  IN  UINTN  Size
   )
 {
-  SbiRet Ret = SbiCall (
-                 SBI_EXT_RFENCE,
-                 SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
-                 4,
-                 (UINTN)HartMask,
-                 HartMaskBase,
-                 StartAddr,
-                 Size
-                 );
+  SBI_RET  Ret;
+
+  Ret = SbiCall (
+          SBI_EXT_RFENCE,
+          SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
+          4,
+          (UINTN)HartMask,
+          HartMaskBase,
+          StartAddr,
+          Size
+          );
+
   return TranslateError (Ret.Error);
 }
 
@@ -505,23 +542,26 @@ SbiRemoteSfenceVma (
 EFI_STATUS
 EFIAPI
 SbiRemoteSfenceVmaAsid (
-  IN  UINTN                         *HartMask,
-  IN  UINTN                          HartMaskBase,
-  IN  UINTN                          StartAddr,
-  IN  UINTN                          Size,
-  IN  UINTN                          Asid
+  IN  UINTN  *HartMask,
+  IN  UINTN  HartMaskBase,
+  IN  UINTN  StartAddr,
+  IN  UINTN  Size,
+  IN  UINTN  Asid
   )
 {
-  SbiRet Ret = SbiCall (
-                 SBI_EXT_RFENCE,
-                 SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
-                 5,
-                 (UINTN)HartMask,
-                 HartMaskBase,
-                 StartAddr,
-                 Size,
-                 Asid
-                 );
+  SBI_RET  Ret;
+
+  Ret = SbiCall (
+          SBI_EXT_RFENCE,
+          SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
+          5,
+          (UINTN)HartMask,
+          HartMaskBase,
+          StartAddr,
+          Size,
+          Asid
+          );
+
   return TranslateError (Ret.Error);
 }
 
@@ -554,23 +594,26 @@ SbiRemoteSfenceVmaAsid (
 EFI_STATUS
 EFIAPI
 SbiRemoteHFenceGvmaVmid (
-  IN  UINTN                         *HartMask,
-  IN  UINTN                          HartMaskBase,
-  IN  UINTN                          StartAddr,
-  IN  UINTN                          Size,
-  IN  UINTN                          Vmid
+  IN  UINTN  *HartMask,
+  IN  UINTN  HartMaskBase,
+  IN  UINTN  StartAddr,
+  IN  UINTN  Size,
+  IN  UINTN  Vmid
   )
 {
-  SbiRet Ret = SbiCall (
-                 SBI_EXT_RFENCE,
-                 SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
-                 5,
-                 (UINTN)HartMask,
-                 HartMaskBase,
-                 StartAddr,
-                 Size,
-                 Vmid
-                 );
+  SBI_RET  Ret;
+
+  Ret = SbiCall (
+          SBI_EXT_RFENCE,
+          SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
+          5,
+          (UINTN)HartMask,
+          HartMaskBase,
+          StartAddr,
+          Size,
+          Vmid
+          );
+
   return TranslateError (Ret.Error);
 }
 
@@ -602,21 +645,24 @@ SbiRemoteHFenceGvmaVmid (
 EFI_STATUS
 EFIAPI
 SbiRemoteHFenceGvma (
-  IN  UINTN                         *HartMask,
-  IN  UINTN                          HartMaskBase,
-  IN  UINTN                          StartAddr,
-  IN  UINTN                          Size
+  IN  UINTN  *HartMask,
+  IN  UINTN  HartMaskBase,
+  IN  UINTN  StartAddr,
+  IN  UINTN  Size
   )
 {
-  SbiRet Ret = SbiCall (
-                 SBI_EXT_RFENCE,
-                 SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
-                 4,
-                 (UINTN)HartMask,
-                 HartMaskBase,
-                 StartAddr,
-                 Size
-                 );
+  SBI_RET  Ret;
+
+  Ret = SbiCall (
+          SBI_EXT_RFENCE,
+          SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
+          4,
+          (UINTN)HartMask,
+          HartMaskBase,
+          StartAddr,
+          Size
+          );
+
   return TranslateError (Ret.Error);
 }
 
@@ -649,23 +695,26 @@ SbiRemoteHFenceGvma (
 EFI_STATUS
 EFIAPI
 SbiRemoteHFenceVvmaAsid (
-  IN  UINTN                         *HartMask,
-  IN  UINTN                          HartMaskBase,
-  IN  UINTN                          StartAddr,
-  IN  UINTN                          Size,
-  IN  UINTN                          Asid
+  IN  UINTN  *HartMask,
+  IN  UINTN  HartMaskBase,
+  IN  UINTN  StartAddr,
+  IN  UINTN  Size,
+  IN  UINTN  Asid
   )
 {
-  SbiRet Ret = SbiCall (
-                 SBI_EXT_RFENCE,
-                 SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
-                 5,
-                 (UINTN)HartMask,
-                 HartMaskBase,
-                 StartAddr,
-                 Size,
-                 Asid
-                 );
+  SBI_RET  Ret;
+
+  Ret = SbiCall (
+          SBI_EXT_RFENCE,
+          SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
+          5,
+          (UINTN)HartMask,
+          HartMaskBase,
+          StartAddr,
+          Size,
+          Asid
+          );
+
   return TranslateError (Ret.Error);
 }
 
@@ -697,21 +746,24 @@ SbiRemoteHFenceVvmaAsid (
 EFI_STATUS
 EFIAPI
 SbiRemoteHFenceVvma (
-  IN  UINTN                         *HartMask,
-  IN  UINTN                          HartMaskBase,
-  IN  UINTN                          StartAddr,
-  IN  UINTN                          Size
+  IN  UINTN  *HartMask,
+  IN  UINTN  HartMaskBase,
+  IN  UINTN  StartAddr,
+  IN  UINTN  Size
   )
 {
-  SbiRet Ret = SbiCall (
-                 SBI_EXT_RFENCE,
-                 SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
-                 4,
-                 (UINTN)HartMask,
-                 HartMaskBase,
-                 StartAddr,
-                 Size
-                 );
+  SBI_RET  Ret;
+
+  Ret = SbiCall (
+          SBI_EXT_RFENCE,
+          SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
+          4,
+          (UINTN)HartMask,
+          HartMaskBase,
+          StartAddr,
+          Size
+          );
+
   return TranslateError (Ret.Error);
 }
 
@@ -743,17 +795,20 @@ SbiRemoteHFenceVvma (
 EFI_STATUS
 EFIAPI
 SbiSystemReset (
-  IN  UINTN                          ResetType,
-  IN  UINTN                          ResetReason
+  IN  UINTN  ResetType,
+  IN  UINTN  ResetReason
   )
 {
-  SbiRet Ret = SbiCall (
-                 SBI_EXT_SRST,
-                 SBI_EXT_SRST_RESET,
-                 2,
-                 ResetType,
-                 ResetReason
-                 );
+  SBI_RET  Ret;
+
+  Ret = SbiCall (
+          SBI_EXT_SRST,
+          SBI_EXT_SRST_RESET,
+          2,
+          ResetType,
+          ResetReason
+          );
+
   return TranslateError (Ret.Error);
 }
 
@@ -777,59 +832,91 @@ SbiSystemReset (
 EFI_STATUS
 EFIAPI
 SbiVendorCall (
-  IN  UINTN                          ExtensionId,
-  IN  UINTN                          FunctionId,
-  IN  UINTN                          NumArgs,
+  IN  UINTN  ExtensionId,
+  IN  UINTN  FunctionId,
+  IN  UINTN  NumArgs,
   ...
   )
 {
-    SbiRet Ret;
-    VA_LIST Args;
-    VA_START (Args, NumArgs);
-
-    ASSERT (ExtensionId >= SBI_EXT_VENDOR_START && ExtensionId <= SBI_EXT_VENDOR_END);
-    ASSERT (NumArgs <= SBI_CALL_MAX_ARGS);
-
-    switch (NumArgs) {
-      case 0:
-        Ret = SbiCall (ExtensionId, FunctionId, NumArgs);
-        break;
-      case 1:
-        Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN));
-        break;
-      case 2:
-        Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN),
-                       VA_ARG (Args, UINTN));
-        break;
-      case 3:
-        Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN),
-                       VA_ARG (Args, UINTN), VA_ARG (Args, UINTN));
-        break;
-      case 4:
-        Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN),
-                       VA_ARG (Args, UINTN), VA_ARG (Args, UINTN),
-                       VA_ARG (Args, UINTN));
-        break;
-      case 5:
-        Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN),
-                       VA_ARG (Args, UINTN), VA_ARG (Args, UINTN),
-                       VA_ARG (Args, UINTN), VA_ARG (Args, UINTN));
-        break;
-      case 6:
-        Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN),
-                       VA_ARG (Args, UINTN), VA_ARG (Args, UINTN),
-                       VA_ARG (Args, UINTN), VA_ARG (Args, UINTN),
-                       VA_ARG (Args, UINTN));
-        break;
-      default:
-        // Too many args. In theory SBI can handle more arguments when they are
-        // passed on the stack but no SBI extension uses this, therefore it's
-        // not yet implemented here.
-        return EFI_INVALID_PARAMETER;
-     }
-
-    VA_END(Args);
-    return TranslateError (Ret.Error);
+  SBI_RET  Ret;
+  VA_LIST  Args;
+
+  VA_START (Args, NumArgs);
+
+  ASSERT (ExtensionId >= SBI_EXT_VENDOR_START && ExtensionId <= SBI_EXT_VENDOR_END);
+  ASSERT (NumArgs <= SBI_CALL_MAX_ARGS);
+
+  switch (NumArgs) {
+    case 0:
+      Ret = SbiCall (ExtensionId, FunctionId, NumArgs);
+      break;
+    case 1:
+      Ret = SbiCall (ExtensionId, FunctionId, NumArgs, VA_ARG (Args, UINTN));
+      break;
+    case 2:
+      Ret = SbiCall (
+              ExtensionId,
+              FunctionId,
+              NumArgs,
+              VA_ARG (Args, UINTN),
+              VA_ARG (Args, UINTN)
+              );
+      break;
+    case 3:
+      Ret = SbiCall (
+              ExtensionId,
+              FunctionId,
+              NumArgs,
+              VA_ARG (Args, UINTN),
+              VA_ARG (Args, UINTN),
+              VA_ARG (Args, UINTN)
+              );
+      break;
+    case 4:
+      Ret = SbiCall (
+              ExtensionId,
+              FunctionId,
+              NumArgs,
+              VA_ARG (Args, UINTN),
+              VA_ARG (Args, UINTN),
+              VA_ARG (Args, UINTN),
+              VA_ARG (Args, UINTN)
+              );
+      break;
+    case 5:
+      Ret = SbiCall (
+              ExtensionId,
+              FunctionId,
+              NumArgs,
+              VA_ARG (Args, UINTN),
+              VA_ARG (Args, UINTN),
+              VA_ARG (Args, UINTN),
+              VA_ARG (Args, UINTN),
+              VA_ARG (Args, UINTN)
+              );
+      break;
+    case 6:
+      Ret = SbiCall (
+              ExtensionId,
+              FunctionId,
+              NumArgs,
+              VA_ARG (Args, UINTN),
+              VA_ARG (Args, UINTN),
+              VA_ARG (Args, UINTN),
+              VA_ARG (Args, UINTN),
+              VA_ARG (Args, UINTN),
+              VA_ARG (Args, UINTN)
+              );
+      break;
+    default:
+      // Too many args. In theory SBI can handle more arguments when they are
+      // passed on the stack but no SBI extension uses this, therefore it's
+      // not yet implemented here.
+      return EFI_INVALID_PARAMETER;
+  }
+
+  VA_END (Args);
+  return TranslateError (Ret.Error);
 }
 
 //
@@ -847,10 +934,12 @@ SbiVendorCall (
 VOID
 EFIAPI
 SbiGetMscratch (
-  OUT SBI_SCRATCH                    **ScratchSpace
+  OUT SBI_SCRATCH  **ScratchSpace
   )
 {
-  SbiRet Ret = SbiCall (SBI_EDK2_FW_EXT, SBI_EXT_FW_MSCRATCH_FUNC, 0);
+  SBI_RET  Ret;
+
+  Ret = SbiCall (SBI_EDK2_FW_EXT, SBI_EXT_FW_MSCRATCH_FUNC, 0);
 
   // Our ecall handler never returns an error, only when the func id is invalid
   ASSERT (Ret.Error == SBI_OK);
@@ -867,16 +956,18 @@ SbiGetMscratch (
 VOID
 EFIAPI
 SbiGetMscratchHartid (
-  IN  UINTN                            HartId,
-  OUT SBI_SCRATCH                    **ScratchSpace
+  IN  UINTN        HartId,
+  OUT SBI_SCRATCH  **ScratchSpace
   )
 {
-  SbiRet Ret = SbiCall (
-                 SBI_EDK2_FW_EXT,
-                 SBI_EXT_FW_MSCRATCH_HARTID_FUNC,
-                 1,
-                 HartId
-                 );
+  SBI_RET  Ret;
+
+  Ret = SbiCall (
+          SBI_EDK2_FW_EXT,
+          SBI_EXT_FW_MSCRATCH_HARTID_FUNC,
+          1,
+          HartId
+          );
 
   // Our ecall handler never returns an error, only when the func id is invalid
   ASSERT (Ret.Error == SBI_OK);
@@ -893,14 +984,14 @@ SbiGetMscratchHartid (
 VOID
 EFIAPI
 SbiGetFirmwareContext (
-  OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContext
+  OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT  **FirmwareContext
   )
 {
-  SBI_SCRATCH  *ScratchSpace;
-  SBI_PLATFORM *SbiPlatform;
+  SBI_SCRATCH   *ScratchSpace;
+  SBI_PLATFORM  *SbiPlatform;
 
-  SbiGetMscratch(&ScratchSpace);
-  SbiPlatform = (SBI_PLATFORM *)sbi_platform_ptr(ScratchSpace);
+  SbiGetMscratch (&ScratchSpace);
+  SbiPlatform      = (SBI_PLATFORM *)sbi_platform_ptr (ScratchSpace);
   *FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)SbiPlatform->firmware_context;
 }
 
@@ -912,14 +1003,14 @@ SbiGetFirmwareContext (
 VOID
 EFIAPI
 SbiSetFirmwareContext (
-  IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext
+  IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT  *FirmwareContext
   )
 {
-  SBI_SCRATCH  *ScratchSpace;
-  SBI_PLATFORM *SbiPlatform;
+  SBI_SCRATCH   *ScratchSpace;
+  SBI_PLATFORM  *SbiPlatform;
 
-  SbiGetMscratch(&ScratchSpace);
+  SbiGetMscratch (&ScratchSpace);
 
-  SbiPlatform = (SBI_PLATFORM *)sbi_platform_ptr (ScratchSpace);
+  SbiPlatform                   = (SBI_PLATFORM *)sbi_platform_ptr (ScratchSpace);
   SbiPlatform->firmware_context = (UINTN)FirmwareContext;
 }

+ 17 - 17
Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c

@@ -1,7 +1,7 @@
 /** @file
-  RISC-V Exception Handler library implementition.
+  RISC-V Exception Handler library implementation.
 
-  Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+  Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -17,7 +17,7 @@
 
 #include "CpuExceptionHandlerLib.h"
 
-STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2];
+STATIC EFI_CPU_INTERRUPT_HANDLER  mInterruptHandlers[2];
 
 /**
   Initializes all CPU exceptions entries and provides the default exception handlers.
@@ -38,7 +38,7 @@ STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2];
 EFI_STATUS
 EFIAPI
 InitializeCpuExceptionHandlers (
-  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL
+  IN EFI_VECTOR_HANDOFF_INFO  *VectorInfo OPTIONAL
   )
 {
   return EFI_SUCCESS;
@@ -63,7 +63,7 @@ InitializeCpuExceptionHandlers (
 EFI_STATUS
 EFIAPI
 InitializeCpuInterruptHandlers (
-  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL
+  IN EFI_VECTOR_HANDOFF_INFO  *VectorInfo OPTIONAL
   )
 {
   return EFI_SUCCESS;
@@ -95,15 +95,15 @@ InitializeCpuInterruptHandlers (
 EFI_STATUS
 EFIAPI
 RegisterCpuInterruptHandler (
-  IN EFI_EXCEPTION_TYPE            InterruptType,
-  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler
+  IN EFI_EXCEPTION_TYPE         InterruptType,
+  IN EFI_CPU_INTERRUPT_HANDLER  InterruptHandler
   )
 {
-
   DEBUG ((DEBUG_INFO, "%a: Type:%x Handler: %x\n", __FUNCTION__, InterruptType, InterruptHandler));
   mInterruptHandlers[InterruptType] = InterruptHandler;
   return EFI_SUCCESS;
 }
+
 /**
   Machine mode trap handler.
 
@@ -112,23 +112,23 @@ RegisterCpuInterruptHandler (
 **/
 VOID
 RiscVSupervisorModeTrapHandler (
-  SMODE_TRAP_REGISTERS *SmodeTrapReg
+  SMODE_TRAP_REGISTERS  *SmodeTrapReg
   )
 {
-  UINTN SCause;
-  EFI_SYSTEM_CONTEXT RiscVSystemContext;
+  UINTN               SCause;
+  EFI_SYSTEM_CONTEXT  RiscVSystemContext;
 
   RiscVSystemContext.SystemContextRiscV64 = (EFI_SYSTEM_CONTEXT_RISCV64 *)SmodeTrapReg;
   //
   // Check scasue register.
   //
-  SCause = (UINTN)csr_read(RISCV_CSR_SUPERVISOR_SCAUSE);
+  SCause = (UINTN)csr_read (RISCV_CSR_SUPERVISOR_SCAUSE);
   if ((SCause & (1UL << (sizeof (UINTN) * 8- 1))) != 0) {
     //
     // This is interrupt event.
     //
     SCause &= ~(1UL << (sizeof (UINTN) * 8- 1));
-    if((SCause == SCAUSE_SUPERVISOR_TIMER_INT) && (mInterruptHandlers[EXCEPT_RISCV_TIMER_INT] != NULL)) {
+    if ((SCause == SCAUSE_SUPERVISOR_TIMER_INT) && (mInterruptHandlers[EXCEPT_RISCV_TIMER_INT] != NULL)) {
       mInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, RiscVSystemContext);
     }
   }
@@ -160,8 +160,8 @@ RiscVSupervisorModeTrapHandler (
 EFI_STATUS
 EFIAPI
 InitializeCpuExceptionHandlersEx (
-  IN EFI_VECTOR_HANDOFF_INFO            *VectorInfo OPTIONAL,
-  IN CPU_EXCEPTION_INIT_DATA            *InitData OPTIONAL
+  IN EFI_VECTOR_HANDOFF_INFO  *VectorInfo OPTIONAL,
+  IN CPU_EXCEPTION_INIT_DATA  *InitData OPTIONAL
   )
 {
   return InitializeCpuExceptionHandlers (VectorInfo);
@@ -186,9 +186,9 @@ CpuExceptionHandlerLibConstructor (
   )
 {
   //
-  // Set Superviosr mode trap handler.
+  // Set Supervisor mode trap handler.
   //
-  csr_write(CSR_STVEC, SupervisorModeTrap);
+  csr_write (CSR_STVEC, SupervisorModeTrap);
 
   return EFI_SUCCESS;
 }

+ 86 - 83
Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h

@@ -2,7 +2,7 @@
 
   RISC-V Exception Handler library definition file.
 
-  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+  Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -11,96 +11,99 @@
 #ifndef RISCV_CPU_EXECPTION_HANDLER_LIB_H_
 #define RISCV_CPU_EXECPTION_HANDLER_LIB_H_
 
-extern void SupervisorModeTrap(void);
+extern void
+SupervisorModeTrap (
+  void
+  );
 
 //
 // Index of SMode trap register
 //
-#define SMODE_TRAP_REGS_zero          0
-#define SMODE_TRAP_REGS_ra            1
-#define SMODE_TRAP_REGS_sp            2
-#define SMODE_TRAP_REGS_gp            3
-#define SMODE_TRAP_REGS_tp            4
-#define SMODE_TRAP_REGS_t0            5
-#define SMODE_TRAP_REGS_t1            6
-#define SMODE_TRAP_REGS_t2            7
-#define SMODE_TRAP_REGS_s0            8
-#define SMODE_TRAP_REGS_s1            9
-#define SMODE_TRAP_REGS_a0            10
-#define SMODE_TRAP_REGS_a1            11
-#define SMODE_TRAP_REGS_a2            12
-#define SMODE_TRAP_REGS_a3            13
-#define SMODE_TRAP_REGS_a4            14
-#define SMODE_TRAP_REGS_a5            15
-#define SMODE_TRAP_REGS_a6            16
-#define SMODE_TRAP_REGS_a7            17
-#define SMODE_TRAP_REGS_s2            18
-#define SMODE_TRAP_REGS_s3            19
-#define SMODE_TRAP_REGS_s4            20
-#define SMODE_TRAP_REGS_s5            21
-#define SMODE_TRAP_REGS_s6            22
-#define SMODE_TRAP_REGS_s7            23
-#define SMODE_TRAP_REGS_s8            24
-#define SMODE_TRAP_REGS_s9            25
-#define SMODE_TRAP_REGS_s10           26
-#define SMODE_TRAP_REGS_s11           27
-#define SMODE_TRAP_REGS_t3            28
-#define SMODE_TRAP_REGS_t4            29
-#define SMODE_TRAP_REGS_t5            30
-#define SMODE_TRAP_REGS_t6            31
-#define SMODE_TRAP_REGS_sepc          32
-#define SMODE_TRAP_REGS_sstatus       33
-#define SMODE_TRAP_REGS_sie           34
-#define SMODE_TRAP_REGS_last          35
+#define SMODE_TRAP_REGS_zero     0
+#define SMODE_TRAP_REGS_ra       1
+#define SMODE_TRAP_REGS_sp       2
+#define SMODE_TRAP_REGS_gp       3
+#define SMODE_TRAP_REGS_tp       4
+#define SMODE_TRAP_REGS_t0       5
+#define SMODE_TRAP_REGS_t1       6
+#define SMODE_TRAP_REGS_t2       7
+#define SMODE_TRAP_REGS_s0       8
+#define SMODE_TRAP_REGS_s1       9
+#define SMODE_TRAP_REGS_a0       10
+#define SMODE_TRAP_REGS_a1       11
+#define SMODE_TRAP_REGS_a2       12
+#define SMODE_TRAP_REGS_a3       13
+#define SMODE_TRAP_REGS_a4       14
+#define SMODE_TRAP_REGS_a5       15
+#define SMODE_TRAP_REGS_a6       16
+#define SMODE_TRAP_REGS_a7       17
+#define SMODE_TRAP_REGS_s2       18
+#define SMODE_TRAP_REGS_s3       19
+#define SMODE_TRAP_REGS_s4       20
+#define SMODE_TRAP_REGS_s5       21
+#define SMODE_TRAP_REGS_s6       22
+#define SMODE_TRAP_REGS_s7       23
+#define SMODE_TRAP_REGS_s8       24
+#define SMODE_TRAP_REGS_s9       25
+#define SMODE_TRAP_REGS_s10      26
+#define SMODE_TRAP_REGS_s11      27
+#define SMODE_TRAP_REGS_t3       28
+#define SMODE_TRAP_REGS_t4       29
+#define SMODE_TRAP_REGS_t5       30
+#define SMODE_TRAP_REGS_t6       31
+#define SMODE_TRAP_REGS_sepc     32
+#define SMODE_TRAP_REGS_sstatus  33
+#define SMODE_TRAP_REGS_sie      34
+#define SMODE_TRAP_REGS_last     35
 
-#define SMODE_TRAP_REGS_OFFSET(x) ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINTER__)
-#define SMODE_TRAP_REGS_SIZE SMODE_TRAP_REGS_OFFSET(last)
+#define SMODE_TRAP_REGS_OFFSET(x)  ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINTER__)
+#define SMODE_TRAP_REGS_SIZE  SMODE_TRAP_REGS_OFFSET(last)
 
 #pragma pack(1)
 typedef struct {
-//
-// Below are follow the format of EFI_SYSTEM_CONTEXT
-//
-    RISC_V_REGS_PROTOTYPE zero;
-    RISC_V_REGS_PROTOTYPE ra;
-    RISC_V_REGS_PROTOTYPE sp;
-    RISC_V_REGS_PROTOTYPE gp;
-    RISC_V_REGS_PROTOTYPE tp;
-    RISC_V_REGS_PROTOTYPE t0;
-    RISC_V_REGS_PROTOTYPE t1;
-    RISC_V_REGS_PROTOTYPE t2;
-    RISC_V_REGS_PROTOTYPE s0;
-    RISC_V_REGS_PROTOTYPE s1;
-    RISC_V_REGS_PROTOTYPE a0;
-    RISC_V_REGS_PROTOTYPE a1;
-    RISC_V_REGS_PROTOTYPE a2;
-    RISC_V_REGS_PROTOTYPE a3;
-    RISC_V_REGS_PROTOTYPE a4;
-    RISC_V_REGS_PROTOTYPE a5;
-    RISC_V_REGS_PROTOTYPE a6;
-    RISC_V_REGS_PROTOTYPE a7;
-    RISC_V_REGS_PROTOTYPE s2;
-    RISC_V_REGS_PROTOTYPE s3;
-    RISC_V_REGS_PROTOTYPE s4;
-    RISC_V_REGS_PROTOTYPE s5;
-    RISC_V_REGS_PROTOTYPE s6;
-    RISC_V_REGS_PROTOTYPE s7;
-    RISC_V_REGS_PROTOTYPE s8;
-    RISC_V_REGS_PROTOTYPE s9;
-    RISC_V_REGS_PROTOTYPE s10;
-    RISC_V_REGS_PROTOTYPE s11;
-    RISC_V_REGS_PROTOTYPE t3;
-    RISC_V_REGS_PROTOTYPE t4;
-    RISC_V_REGS_PROTOTYPE t5;
-    RISC_V_REGS_PROTOTYPE t6;
-//
-// Below are the additional information to
-// EFI_SYSTEM_CONTEXT, private to supervisor mode trap
-// and not public to EFI environment.
-//
-    RISC_V_REGS_PROTOTYPE sepc;
-    RISC_V_REGS_PROTOTYPE sstatus;
-    RISC_V_REGS_PROTOTYPE sie;
+  //
+  // Below are follow the format of EFI_SYSTEM_CONTEXT
+  //
+  RISC_V_REGS_PROTOTYPE    zero;
+  RISC_V_REGS_PROTOTYPE    ra;
+  RISC_V_REGS_PROTOTYPE    sp;
+  RISC_V_REGS_PROTOTYPE    gp;
+  RISC_V_REGS_PROTOTYPE    tp;
+  RISC_V_REGS_PROTOTYPE    t0;
+  RISC_V_REGS_PROTOTYPE    t1;
+  RISC_V_REGS_PROTOTYPE    t2;
+  RISC_V_REGS_PROTOTYPE    s0;
+  RISC_V_REGS_PROTOTYPE    s1;
+  RISC_V_REGS_PROTOTYPE    a0;
+  RISC_V_REGS_PROTOTYPE    a1;
+  RISC_V_REGS_PROTOTYPE    a2;
+  RISC_V_REGS_PROTOTYPE    a3;
+  RISC_V_REGS_PROTOTYPE    a4;
+  RISC_V_REGS_PROTOTYPE    a5;
+  RISC_V_REGS_PROTOTYPE    a6;
+  RISC_V_REGS_PROTOTYPE    a7;
+  RISC_V_REGS_PROTOTYPE    s2;
+  RISC_V_REGS_PROTOTYPE    s3;
+  RISC_V_REGS_PROTOTYPE    s4;
+  RISC_V_REGS_PROTOTYPE    s5;
+  RISC_V_REGS_PROTOTYPE    s6;
+  RISC_V_REGS_PROTOTYPE    s7;
+  RISC_V_REGS_PROTOTYPE    s8;
+  RISC_V_REGS_PROTOTYPE    s9;
+  RISC_V_REGS_PROTOTYPE    s10;
+  RISC_V_REGS_PROTOTYPE    s11;
+  RISC_V_REGS_PROTOTYPE    t3;
+  RISC_V_REGS_PROTOTYPE    t4;
+  RISC_V_REGS_PROTOTYPE    t5;
+  RISC_V_REGS_PROTOTYPE    t6;
+  //
+  // Below are the additional information to
+  // EFI_SYSTEM_CONTEXT, private to supervisor mode trap
+  // and not public to EFI environment.
+  //
+  RISC_V_REGS_PROTOTYPE    sepc;
+  RISC_V_REGS_PROTOTYPE    sstatus;
+  RISC_V_REGS_PROTOTYPE    sie;
 } SMODE_TRAP_REGISTERS;
 #pragma pack()
 

+ 3 - 3
Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c

@@ -2,7 +2,7 @@
   This instance uses Supervisor mode SCRATCH CSR to get/set the
   pointer of firmware context.
 
-  Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+  Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -25,7 +25,7 @@
 VOID
 EFIAPI
 GetFirmwareContextPointer (
-  IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+  IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT  **FirmwareContextPtr
   )
 {
   *FirmwareContextPtr = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)RiscVGetSupervisorScratch ();
@@ -41,7 +41,7 @@ GetFirmwareContextPointer (
 VOID
 EFIAPI
 SetFirmwareContextPointer (
-  IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+  IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT  *FirmwareContextPtr
   )
 {
   RiscVSetSupervisorScratch ((UINT64)FirmwareContextPtr);

+ 2 - 2
Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c

@@ -25,7 +25,7 @@
 VOID
 EFIAPI
 GetFirmwareContextPointer (
-  IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+  IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT  **FirmwareContextPtr
   )
 {
   *FirmwareContextPtr = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)RiscVGetSupervisorStvec ();
@@ -41,7 +41,7 @@ GetFirmwareContextPointer (
 VOID
 EFIAPI
 SetFirmwareContextPointer (
-  IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+  IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT  *FirmwareContextPtr
   )
 {
   RiscVSetSupervisorStvec ((UINT64)FirmwareContextPtr);

+ 12 - 12
Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c

@@ -1,7 +1,7 @@
 /** @file
   RISC-V instance of Timer Library.
 
-  Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+  Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -24,21 +24,21 @@
 **/
 VOID
 InternalRiscVTimerDelay (
-  IN UINT32 Delay
+  IN UINT32  Delay
   )
 {
-  UINT32                            Ticks;
-  UINT32                            Times;
+  UINT32  Ticks;
+  UINT32  Times;
 
-  Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
-  Delay &= (( 1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
+  Times  = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
+  Delay &= ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
   do {
     //
     // The target timer count is calculated here
     //
     Ticks = RiscVReadMachineTimerInterface () + Delay;
     Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
-    while (((Ticks - RiscVReadMachineTimerInterface ()) & ( 1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
+    while (((Ticks - RiscVReadMachineTimerInterface ()) & (1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
       CpuPause ();
     }
   } while (Times-- > 0);
@@ -57,7 +57,7 @@ InternalRiscVTimerDelay (
 UINTN
 EFIAPI
 MicroSecondDelay (
-  IN UINTN MicroSeconds
+  IN UINTN  MicroSeconds
   )
 {
   InternalRiscVTimerDelay (
@@ -85,7 +85,7 @@ MicroSecondDelay (
 UINTN
 EFIAPI
 NanoSecondDelay (
-  IN UINTN NanoSeconds
+  IN UINTN  NanoSeconds
   )
 {
   InternalRiscVTimerDelay (
@@ -147,7 +147,7 @@ GetPerformanceCounter (
 UINT64
 EFIAPI
 GetPerformanceCounterProperties (
-  OUT      UINT64                    *StartValue,  OPTIONAL
+  OUT      UINT64 *StartValue, OPTIONAL
   OUT      UINT64                    *EndValue     OPTIONAL
   )
 {
@@ -176,7 +176,7 @@ GetPerformanceCounterProperties (
 UINT64
 EFIAPI
 GetTimeInNanoSecond (
-  IN      UINT64                     Ticks
+  IN      UINT64  Ticks
   )
 {
   UINT64  NanoSeconds;
@@ -193,7 +193,7 @@ GetTimeInNanoSecond (
   // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder * 1,000,000,000)
   // will not overflow 64-bit.
   //
-  NanoSeconds += DivU64x32 (MultU64x32 ((UINT64) Remainder, 1000000000u), PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz));
+  NanoSeconds += DivU64x32 (MultU64x32 ((UINT64)Remainder, 1000000000u), PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz));
 
   return NanoSeconds;
 }

+ 33 - 39
Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c

@@ -1,7 +1,7 @@
 /** @file
   RISC-V CPU DXE driver.
 
-  Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+  Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -12,8 +12,8 @@
 //
 // Global Variables
 //
-STATIC BOOLEAN mInterruptState = FALSE;
-STATIC EFI_HANDLE mCpuHandle = NULL;
+STATIC BOOLEAN     mInterruptState = FALSE;
+STATIC EFI_HANDLE  mCpuHandle      = NULL;
 
 EFI_CPU_ARCH_PROTOCOL  gCpu = {
   CpuFlushCpuDataCache,
@@ -50,16 +50,15 @@ EFI_CPU_ARCH_PROTOCOL  gCpu = {
 EFI_STATUS
 EFIAPI
 CpuFlushCpuDataCache (
-  IN EFI_CPU_ARCH_PROTOCOL     *This,
-  IN EFI_PHYSICAL_ADDRESS      Start,
-  IN UINT64                    Length,
-  IN EFI_CPU_FLUSH_TYPE        FlushType
+  IN EFI_CPU_ARCH_PROTOCOL  *This,
+  IN EFI_PHYSICAL_ADDRESS   Start,
+  IN UINT64                 Length,
+  IN EFI_CPU_FLUSH_TYPE     FlushType
   )
 {
   return EFI_SUCCESS;
 }
 
-
 /**
   Enables CPU interrupts.
 
@@ -72,7 +71,7 @@ CpuFlushCpuDataCache (
 EFI_STATUS
 EFIAPI
 CpuEnableInterrupt (
-  IN EFI_CPU_ARCH_PROTOCOL          *This
+  IN EFI_CPU_ARCH_PROTOCOL  *This
   )
 {
   EnableInterrupts ();
@@ -80,7 +79,6 @@ CpuEnableInterrupt (
   return EFI_SUCCESS;
 }
 
-
 /**
   Disables CPU interrupts.
 
@@ -93,7 +91,7 @@ CpuEnableInterrupt (
 EFI_STATUS
 EFIAPI
 CpuDisableInterrupt (
-  IN EFI_CPU_ARCH_PROTOCOL     *This
+  IN EFI_CPU_ARCH_PROTOCOL  *This
   )
 {
   DisableInterrupts ();
@@ -101,7 +99,6 @@ CpuDisableInterrupt (
   return EFI_SUCCESS;
 }
 
-
 /**
   Return the state of interrupts.
 
@@ -115,8 +112,8 @@ CpuDisableInterrupt (
 EFI_STATUS
 EFIAPI
 CpuGetInterruptState (
-  IN  EFI_CPU_ARCH_PROTOCOL     *This,
-  OUT BOOLEAN                   *State
+  IN  EFI_CPU_ARCH_PROTOCOL  *This,
+  OUT BOOLEAN                *State
   )
 {
   if (State == NULL) {
@@ -127,7 +124,6 @@ CpuGetInterruptState (
   return EFI_SUCCESS;
 }
 
-
 /**
   Generates an INIT to the CPU.
 
@@ -143,14 +139,13 @@ CpuGetInterruptState (
 EFI_STATUS
 EFIAPI
 CpuInit (
-  IN EFI_CPU_ARCH_PROTOCOL      *This,
-  IN EFI_CPU_INIT_TYPE          InitType
+  IN EFI_CPU_ARCH_PROTOCOL  *This,
+  IN EFI_CPU_INIT_TYPE      InitType
   )
 {
   return EFI_UNSUPPORTED;
 }
 
-
 /**
   Registers a function to be called from the CPU interrupt handler.
 
@@ -174,15 +169,14 @@ CpuInit (
 EFI_STATUS
 EFIAPI
 CpuRegisterInterruptHandler (
-  IN EFI_CPU_ARCH_PROTOCOL         *This,
-  IN EFI_EXCEPTION_TYPE            InterruptType,
-  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler
+  IN EFI_CPU_ARCH_PROTOCOL      *This,
+  IN EFI_EXCEPTION_TYPE         InterruptType,
+  IN EFI_CPU_INTERRUPT_HANDLER  InterruptHandler
   )
 {
   return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
 }
 
-
 /**
   Returns a timer value from one of the CPU's internal timers. There is no
   inherent time interval between ticks but is a function of the CPU frequency.
@@ -209,10 +203,10 @@ CpuRegisterInterruptHandler (
 EFI_STATUS
 EFIAPI
 CpuGetTimerValue (
-  IN  EFI_CPU_ARCH_PROTOCOL     *This,
-  IN  UINT32                    TimerIndex,
-  OUT UINT64                    *TimerValue,
-  OUT UINT64                    *TimerPeriod OPTIONAL
+  IN  EFI_CPU_ARCH_PROTOCOL  *This,
+  IN  UINT32                 TimerIndex,
+  OUT UINT64                 *TimerValue,
+  OUT UINT64                 *TimerPeriod OPTIONAL
   )
 {
   if (TimerValue == NULL) {
@@ -225,15 +219,15 @@ CpuGetTimerValue (
 
   *TimerValue = (UINT64)RiscVReadMachineTimerInterface ();
   if (TimerPeriod != NULL) {
-    *TimerPeriod  = DivU64x32 (
-                      1000000000000000u,
-                      PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
-                      );
+    *TimerPeriod = DivU64x32 (
+                     1000000000000000u,
+                     PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
+                     );
   }
+
   return EFI_SUCCESS;
 }
 
-
 /**
   Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.
 
@@ -262,10 +256,10 @@ CpuGetTimerValue (
 EFI_STATUS
 EFIAPI
 CpuSetMemoryAttributes (
-  IN EFI_CPU_ARCH_PROTOCOL     *This,
-  IN EFI_PHYSICAL_ADDRESS      BaseAddress,
-  IN UINT64                    Length,
-  IN UINT64                    Attributes
+  IN EFI_CPU_ARCH_PROTOCOL  *This,
+  IN EFI_PHYSICAL_ADDRESS   BaseAddress,
+  IN UINT64                 Length,
+  IN UINT64                 Attributes
   )
 {
   DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __FUNCTION__));
@@ -286,8 +280,8 @@ CpuSetMemoryAttributes (
 EFI_STATUS
 EFIAPI
 InitializeCpu (
-  IN EFI_HANDLE                            ImageHandle,
-  IN EFI_SYSTEM_TABLE                      *SystemTable
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
   EFI_STATUS  Status;
@@ -307,10 +301,10 @@ InitializeCpu (
   //
   Status = gBS->InstallMultipleProtocolInterfaces (
                   &mCpuHandle,
-                  &gEfiCpuArchProtocolGuid, &gCpu,
+                  &gEfiCpuArchProtocolGuid,
+                  &gCpu,
                   NULL
                   );
   ASSERT_EFI_ERROR (Status);
   return Status;
 }
-

+ 22 - 23
Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.h

@@ -1,7 +1,7 @@
 /** @file
   RISC-V CPU DXE module header file.
 
-  Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+  Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -38,10 +38,10 @@
 EFI_STATUS
 EFIAPI
 CpuFlushCpuDataCache (
-  IN EFI_CPU_ARCH_PROTOCOL     *This,
-  IN EFI_PHYSICAL_ADDRESS      Start,
-  IN UINT64                    Length,
-  IN EFI_CPU_FLUSH_TYPE        FlushType
+  IN EFI_CPU_ARCH_PROTOCOL  *This,
+  IN EFI_PHYSICAL_ADDRESS   Start,
+  IN UINT64                 Length,
+  IN EFI_CPU_FLUSH_TYPE     FlushType
   );
 
 /**
@@ -56,7 +56,7 @@ CpuFlushCpuDataCache (
 EFI_STATUS
 EFIAPI
 CpuEnableInterrupt (
-  IN EFI_CPU_ARCH_PROTOCOL     *This
+  IN EFI_CPU_ARCH_PROTOCOL  *This
   );
 
 /**
@@ -71,7 +71,7 @@ CpuEnableInterrupt (
 EFI_STATUS
 EFIAPI
 CpuDisableInterrupt (
-  IN EFI_CPU_ARCH_PROTOCOL     *This
+  IN EFI_CPU_ARCH_PROTOCOL  *This
   );
 
 /**
@@ -87,8 +87,8 @@ CpuDisableInterrupt (
 EFI_STATUS
 EFIAPI
 CpuGetInterruptState (
-  IN  EFI_CPU_ARCH_PROTOCOL     *This,
-  OUT BOOLEAN                   *State
+  IN  EFI_CPU_ARCH_PROTOCOL  *This,
+  OUT BOOLEAN                *State
   );
 
 /**
@@ -106,8 +106,8 @@ CpuGetInterruptState (
 EFI_STATUS
 EFIAPI
 CpuInit (
-  IN EFI_CPU_ARCH_PROTOCOL     *This,
-  IN EFI_CPU_INIT_TYPE         InitType
+  IN EFI_CPU_ARCH_PROTOCOL  *This,
+  IN EFI_CPU_INIT_TYPE      InitType
   );
 
 /**
@@ -133,9 +133,9 @@ CpuInit (
 EFI_STATUS
 EFIAPI
 CpuRegisterInterruptHandler (
-  IN EFI_CPU_ARCH_PROTOCOL         *This,
-  IN EFI_EXCEPTION_TYPE            InterruptType,
-  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler
+  IN EFI_CPU_ARCH_PROTOCOL      *This,
+  IN EFI_EXCEPTION_TYPE         InterruptType,
+  IN EFI_CPU_INTERRUPT_HANDLER  InterruptHandler
   );
 
 /**
@@ -164,10 +164,10 @@ CpuRegisterInterruptHandler (
 EFI_STATUS
 EFIAPI
 CpuGetTimerValue (
-  IN  EFI_CPU_ARCH_PROTOCOL       *This,
-  IN  UINT32                      TimerIndex,
-  OUT UINT64                      *TimerValue,
-  OUT UINT64                      *TimerPeriod OPTIONAL
+  IN  EFI_CPU_ARCH_PROTOCOL  *This,
+  IN  UINT32                 TimerIndex,
+  OUT UINT64                 *TimerValue,
+  OUT UINT64                 *TimerPeriod OPTIONAL
   );
 
 /**
@@ -189,11 +189,10 @@ CpuGetTimerValue (
 EFI_STATUS
 EFIAPI
 CpuSetMemoryAttributes (
-  IN EFI_CPU_ARCH_PROTOCOL      *This,
-  IN EFI_PHYSICAL_ADDRESS       BaseAddress,
-  IN UINT64                     Length,
-  IN UINT64                     Attributes
+  IN EFI_CPU_ARCH_PROTOCOL  *This,
+  IN EFI_PHYSICAL_ADDRESS   BaseAddress,
+  IN UINT64                 Length,
+  IN UINT64                 Attributes
   );
 
 #endif
-

+ 42 - 24
Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.c

@@ -6,7 +6,7 @@
   it runs in S-Mode, it cannot get this information from mhartid. Instead we
   insert the id into the device tree, that the EFIFSTUB can read from the config table.
 
-  Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+  Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -21,7 +21,8 @@
 /**
   Fix up the device tree with booting hartid for the kernel
 
-  @param DtbBlob The device tree. Is extended to fit the hart id.
+  @param  DtbBlob The device tree. Is extended to fit the hart id.
+  @param  BootingHartId The boot hart ID.
 
   @retval EFI_SUCCESS           The device tree was success fixed up with the hart id.
   @retval EFI_OUT_OF_RESOURCES  There is not enough memory available to complete the operation.
@@ -29,25 +30,32 @@
 EFI_STATUS
 EFIAPI
 FixDtb (
-  IN OUT VOID  *DtbBlob,
+  IN OUT VOID   *DtbBlob,
   IN     UINTN  BootingHartId
   )
 {
-  fdt32_t Size;
-  UINT32 ChosenOffset, Err;
+  fdt32_t  Size;
+  UINT32   ChosenOffset, Err;
 
-  DEBUG ((DEBUG_INFO, "Fixing up device tree with boot hart id: %d\n",
-    BootingHartId));
+  DEBUG ((
+    DEBUG_INFO,
+    "Fixing up device tree with boot hart id: %d\n",
+    BootingHartId
+    ));
 
-  Size = fdt_totalsize(DtbBlob);
-  Err  = fdt_open_into(DtbBlob, DtbBlob, Size + 32);
+  Size = fdt_totalsize (DtbBlob);
+  Err  = fdt_open_into (DtbBlob, DtbBlob, Size + 32);
   if (Err < 0) {
-    DEBUG ((DEBUG_ERROR,
-      "Device Tree can't be expanded to accommodate new node\n", __FUNCTION__));
+    DEBUG ((
+      DEBUG_ERROR,
+      "Device Tree can't be expanded to accommodate new node\n",
+      __FUNCTION__
+      ));
     return EFI_OUT_OF_RESOURCES;
   }
-  ChosenOffset = fdt_path_offset(DtbBlob, "/chosen");
-  fdt_setprop_u32(DtbBlob, ChosenOffset, "boot-hartid", BootingHartId);
+
+  ChosenOffset = fdt_path_offset (DtbBlob, "/chosen");
+  fdt_setprop_u32 (DtbBlob, ChosenOffset, "boot-hartid", BootingHartId);
 
   return EFI_SUCCESS;
 }
@@ -61,32 +69,42 @@ FixDtb (
 **/
 EFI_STATUS
 EFIAPI
-InstallFdtFromHob (VOID)
+InstallFdtFromHob (
+  VOID
+  )
 {
   EFI_STATUS         Status;
-  EFI_HOB_GUID_TYPE *GuidHob;
-  VOID              *DataInHob;
+  EFI_HOB_GUID_TYPE  *GuidHob;
+  VOID               *DataInHob;
   UINTN              DataSize;
 
   GuidHob = GetFirstGuidHob (&gFdtHobGuid);
   if (GuidHob == NULL) {
-    DEBUG ((DEBUG_ERROR, "Failed to find RISC-V DTB Hob\n",
-      __FUNCTION__));
+    DEBUG ((
+      DEBUG_ERROR,
+      "Failed to find RISC-V DTB Hob\n",
+      __FUNCTION__
+      ));
     return EFI_NOT_FOUND;
   }
-  DataInHob = (VOID *) *((UINTN *) GET_GUID_HOB_DATA (GuidHob));
+
+  DataInHob = (VOID *)*((UINTN *)GET_GUID_HOB_DATA (GuidHob));
   DataSize  = GET_GUID_HOB_DATA_SIZE (GuidHob);
 
-  Status = FixDtb (DataInHob, PcdGet32(PcdBootHartId));
+  Status = FixDtb (DataInHob, PcdGet32 (PcdBootHartId));
   if (EFI_ERROR (Status)) {
     return Status;
   }
 
   Status = gBS->InstallConfigurationTable (&gFdtTableGuid, DataInHob);
   if (EFI_ERROR (Status)) {
-    DEBUG ((DEBUG_ERROR, "%a: failed to install FDT configuration table\n",
-      __FUNCTION__));
+    DEBUG ((
+      DEBUG_ERROR,
+      "%a: failed to install FDT configuration table\n",
+      __FUNCTION__
+      ));
   }
+
   return Status;
 }
 
@@ -104,8 +122,8 @@ InstallFdtFromHob (VOID)
 EFI_STATUS
 EFIAPI
 InstallFdt (
-  IN EFI_HANDLE                            ImageHandle,
-  IN EFI_SYSTEM_TABLE                      *SystemTable
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
   EFI_STATUS  Status;

+ 25 - 22
Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c

@@ -3,7 +3,7 @@
 
 Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
 Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
-(C) Copyright 2021 Hewlett Packard Enterprise Development LP<BR>
+(C) Copyright 2021-2022 Hewlett Packard Enterprise Development LP<BR>
 
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -19,7 +19,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Library/PcdLib.h>
 #include <Library/UefiBootServicesTableLib.h>
 
-#define MAX_IO_PORT_ADDRESS   0xFFFF
+#define MAX_IO_PORT_ADDRESS  0xFFFF
 
 //
 // Handle for the CPU I/O 2 Protocol
@@ -29,7 +29,7 @@ STATIC EFI_HANDLE  mHandle = NULL;
 //
 // Lookup table for increment values based on transfer widths
 //
-STATIC CONST UINT8 mInStride[] = {
+STATIC CONST UINT8  mInStride[] = {
   1, // EfiCpuIoWidthUint8
   2, // EfiCpuIoWidthUint16
   4, // EfiCpuIoWidthUint32
@@ -47,7 +47,7 @@ STATIC CONST UINT8 mInStride[] = {
 //
 // Lookup table for increment values based on transfer widths
 //
-STATIC CONST UINT8 mOutStride[] = {
+STATIC CONST UINT8  mOutStride[] = {
   1, // EfiCpuIoWidthUint8
   2, // EfiCpuIoWidthUint16
   4, // EfiCpuIoWidthUint32
@@ -118,14 +118,14 @@ CpuIoCheckParameter (
   // For FIFO type, the target address won't increase during the access,
   // so treat Count as 1
   //
-  if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
+  if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64)) {
     Count = 1;
   }
 
   //
   // Check to see if Width is in the valid range for I/O Port operations
   //
-  Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+  Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
   if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
     return EFI_INVALID_PARAMETER;
   }
@@ -162,6 +162,7 @@ CpuIoCheckParameter (
     if (MaxCount < (Count - 1)) {
       return EFI_UNSUPPORTED;
     }
+
     if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
       return EFI_UNSUPPORTED;
     }
@@ -241,9 +242,9 @@ CpuMemoryServiceRead (
   //
   // Select loop based on the width of the transfer
   //
-  InStride = mInStride[Width];
-  OutStride = mOutStride[Width];
-  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+  InStride       = mInStride[Width];
+  OutStride      = mOutStride[Width];
+  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
   for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
     if (OperationWidth == EfiCpuIoWidthUint8) {
       *Uint8Buffer = MmioRead8 ((UINTN)Address);
@@ -255,6 +256,7 @@ CpuMemoryServiceRead (
       *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
     }
   }
+
   return EFI_SUCCESS;
 }
 
@@ -322,9 +324,9 @@ CpuMemoryServiceWrite (
   //
   // Select loop based on the width of the transfer
   //
-  InStride = mInStride[Width];
-  OutStride = mOutStride[Width];
-  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+  InStride       = mInStride[Width];
+  OutStride      = mOutStride[Width];
+  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
   for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
     if (OperationWidth == EfiCpuIoWidthUint8) {
       MmioWrite8 ((UINTN)Address, *Uint8Buffer);
@@ -336,6 +338,7 @@ CpuMemoryServiceWrite (
       MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
     }
   }
+
   return EFI_SUCCESS;
 }
 
@@ -405,9 +408,9 @@ CpuIoServiceRead (
   //
   // Select loop based on the width of the transfer
   //
-  InStride = mInStride[Width];
-  OutStride = mOutStride[Width];
-  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+  InStride       = mInStride[Width];
+  OutStride      = mOutStride[Width];
+  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
 
   for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
     if (OperationWidth == EfiCpuIoWidthUint8) {
@@ -491,9 +494,9 @@ CpuIoServiceWrite (
   //
   // Select loop based on the width of the transfer
   //
-  InStride = mInStride[Width];
-  OutStride = mOutStride[Width];
-  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+  InStride       = mInStride[Width];
+  OutStride      = mOutStride[Width];
+  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
 
   for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
     if (OperationWidth == EfiCpuIoWidthUint8) {
@@ -511,7 +514,7 @@ CpuIoServiceWrite (
 //
 // CPU I/O 2 Protocol instance
 //
-STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
+STATIC EFI_CPU_IO2_PROTOCOL  mCpuIo2 = {
   {
     CpuMemoryServiceRead,
     CpuMemoryServiceWrite
@@ -522,7 +525,6 @@ STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
   }
 };
 
-
 /**
   The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
 
@@ -540,12 +542,13 @@ PciCpuIo2Initialize (
   IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS Status;
+  EFI_STATUS  Status;
 
   ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
   Status = gBS->InstallMultipleProtocolInterfaces (
                   &mHandle,
-                  &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
+                  &gEfiCpuIo2ProtocolGuid,
+                  &mCpuIo2,
                   NULL
                   );
   ASSERT_EFI_ERROR (Status);

+ 88 - 65
Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c

@@ -9,7 +9,7 @@
 
 #include "RiscVSmbiosDxe.h"
 
-STATIC EFI_SMBIOS_PROTOCOL   *mSmbios;
+STATIC EFI_SMBIOS_PROTOCOL  *mSmbios;
 
 /**
   This function builds SMBIOS type 7 record according to
@@ -25,28 +25,31 @@ STATIC EFI_SMBIOS_PROTOCOL   *mSmbios;
 STATIC
 EFI_STATUS
 BuildSmbiosType7 (
- IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,
- IN RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7DataHob,
- OUT SMBIOS_HANDLE *SmbiosHandle
-)
+  IN RISC_V_PROCESSOR_TYPE4_HOB_DATA  *Type4HobData,
+  IN RISC_V_PROCESSOR_TYPE7_HOB_DATA  *Type7DataHob,
+  OUT SMBIOS_HANDLE                   *SmbiosHandle
+  )
 {
-  EFI_STATUS Status;
-  SMBIOS_HANDLE Handle;
+  EFI_STATUS     Status;
+  SMBIOS_HANDLE  Handle;
 
   if (!CompareGuid (&Type4HobData->ProcessorGuid, &Type7DataHob->ProcessorGuid) ||
-    Type4HobData->ProcessorUid != Type7DataHob->ProcessorUid) {
+      (Type4HobData->ProcessorUid != Type7DataHob->ProcessorUid))
+  {
     return EFI_INVALID_PARAMETER;
   }
-  Handle = SMBIOS_HANDLE_PI_RESERVED;
-  Type7DataHob->SmbiosType7Cache.Hdr.Type = SMBIOS_TYPE_CACHE_INFORMATION;
-  Type7DataHob->SmbiosType7Cache.Hdr.Length = sizeof(SMBIOS_TABLE_TYPE7);
+
+  Handle                                    = SMBIOS_HANDLE_PI_RESERVED;
+  Type7DataHob->SmbiosType7Cache.Hdr.Type   = SMBIOS_TYPE_CACHE_INFORMATION;
+  Type7DataHob->SmbiosType7Cache.Hdr.Length = sizeof (SMBIOS_TABLE_TYPE7);
   Type7DataHob->SmbiosType7Cache.Hdr.Handle = 0;
-  Type7DataHob->EndingZero = 0;
-  Status = mSmbios->Add (mSmbios, NULL, &Handle, &Type7DataHob->SmbiosType7Cache.Hdr);
-  if (EFI_ERROR(Status)) {
+  Type7DataHob->EndingZero                  = 0;
+  Status                                    = mSmbios->Add (mSmbios, NULL, &Handle, &Type7DataHob->SmbiosType7Cache.Hdr);
+  if (EFI_ERROR (Status)) {
     DEBUG ((DEBUG_ERROR, "%a: Fail to add SMBIOS Type 7\n", __FUNCTION__));
     return Status;
   }
+
   DEBUG ((DEBUG_INFO, "SMBIOS Type 7 was added. SMBIOS Handle: 0x%x\n", Handle));
   DEBUG ((DEBUG_VERBOSE, "     Cache belone to processor GUID: %g\n", &Type7DataHob->ProcessorGuid));
   DEBUG ((DEBUG_VERBOSE, "     Cache belone processor  UID: %d\n", Type7DataHob->ProcessorUid));
@@ -79,15 +82,15 @@ BuildSmbiosType7 (
 STATIC
 EFI_STATUS
 BuildSmbiosType4 (
-  IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,
-  OUT SMBIOS_HANDLE *SmbiosHandle
+  IN RISC_V_PROCESSOR_TYPE4_HOB_DATA  *Type4HobData,
+  OUT SMBIOS_HANDLE                   *SmbiosHandle
   )
 {
-  EFI_HOB_GUID_TYPE *GuidHob;
-  RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7HobData;
-  SMBIOS_HANDLE Cache;
-  SMBIOS_HANDLE Processor;
-  EFI_STATUS Status;
+  EFI_HOB_GUID_TYPE                *GuidHob;
+  RISC_V_PROCESSOR_TYPE7_HOB_DATA  *Type7HobData;
+  SMBIOS_HANDLE                    Cache;
+  SMBIOS_HANDLE                    Processor;
+  EFI_STATUS                       Status;
 
   DEBUG ((DEBUG_INFO, "Building Type 4.\n"));
   DEBUG ((DEBUG_INFO, "    Processor GUID: %g\n", &Type4HobData->ProcessorGuid));
@@ -96,55 +99,66 @@ BuildSmbiosType4 (
   Type4HobData->SmbiosType4Processor.L1CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
   Type4HobData->SmbiosType4Processor.L2CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
   Type4HobData->SmbiosType4Processor.L3CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
-  GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType7GuidHobGuid));
+  GuidHob                                          = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid));
   if (GuidHob == NULL) {
     DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS Type7 data HOB found.\n"));
     return EFI_NOT_FOUND;
   }
+
   //
   // Go through each RISC_V_PROCESSOR_TYPE4_HOB_DATA for multiple processors.
   //
   do {
     Type7HobData = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)GET_GUID_HOB_DATA (GuidHob);
-    Status = BuildSmbiosType7 (Type4HobData, Type7HobData, &Cache);
+    Status       = BuildSmbiosType7 (Type4HobData, Type7HobData, &Cache);
     if (EFI_ERROR (Status)) {
       return Status;
     }
+
     if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
-        RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1) {
+        RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1)
+    {
       Type4HobData->SmbiosType4Processor.L1CacheHandle = Cache;
     } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
-        RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2) {
+               RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2)
+    {
       Type4HobData->SmbiosType4Processor.L2CacheHandle = Cache;
     } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
-        RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3) {
+               RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3)
+    {
       Type4HobData->SmbiosType4Processor.L3CacheHandle = Cache;
     } else {
       DEBUG ((DEBUG_ERROR, "Improper cache level of SMBIOS handle %d\n", Cache));
     }
-    GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType7GuidHobGuid), GET_NEXT_HOB(GuidHob));
+
+    GuidHob = GetNextGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid), GET_NEXT_HOB (GuidHob));
   } while (GuidHob != NULL);
 
   //
   // Build SMBIOS Type 4 record
   //
-  Processor = SMBIOS_HANDLE_PI_RESERVED;
-  Type4HobData->SmbiosType4Processor.Hdr.Type = SMBIOS_TYPE_PROCESSOR_INFORMATION;
-  Type4HobData->SmbiosType4Processor.Hdr.Length = sizeof(SMBIOS_TABLE_TYPE4);
+  Processor                                     = SMBIOS_HANDLE_PI_RESERVED;
+  Type4HobData->SmbiosType4Processor.Hdr.Type   = SMBIOS_TYPE_PROCESSOR_INFORMATION;
+  Type4HobData->SmbiosType4Processor.Hdr.Length = sizeof (SMBIOS_TABLE_TYPE4);
   Type4HobData->SmbiosType4Processor.Hdr.Handle = 0;
-  Type4HobData->EndingZero = 0;
-  Status = mSmbios->Add (mSmbios, NULL, &Processor, &Type4HobData->SmbiosType4Processor.Hdr);
-  if (EFI_ERROR(Status)) {
+  Type4HobData->EndingZero                      = 0;
+  Status                                        = mSmbios->Add (mSmbios, NULL, &Processor, &Type4HobData->SmbiosType4Processor.Hdr);
+  if (EFI_ERROR (Status)) {
     DEBUG ((DEBUG_ERROR, "Fail to add SMBIOS Type 4\n"));
     return Status;
   }
+
   DEBUG ((DEBUG_INFO, "SMBIOS Type 4 was added. SMBIOS Handle: 0x%x\n", Processor));
   DEBUG ((DEBUG_VERBOSE, "     Socket StringID: %d\n", Type4HobData->SmbiosType4Processor.Socket));
   DEBUG ((DEBUG_VERBOSE, "     Processor Type: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorType));
   DEBUG ((DEBUG_VERBOSE, "     Processor Family: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorFamily));
   DEBUG ((DEBUG_VERBOSE, "     Processor Manufacture StringID: %d\n", Type4HobData->SmbiosType4Processor.ProcessorManufacturer));
-  DEBUG ((DEBUG_VERBOSE, "     Processor Id: 0x%x:0x%x\n", \
-          Type4HobData->SmbiosType4Processor.ProcessorId.Signature, Type4HobData->SmbiosType4Processor.ProcessorId.FeatureFlags));
+  DEBUG ((
+    DEBUG_VERBOSE,
+    "     Processor Id: 0x%x:0x%x\n", \
+    Type4HobData->SmbiosType4Processor.ProcessorId.Signature,
+    Type4HobData->SmbiosType4Processor.ProcessorId.FeatureFlags
+    ));
   DEBUG ((DEBUG_VERBOSE, "     Processor Version StringID: %d\n", Type4HobData->SmbiosType4Processor.ProcessorVersion));
   DEBUG ((DEBUG_VERBOSE, "     Voltage: 0x%x\n", Type4HobData->SmbiosType4Processor.Voltage));
   DEBUG ((DEBUG_VERBOSE, "     External Clock: 0x%x\n", Type4HobData->SmbiosType4Processor.ExternalClock));
@@ -153,7 +167,7 @@ BuildSmbiosType4 (
   DEBUG ((DEBUG_VERBOSE, "     Status: 0x%x\n", Type4HobData->SmbiosType4Processor.Status));
   DEBUG ((DEBUG_VERBOSE, "     ProcessorUpgrade: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorUpgrade));
   DEBUG ((DEBUG_VERBOSE, "     L1 Cache Handle: 0x%x\n", Type4HobData->SmbiosType4Processor.L1CacheHandle));
-  DEBUG ((DEBUG_VERBOSE, "     L2 Cache Handle: 0x%x\n",Type4HobData->SmbiosType4Processor.L2CacheHandle));
+  DEBUG ((DEBUG_VERBOSE, "     L2 Cache Handle: 0x%x\n", Type4HobData->SmbiosType4Processor.L2CacheHandle));
   DEBUG ((DEBUG_VERBOSE, "     L3 Cache Handle: 0x%x\n", Type4HobData->SmbiosType4Processor.L3CacheHandle));
   DEBUG ((DEBUG_VERBOSE, "     Serial Number StringID: %d\n", Type4HobData->SmbiosType4Processor.SerialNumber));
   DEBUG ((DEBUG_VERBOSE, "     Asset Tag StringID: %d\n", Type4HobData->SmbiosType4Processor.AssetTag));
@@ -182,51 +196,55 @@ BuildSmbiosType4 (
 **/
 EFI_STATUS
 BuildSmbiosType44 (
-  IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,
-  IN SMBIOS_HANDLE Type4Handle
+  IN RISC_V_PROCESSOR_TYPE4_HOB_DATA  *Type4HobData,
+  IN SMBIOS_HANDLE                    Type4Handle
   )
 {
-  EFI_HOB_GUID_TYPE *GuidHob;
-  RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificData;
-  SMBIOS_HANDLE RiscVType44;
-  SMBIOS_TABLE_TYPE44 *Type44Ptr;
-  EFI_STATUS Status;
+  EFI_HOB_GUID_TYPE                   *GuidHob;
+  RISC_V_PROCESSOR_SPECIFIC_HOB_DATA  *ProcessorSpecificData;
+  SMBIOS_HANDLE                       RiscVType44;
+  SMBIOS_TABLE_TYPE44                 *Type44Ptr;
+  EFI_STATUS                          Status;
 
   DEBUG ((DEBUG_INFO, "Building Type 44 for...\n"));
   DEBUG ((DEBUG_VERBOSE, "     Processor GUID: %g\n", &Type4HobData->ProcessorGuid));
   DEBUG ((DEBUG_VERBOSE, "     Processor UUID: %d\n", Type4HobData->ProcessorUid));
 
-  GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid));
+  GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSpecificDataGuidHobGuid));
   if (GuidHob == NULL) {
     DEBUG ((DEBUG_ERROR, "No RISC_V_PROCESSOR_SPECIFIC_HOB_DATA found.\n"));
     return EFI_NOT_FOUND;
   }
+
   //
   // Go through each RISC_V_PROCESSOR_SPECIFIC_HOB_DATA for multiple cores.
   //
   do {
     ProcessorSpecificData = (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)GET_GUID_HOB_DATA (GuidHob);
     if (!CompareGuid (&ProcessorSpecificData->ParentProcessorGuid, &Type4HobData->ProcessorGuid) ||
-      ProcessorSpecificData->ParentProcessorUid != Type4HobData->ProcessorUid) {
-      GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB(GuidHob));
+        (ProcessorSpecificData->ParentProcessorUid != Type4HobData->ProcessorUid))
+    {
+      GuidHob = GetNextGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB (GuidHob));
       if (GuidHob == NULL) {
         break;
       }
+
       continue;
     }
 
     DEBUG ((DEBUG_VERBOSE, "================================\n"));
     DEBUG ((DEBUG_VERBOSE, "Core GUID: %g\n", &ProcessorSpecificData->CoreGuid));
 
-    Type44Ptr = AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA) + 2); // Two ending zero.
+    Type44Ptr = AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE44) + sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA) + 2); // Two ending zero.
     if (Type44Ptr == NULL) {
       return EFI_NOT_FOUND;
     }
-    Type44Ptr->Hdr.Type = SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION;
-    Type44Ptr->Hdr.Handle = 0;
-    Type44Ptr->Hdr.Length = sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
-    Type44Ptr->RefHandle = Type4Handle;
-    Type44Ptr->ProcessorSpecificBlock.Length = sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+
+    Type44Ptr->Hdr.Type                                 = SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION;
+    Type44Ptr->Hdr.Handle                               = 0;
+    Type44Ptr->Hdr.Length                               = sizeof (SMBIOS_TABLE_TYPE44) + sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+    Type44Ptr->RefHandle                                = Type4Handle;
+    Type44Ptr->ProcessorSpecificBlock.Length            = sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
     Type44Ptr->ProcessorSpecificBlock.ProcessorArchType = Type4HobData->SmbiosType4Processor.ProcessorFamily2 -
                                                           ProcessorFamilyRiscvRV32 + \
                                                           ProcessorSpecificBlockArchTypeRiscVRV32;
@@ -251,15 +269,17 @@ BuildSmbiosType44 (
     // Add to SMBIOS table.
     //
     RiscVType44 = SMBIOS_HANDLE_PI_RESERVED;
-    Status = mSmbios->Add (mSmbios, NULL, &RiscVType44, &Type44Ptr->Hdr);
-    if (EFI_ERROR(Status)) {
+    Status      = mSmbios->Add (mSmbios, NULL, &RiscVType44, &Type44Ptr->Hdr);
+    if (EFI_ERROR (Status)) {
       DEBUG ((DEBUG_ERROR, "Fail to add SMBIOS Type 44\n"));
       return Status;
     }
+
     DEBUG ((DEBUG_INFO, "SMBIOS Type 44 was added. SMBIOS Handle: 0x%x\n", RiscVType44));
 
-    GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB(GuidHob));
+    GuidHob = GetNextGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB (GuidHob));
   } while (GuidHob != NULL);
+
   return EFI_SUCCESS;
 }
 
@@ -277,14 +297,14 @@ BuildSmbiosType44 (
 EFI_STATUS
 EFIAPI
 RiscVSmbiosBuilderEntry (
-  IN EFI_HANDLE                            ImageHandle,
-  IN EFI_SYSTEM_TABLE                      *SystemTable
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS Status;
-  EFI_HOB_GUID_TYPE *GuidHob;
-  RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData;
-  SMBIOS_HANDLE Processor;
+  EFI_STATUS                       Status;
+  EFI_HOB_GUID_TYPE                *GuidHob;
+  RISC_V_PROCESSOR_TYPE4_HOB_DATA  *Type4HobData;
+  SMBIOS_HANDLE                    Processor;
 
   DEBUG ((DEBUG_INFO, "%a: entry\n", __FUNCTION__));
 
@@ -297,13 +317,15 @@ RiscVSmbiosBuilderEntry (
     DEBUG ((DEBUG_ERROR, "Locate SMBIOS Protocol fail\n"));
     return Status;
   }
-  GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType4GuidHobGuid));
+
+  GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid));
   if (GuidHob == NULL) {
     DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS information found.\n"));
     return EFI_NOT_FOUND;
   }
+
   Type4HobData = (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)GET_GUID_HOB_DATA (GuidHob);
-  Status = EFI_NOT_FOUND;
+  Status       = EFI_NOT_FOUND;
   //
   // Go through each RISC_V_PROCESSOR_TYPE4_HOB_DATA for multiple processors.
   //
@@ -313,15 +335,16 @@ RiscVSmbiosBuilderEntry (
       DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS type 4 created.\n"));
       ASSERT (FALSE);
     }
+
     Status = BuildSmbiosType44 (Type4HobData, Processor);
     if (EFI_ERROR (Status)) {
       DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS type 44 found.\n"));
       ASSERT (FALSE);
     }
 
-    GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType4GuidHobGuid), GET_NEXT_HOB(GuidHob));
+    GuidHob = GetNextGuidHob ((EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid), GET_NEXT_HOB (GuidHob));
   } while (GuidHob != NULL);
+
   DEBUG ((DEBUG_INFO, "%a: exit\n", __FUNCTION__));
   return Status;
 }
-

+ 1 - 2
Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h

@@ -1,7 +1,7 @@
 /** @file
   RISC-V SMBIOS Builder DXE module header file.
 
-  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+  Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -20,4 +20,3 @@
 #include <ProcessorSpecificHobData.h>
 #include <SmbiosProcessorSpecificData.h>
 #endif
-