ProcessorSpecificHobData.h 4.2 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697
  1. /** @file
  2. Definition of Processor Specific Data HOB.
  3. Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_
  7. #define RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_
  8. #include <Uefi.h>
  9. #include <IndustryStandard/SmBios.h>
  10. #include <SmbiosProcessorSpecificData.h>
  11. #define TO_BE_FILLED 0
  12. #define TO_BE_FILLED_BY_VENDOR 0
  13. #define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0
  14. #define TO_BE_FILLED_BY_CODE 0
  15. #pragma pack(1)
  16. ///
  17. /// RISC-V processor specific data HOB
  18. ///
  19. typedef struct {
  20. EFI_GUID ParentProcessorGuid;
  21. UINTN ParentProcessorUid;
  22. EFI_GUID CoreGuid;
  23. VOID *Context; // The additional information of this core which
  24. // built in PEI phase and carried to DXE phase.
  25. // The content is processor or platform specific.
  26. SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;
  27. } RISC_V_PROCESSOR_SPECIFIC_HOB_DATA;
  28. ///
  29. /// RISC-V SMBIOS type 4 (Processor) GUID data HOB
  30. ///
  31. typedef struct {
  32. EFI_GUID ProcessorGuid;
  33. UINTN ProcessorUid;
  34. SMBIOS_TABLE_TYPE4 SmbiosType4Processor;
  35. UINT16 EndingZero;
  36. } RISC_V_PROCESSOR_TYPE4_HOB_DATA;
  37. #define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF
  38. #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7
  39. #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01
  40. #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02
  41. #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03
  42. #define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3
  43. #define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
  44. #define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
  45. #define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5
  46. #define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
  47. #define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
  48. #define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
  49. #define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
  50. #define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
  51. #define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7
  52. #define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
  53. #define RISC_V_CACHE_CONFIGURATION_ENABLED (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
  54. #define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8
  55. #define RISC_V_CACHE_CONFIGURATION_MODE_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
  56. #define RISC_V_CACHE_CONFIGURATION_MODE_WT (0x0 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
  57. #define RISC_V_CACHE_CONFIGURATION_MODE_WB (0x1 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
  58. #define RISC_V_CACHE_CONFIGURATION_MODE_VARIES (0x2 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
  59. #define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
  60. ///
  61. /// RISC-V SMBIOS type 7 (Cache) GUID data HOB
  62. ///
  63. typedef struct {
  64. EFI_GUID ProcessorGuid;
  65. UINTN ProcessorUid;
  66. SMBIOS_TABLE_TYPE7 SmbiosType7Cache;
  67. UINT16 EndingZero;
  68. } RISC_V_PROCESSOR_TYPE7_HOB_DATA;
  69. ///
  70. /// RISC-V SMBIOS type 7 (Cache) GUID data HOB
  71. ///
  72. typedef struct {
  73. RISC_V_PROCESSOR_TYPE4_HOB_DATA *Processor;
  74. RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1Cache;
  75. RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2Cache;
  76. RISC_V_PROCESSOR_TYPE7_HOB_DATA *L3Cache;
  77. } RISC_V_PROCESSOR_SMBIOS_HOB_DATA;
  78. #pragma pack()
  79. #endif