RiscV.h 6.2 KB

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  1. /** @file
  2. RISC-V package definitions.
  3. Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef RISCV_INDUSTRY_STANDARD_H_
  7. #define RISCV_INDUSTRY_STANDARD_H_
  8. #if defined (MDE_CPU_RISCV64)
  9. #define RISC_V_XLEN_BITS 64
  10. #else
  11. #endif
  12. #define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 << 0)
  13. #define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 << 1)
  14. #define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 << 2)
  15. #define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001 << 3)
  16. #define RISC_V_ISA_RV32E_ISA (0x00000001 << 4)
  17. #define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001 << 5)
  18. #define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001 << 6)
  19. #define RISC_V_ISA_RESERVED_1 (0x00000001 << 7)
  20. #define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 << 8)
  21. #define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION (0x00000001 << 9)
  22. #define RISC_V_ISA_RESERVED_2 (0x00000001 << 10)
  23. #define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 << 11)
  24. #define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 << 12)
  25. #define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001 << 13)
  26. #define RISC_V_ISA_RESERVED_3 (0x00000001 << 14)
  27. #define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 << 15)
  28. #define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001 << 16)
  29. #define RISC_V_ISA_RESERVED_4 (0x00000001 << 17)
  30. #define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001 << 18)
  31. #define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION (0x00000001 << 19)
  32. #define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 << 20)
  33. #define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 << 21)
  34. #define RISC_V_ISA_RESERVED_5 (0x00000001 << 22)
  35. #define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 << 23)
  36. #define RISC_V_ISA_RESERVED_6 (0x00000001 << 24)
  37. #define RISC_V_ISA_RESERVED_7 (0x00000001 << 25)
  38. //
  39. // RISC-V CSR definitions.
  40. //
  41. //
  42. // Machine information
  43. //
  44. #define RISCV_CSR_MACHINE_MVENDORID 0xF11
  45. #define RISCV_CSR_MACHINE_MARCHID 0xF12
  46. #define RISCV_CSR_MACHINE_MIMPID 0xF13
  47. #define RISCV_CSR_MACHINE_HARRID 0xF14
  48. //
  49. // Machine Trap Setup.
  50. //
  51. #define RISCV_CSR_MACHINE_MSTATUS 0x300
  52. #define RISCV_CSR_MACHINE_MISA 0x301
  53. #define RISCV_CSR_MACHINE_MEDELEG 0x302
  54. #define RISCV_CSR_MACHINE_MIDELEG 0x303
  55. #define RISCV_CSR_MACHINE_MIE 0x304
  56. #define RISCV_CSR_MACHINE_MTVEC 0x305
  57. #define RISCV_TIMER_COMPARE_BITS 32
  58. //
  59. // Machine Timer and Counter.
  60. //
  61. // #define RISCV_CSR_MACHINE_MTIME 0x701
  62. // #define RISCV_CSR_MACHINE_MTIMEH 0x741
  63. //
  64. // Machine Trap Handling.
  65. //
  66. #define RISCV_CSR_MACHINE_MSCRATCH 0x340
  67. #define RISCV_CSR_MACHINE_MEPC 0x341
  68. #define RISCV_CSR_MACHINE_MCAUSE 0x342
  69. #define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f
  70. #define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1)
  71. #define RISCV_CSR_MACHINE_MBADADDR 0x343
  72. #define RISCV_CSR_MACHINE_MIP 0x344
  73. //
  74. // Machine Protection and Translation.
  75. //
  76. #define RISCV_CSR_MACHINE_MBASE 0x380
  77. #define RISCV_CSR_MACHINE_MBOUND 0x381
  78. #define RISCV_CSR_MACHINE_MIBASE 0x382
  79. #define RISCV_CSR_MACHINE_MIBOUND 0x383
  80. #define RISCV_CSR_MACHINE_MDBASE 0x384
  81. #define RISCV_CSR_MACHINE_MDBOUND 0x385
  82. //
  83. // Supervisor mode CSR.
  84. //
  85. #define RISCV_CSR_SUPERVISOR_SSTATUS 0x100
  86. #define SSTATUS_SIE_BIT_POSITION 1
  87. #define SSTATUS_SPP_BIT_POSITION 8
  88. #define RISCV_CSR_SUPERVISOR_SIE 0x104
  89. #define RISCV_CSR_SUPERVISOR_STVEC 0x105
  90. #define RISCV_CSR_SUPERVISOR_SSCRATCH 0x140
  91. #define RISCV_CSR_SUPERVISOR_SEPC 0x141
  92. #define RISCV_CSR_SUPERVISOR_SCAUSE 0x142
  93. #define SCAUSE_USER_SOFTWARE_INT 0
  94. #define SCAUSE_SUPERVISOR_SOFTWARE_INT 1
  95. #define SCAUSE_USER_TIMER_INT 4
  96. #define SCAUSE_SUPERVISOR_TIMER_INT 5
  97. #define SCAUSE_USER_EXTERNAL_INT 8
  98. #define SCAUSE_SUPERVISOR_EXTERNAL_INT 9
  99. #define RISCV_CSR_SUPERVISOR_STVAL 0x143
  100. #define RISCV_CSR_SUPERVISOR_SIP 0x144
  101. #define RISCV_CSR_SUPERVISOR_SATP 0x180
  102. #if defined (MDE_CPU_RISCV64)
  103. #define RISCV_SATP_MODE_MASK 0xF000000000000000
  104. #define RISCV_SATP_MODE_BIT_POSITION 60
  105. #endif
  106. #define RISCV_SATP_MODE_OFF 0
  107. #define RISCV_SATP_MODE_SV32 1
  108. #define RISCV_SATP_MODE_SV39 8
  109. #define RISCV_SATP_MODE_SV48 9
  110. #define RISCV_SATP_MODE_SV57 10
  111. #define RISCV_SATP_MODE_SV64 11
  112. #define SATP64_ASID_MASK 0x0FFFF00000000000
  113. #define SATP64_PPN_MASK 0x00000FFFFFFFFFFF
  114. #define RISCV_CAUSE_MISALIGNED_FETCH 0x0
  115. #define RISCV_CAUSE_FETCH_ACCESS 0x1
  116. #define RISCV_CAUSE_ILLEGAL_INSTRUCTION 0x2
  117. #define RISCV_CAUSE_BREAKPOINT 0x3
  118. #define RISCV_CAUSE_MISALIGNED_LOAD 0x4
  119. #define RISCV_CAUSE_LOAD_ACCESS 0x5
  120. #define RISCV_CAUSE_MISALIGNED_STORE 0x6
  121. #define RISCV_CAUSE_STORE_ACCESS 0x7
  122. #define RISCV_CAUSE_USER_ECALL 0x8
  123. #define RISCV_CAUSE_HYPERVISOR_ECALL 0x9
  124. #define RISCV_CAUSE_SUPERVISOR_ECALL 0xa
  125. #define RISCV_CAUSE_MACHINE_ECALL 0xb
  126. #define RISCV_CAUSE_FETCH_PAGE_FAULT 0xc
  127. #define RISCV_CAUSE_LOAD_PAGE_FAULT 0xd
  128. #define RISCV_CAUSE_STORE_PAGE_FAULT 0xf
  129. #define RISCV_CAUSE_FETCH_GUEST_PAGE_FAULT 0x14
  130. #define RISCV_CAUSE_LOAD_GUEST_PAGE_FAULT 0x15
  131. #define RISCV_CAUSE_STORE_GUEST_PAGE_FAULT 0x17
  132. //
  133. // Machine Read-Write Shadow of Hypervisor Read-Only Registers
  134. //
  135. #define RISCV_CSR_HTIMEW 0xB01
  136. #define RISCV_CSR_HTIMEHW 0xB81
  137. //
  138. // Machine Host-Target Interface (Non-Standard Berkeley Extension)
  139. //
  140. #define RISCV_CSR_MTOHOST 0x780
  141. #define RISCV_CSR_MFROMHOST 0x781
  142. //
  143. // User mode CSR
  144. //
  145. #define RISCV_CSR_CYCLE 0xc00
  146. #define RISCV_CSR_TIME 0xc01
  147. #endif