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@@ -44,6 +44,9 @@
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//#define VPU_IRQ_CONTROL
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#endif
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+/* if clktree is work,try this...*/
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+//#define STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
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+
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/* if the platform driver knows the name of this driver */
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/* VPU_PLATFORM_DEVICE_NAME */
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#define VPU_SUPPORT_PLATFORM_DRIVER_REGISTER
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@@ -102,6 +105,37 @@ typedef struct vpudrv_instance_pool_t {
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unsigned char codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
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} vpudrv_instance_pool_t;
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+#ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
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+typedef struct vpu_clkgen_t {
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+ void __iomem *en_ctrl;
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+ uint32_t rst_mask;
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+} vpu_clkgen_t;
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+#endif
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+
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+typedef struct vpu_clk_t {
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+#ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
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+ void __iomem *rst_ctrl;
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+ void __iomem *rst_status;
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+ uint32_t en_shift;
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+ uint32_t en_mask;
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+ vpu_clkgen_t apb_clk;
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+ vpu_clkgen_t axi_clk;
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+ vpu_clkgen_t bpu_clk;
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+ vpu_clkgen_t vce_clk;
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+ vpu_clkgen_t aximem_128b;
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+#else
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+ struct clk *apb_clk;
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+ struct clk *axi_clk;
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+ struct clk *bpu_clk;
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+ struct clk *vce_clk;
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+ struct clk *aximem_128b;
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+#endif
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+ void __iomem *clkgen;
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+ phys_addr_t pmu_base;
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+ void __iomem *noc_bus;
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+ bool noc_ctrl;
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+} vpu_clk_t;
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+
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#ifdef VPU_SUPPORT_RESERVED_VIDEO_MEMORY
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#include "vmm.h"
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static video_mm_t s_vmem;
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@@ -109,10 +143,10 @@ static vpudrv_buffer_t s_video_memory = {0};
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#endif /*VPU_SUPPORT_RESERVED_VIDEO_MEMORY*/
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static int vpu_hw_reset(void);
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-static void vpu_clk_disable(struct clk *clk);
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-static int vpu_clk_enable(struct clk *clk);
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-static struct clk *vpu_clk_get(struct device *dev);
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-static void vpu_clk_put(struct clk *clk);
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+static void vpu_clk_disable(vpu_clk_t *clk);
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+static int vpu_clk_enable(vpu_clk_t *clk);
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+static vpu_clk_t *vpu_clk_get(struct platform_device *pdev);
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+static void vpu_clk_put(vpu_clk_t *clk);
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/* end customer definition */
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static vpudrv_buffer_t s_instance_pool = {0};
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@@ -121,7 +155,7 @@ static vpu_drv_context_t s_vpu_drv_context;
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static int s_vpu_major;
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static struct cdev s_vpu_cdev;
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-static struct clk *s_vpu_clk;
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+static vpu_clk_t *s_vpu_clk;
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static int s_vpu_open_ref_count;
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#ifdef VPU_SUPPORT_ISR
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static int s_vpu_irq = VPU_IRQ_NUM;
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@@ -240,25 +274,6 @@ static u32 s_vpu_reg_store[MAX_NUM_VPU_CORE][64];
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#define WriteVpuRegister(addr, val) *(volatile unsigned int *)(s_vpu_register.virt_addr + s_bit_firmware_info[core].reg_base_offset + addr) = (unsigned int)val
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#define WriteVpu(addr, val) *(volatile unsigned int *)(addr) = (unsigned int)val;
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-#define vic_readl(addr) readl((void __iomem *)addr)
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-#define vic_writel(val,addr) writel(val,(void __iomem *)addr)
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-
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-#define rstgen_Software_RESET_BASE_REG_ADDR 0x11840000
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-#define rstgen_Software_RESET_assert0_OFFSET (0x0)
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-#define rstgen_Software_RESET_status0_OFFSET (0x10)
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-#define NBIT_RSTN_VDEC_BRG_MAIN 13
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-#define NBIT_RSTN_VDEC_AXI 14
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-#define NBIT_RSTN_VDEC_BCLK 15
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-#define NBIT_RSTN_VDEC_CCLK 16
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-#define NBIT_RSTN_VDEC_APB 17
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-
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-#define clk_BASE_REG_ADDR 0x11800000
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-#define clk_vdec_axi_ctrl_REG_OFFSET (0xac)
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-#define clk_vdecbrg_mainclk_ctrl_REG_OFFSET (0xb0)
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-#define clk_vdec_bclk_ctrl_REG_OFFSET (0xb4)
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-#define clk_vdec_cclk_ctrl_REG_OFFSET (0xb8)
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-#define clk_vdec_apb_ctrl_REG_OFFSET (0xbc)
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-
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static int vpu_alloc_dma_buffer(vpudrv_buffer_t *vb)
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{
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if (!vb)
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@@ -1295,7 +1310,7 @@ static int vpu_probe(struct platform_device *pdev)
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}
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if (pdev)
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- s_vpu_clk = vpu_clk_get(&pdev->dev);
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+ s_vpu_clk = vpu_clk_get(pdev);
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else
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s_vpu_clk = vpu_clk_get(NULL);
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@@ -1307,7 +1322,6 @@ static int vpu_probe(struct platform_device *pdev)
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#ifdef VPU_SUPPORT_CLOCK_CONTROL
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#else
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vpu_clk_enable(s_vpu_clk);
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- vpu_hw_reset();
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#endif
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#ifdef VPU_SUPPORT_ISR
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@@ -1638,6 +1652,10 @@ static const struct of_device_id cm_vpu_match[] = {
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.compatible = "c&m,cm511-vpu",
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},
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{
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+ .compatible = "starfive,vdec",
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+ },
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+ {
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+ /* end of table */
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},
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};
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MODULE_DEVICE_TABLE(of, cm_vpu_match);
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@@ -1763,175 +1781,393 @@ MODULE_LICENSE("GPL");
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module_init(vpu_init);
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module_exit(vpu_exit);
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-static void _set_reset(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg,int ibit)
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+/* clk&reset for starfive jh7110*/
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+#define PMU_BASE_ADDR 0x17030000
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+#define PMU_VDEC_MASK (0x1 << 3)
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+
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+static void pmu_pd_set(vpu_clk_t *clk, int on_off, uint32_t pd_flag)
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{
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- unsigned int read_value;
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- read_value = vic_readl(p_assert_reg);
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- read_value &= ~(0x1<<ibit);
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- read_value |= (0x1&0x1)<<ibit;
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- vic_writel(read_value,p_assert_reg);
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-
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- do {
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- read_value = (vic_readl(p_status_reg))>>ibit;
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- read_value &= 0x1;
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- } while(read_value!=0x0);
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+ const uint32_t flag_off = 0x0c;
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+ const uint32_t sw_off = 0x44;
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+ void __iomem *base = ioremap(clk->pmu_base, 0x100);
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+
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+ writel(pd_flag, base + flag_off);
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+ writel(0xff, base + sw_off);
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+ if (on_off) {
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+ writel(0x05, base + sw_off);
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+ writel(0x50, base + sw_off);
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+ } else {
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+ writel(0x0a, base + sw_off);
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+ writel(0xa0, base + sw_off);
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+ }
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+
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+ iounmap(base);
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}
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-static void _clr_reset(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg,int ibit)
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+#ifndef STARFIVE_VPU_SUPPORT_CLOCK_CONTROL
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+
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+#define CLK_ENABLE_DATA 1
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+#define CLK_DISABLE_DATA 0
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+#define CLK_EN_SHIFT 31
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+#define CLK_EN_MASK 0x80000000U
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+
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+#define SAIF_BD_APBS_BASE 0x13020000
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+#define WAVE511_CLK_AXI_CTRL 0x118U
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+#define WAVE511_CLK_BPU_CTRL 0x11cU
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+#define WAVE511_CLK_VCE_CTRL 0x120U
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+#define WAVE511_CLK_APB_CTRL 0x124U
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+#define WAVE511_CLK_NOCBUS_CTRL 0x130U
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+
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+#define RSTGEN_SOFTWARE_RESET_ASSERT1 0x2FCU
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+#define RSTGEN_SOFTWARE_RESET_STATUS1 0x30CU
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+
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+#define RSTN_AXI_MASK (0x1 << 15)
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+#define RSTN_BPU_MASK (0x1 << 16)
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+#define RSTN_VCE_MASK (0x1 << 17)
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+#define RSTN_APB_MASK (0x1 << 18)
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+#define RSTN_128B_AXIMEM_MASK (0x1 << 21)
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+
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+static uint32_t saif_get_reg(const volatile void __iomem *addr,
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+ uint32_t shift, uint32_t mask)
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{
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- unsigned int read_value;
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- read_value = vic_readl(p_assert_reg);
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- read_value &= ~(0x1<<ibit);
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- read_value |= (0x0&0x1)<<ibit;
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- vic_writel(read_value,p_assert_reg);
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-
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- do {
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- read_value = (vic_readl(p_status_reg))>>ibit;
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- read_value &= 0x1;
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- } while(read_value!=0x1);
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+ u32 tmp;
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+ tmp = readl(addr);
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+ tmp = (tmp & mask) >> shift;
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+ return tmp;
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}
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-static void _enable_clk(volatile unsigned long p_reg,int ibit)
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+static void saif_set_reg(volatile void __iomem *addr, uint32_t data,
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+ uint32_t shift, uint32_t mask)
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{
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- unsigned int read_value;
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- read_value = vic_readl(p_reg);
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- read_value &= ~(0x1<<ibit);
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- read_value |= (0x1&0x1)<<ibit;
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- vic_writel(read_value,p_reg);
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+ uint32_t tmp;
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+
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+ tmp = readl(addr);
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+ tmp &= ~mask;
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+ tmp |= (data << shift) & mask;
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+ writel(tmp, addr);
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}
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-static void _disable_clk(volatile unsigned long p_reg,int ibit)
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+static void saif_assert_rst(volatile void __iomem *addr,
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+ const volatile void __iomem *addr_status, uint32_t mask)
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{
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- unsigned int read_value;
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- read_value = vic_readl(p_reg);
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- read_value &= ~(0x1<<ibit);
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- read_value |= (0x0&0x1)<<ibit;
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- vic_writel(read_value,p_reg);
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+ uint32_t tmp;
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+
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+ tmp = readl(addr);
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+ tmp |= mask;
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+ writel(tmp, addr);
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+ do {
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+ tmp = readl(addr_status);
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+ } while ((tmp & mask) != 0);
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}
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-static void _reset_assert(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg)
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+static void saif_clear_rst(volatile void __iomem *addr,
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+ const volatile void __iomem *addr_status, uint32_t mask)
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{
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- _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_BRG_MAIN);
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- _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_APB);
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- _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_AXI);
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- _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_BCLK);
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- _set_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_CCLK);
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+ uint32_t tmp;
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+
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+ tmp = readl(addr);
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+ tmp &= ~mask;
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+ writel(tmp, addr);
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+ do {
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+ tmp = readl(addr_status);
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+ } while ((tmp & mask) != mask);
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}
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-static void _reset_clear(volatile unsigned long p_assert_reg,volatile unsigned long p_status_reg)
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+static void vpu_noc_vdec_bus_control(vpu_clk_t *clk, bool enable)
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{
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- _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_BRG_MAIN);
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- _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_AXI);
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- _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_BCLK);
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- _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_CCLK);
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- _clr_reset(p_assert_reg,p_status_reg,NBIT_RSTN_VDEC_APB);
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+ if (enable)
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+ saif_set_reg(clk->noc_bus, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
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+ else
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+ saif_set_reg(clk->noc_bus, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
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}
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-static int _reset(void)
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+static void vpu_aximem_128b_control(vpu_clk_t *clk, bool enable)
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{
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- volatile unsigned long p_breg = (unsigned long)ioremap_nocache(rstgen_Software_RESET_BASE_REG_ADDR,0x20);
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+ if (enable) {
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+ saif_set_reg(clk->axi_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
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+ saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
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+ } else {
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+ saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->aximem_128b.rst_mask);
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+ saif_set_reg(clk->axi_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
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+ }
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+}
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- if(!p_breg){
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- return -1;
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- }
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+static void vpu_clk_control(vpu_clk_t *clk, bool enable)
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+{
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+ if (enable) {
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+ /*enable*/
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+ saif_set_reg(clk->apb_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
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+ saif_set_reg(clk->axi_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
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+ saif_set_reg(clk->bpu_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
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+ saif_set_reg(clk->vce_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
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+
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+ /*clr-reset*/
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+ saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
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+ saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
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+ saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
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+ saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
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+ } else {
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+ /*assert-reset*/
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+ saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
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+ saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
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+ saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
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+ saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
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+
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+ /*disable*/
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+ saif_set_reg(clk->apb_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
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+ saif_set_reg(clk->axi_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
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+ saif_set_reg(clk->bpu_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
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+ saif_set_reg(clk->vce_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
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+ }
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+}
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- _reset_assert(p_breg+rstgen_Software_RESET_assert0_OFFSET,p_breg+rstgen_Software_RESET_status0_OFFSET);
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+static void vpu_clk_reset(vpu_clk_t *clk)
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+{
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+ /*assert-reset*/
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+ saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
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+ saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
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+ saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
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+ saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
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+
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+ /*clr-reset*/
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+ saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
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+ saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
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+ saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->bpu_clk.rst_mask);
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+ saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->vce_clk.rst_mask);
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- mdelay(1);
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+}
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|
|
|
|
|
- _reset_clear(p_breg+rstgen_Software_RESET_assert0_OFFSET,p_breg+rstgen_Software_RESET_status0_OFFSET);
|
|
|
+int vpu_hw_reset(void)
|
|
|
+{
|
|
|
+ if (!s_vpu_clk)
|
|
|
+ return -1;
|
|
|
|
|
|
- iounmap((void *)p_breg);
|
|
|
+ vpu_clk_reset(s_vpu_clk);
|
|
|
|
|
|
- return 0;
|
|
|
+ DPRINTK("[VPUDRV] reset vpu hardware. \n");
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
-static int _clk_control(int enable)
|
|
|
+static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
|
|
|
{
|
|
|
- volatile unsigned long p_breg = (unsigned long)ioremap_nocache(clk_BASE_REG_ADDR,0x100);
|
|
|
- if(!p_breg){
|
|
|
- return -1;
|
|
|
- }
|
|
|
+ if (!pdev)
|
|
|
+ return -ENXIO;
|
|
|
+
|
|
|
+ vpu_clk->pmu_base = PMU_BASE_ADDR;
|
|
|
+ vpu_clk->clkgen = ioremap(SAIF_BD_APBS_BASE, 0x400);
|
|
|
+ if (IS_ERR(vpu_clk->clkgen)) {
|
|
|
+ dev_err(&pdev->dev, "ioremap clkgen failed.\n");
|
|
|
+ return PTR_ERR(vpu_clk->clkgen);
|
|
|
+ }
|
|
|
|
|
|
- if(enable){
|
|
|
- _enable_clk(p_breg+clk_vdec_axi_ctrl_REG_OFFSET,31);
|
|
|
- _enable_clk(p_breg+clk_vdecbrg_mainclk_ctrl_REG_OFFSET,31);
|
|
|
- _enable_clk(p_breg+clk_vdec_bclk_ctrl_REG_OFFSET,31);
|
|
|
- _enable_clk(p_breg+clk_vdec_cclk_ctrl_REG_OFFSET,31);
|
|
|
- _enable_clk(p_breg+clk_vdec_apb_ctrl_REG_OFFSET,31);
|
|
|
- }
|
|
|
- else
|
|
|
- {
|
|
|
- _disable_clk(p_breg+clk_vdec_axi_ctrl_REG_OFFSET,31);
|
|
|
- _disable_clk(p_breg+clk_vdecbrg_mainclk_ctrl_REG_OFFSET,31);
|
|
|
- _disable_clk(p_breg+clk_vdec_bclk_ctrl_REG_OFFSET,31);
|
|
|
- _disable_clk(p_breg+clk_vdec_cclk_ctrl_REG_OFFSET,31);
|
|
|
- _disable_clk(p_breg+clk_vdec_apb_ctrl_REG_OFFSET,31);
|
|
|
- }
|
|
|
+ /* clkgen define */
|
|
|
+ vpu_clk->axi_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_AXI_CTRL;
|
|
|
+ vpu_clk->bpu_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_BPU_CTRL;
|
|
|
+ vpu_clk->vce_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_VCE_CTRL;
|
|
|
+ vpu_clk->apb_clk.en_ctrl = vpu_clk->clkgen + WAVE511_CLK_APB_CTRL;
|
|
|
+ vpu_clk->noc_bus = vpu_clk->clkgen + WAVE511_CLK_NOCBUS_CTRL;
|
|
|
+ vpu_clk->en_mask = CLK_EN_MASK;
|
|
|
+ vpu_clk->en_shift = CLK_EN_SHIFT;
|
|
|
+
|
|
|
+ /* rstgen define */
|
|
|
+ vpu_clk->rst_ctrl = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_ASSERT1;
|
|
|
+ vpu_clk->rst_status = vpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_STATUS1;
|
|
|
+ vpu_clk->axi_clk.rst_mask = RSTN_AXI_MASK;
|
|
|
+ vpu_clk->bpu_clk.rst_mask = RSTN_BPU_MASK;
|
|
|
+ vpu_clk->vce_clk.rst_mask = RSTN_VCE_MASK;
|
|
|
+ vpu_clk->apb_clk.rst_mask = RSTN_APB_MASK;
|
|
|
+ vpu_clk->aximem_128b.rst_mask = RSTN_128B_AXIMEM_MASK;
|
|
|
+
|
|
|
+ if (device_property_read_bool(&pdev->dev, "starfive,vdec_noc_ctrl"))
|
|
|
+ vpu_clk->noc_ctrl = true;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
|
|
|
- iounmap((void *)p_breg);
|
|
|
+static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ vpu_clk_t *vpu_clk;
|
|
|
|
|
|
- return 0;
|
|
|
+ vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
|
|
|
+ if (!vpu_clk)
|
|
|
+ return NULL;
|
|
|
+
|
|
|
+ if (vpu_of_clk_get(pdev, vpu_clk))
|
|
|
+ goto err_get_clk;
|
|
|
+
|
|
|
+ return vpu_clk;
|
|
|
+err_get_clk:
|
|
|
+ kfree(vpu_clk);
|
|
|
+ return NULL;
|
|
|
}
|
|
|
|
|
|
-int vpu_hw_reset(void)
|
|
|
+static void vpu_clk_put(vpu_clk_t *clk)
|
|
|
{
|
|
|
- _reset();
|
|
|
- DPRINTK("[VPUDRV] reset vpu hardware. \n");
|
|
|
- return 0;
|
|
|
+ iounmap(clk->clkgen);
|
|
|
}
|
|
|
|
|
|
-struct clk *vpu_clk_get(struct device *dev)
|
|
|
+static int vpu_clk_enable(vpu_clk_t *clk)
|
|
|
{
|
|
|
- return clk_get(dev, VPU_CLK_NAME);
|
|
|
+ if (clk == NULL || IS_ERR(clk))
|
|
|
+ return -1;
|
|
|
+
|
|
|
+ pmu_pd_set(clk, true, PMU_VDEC_MASK);
|
|
|
+ vpu_clk_control(clk, true);
|
|
|
+ vpu_aximem_128b_control(clk, true);
|
|
|
+
|
|
|
+ if (clk->noc_ctrl == true)
|
|
|
+ vpu_noc_vdec_bus_control(clk, true);
|
|
|
+
|
|
|
+ DPRINTK("[VPUDRV] vpu_clk_enable\n");
|
|
|
+ return 0;
|
|
|
}
|
|
|
-void vpu_clk_put(struct clk *clk)
|
|
|
+
|
|
|
+static void vpu_clk_disable(vpu_clk_t *clk)
|
|
|
{
|
|
|
- if (!(clk == NULL || IS_ERR(clk)))
|
|
|
- clk_put(clk);
|
|
|
+ if (clk == NULL || IS_ERR(clk))
|
|
|
+ return;
|
|
|
+
|
|
|
+ vpu_aximem_128b_control(clk, false);
|
|
|
+ vpu_clk_control(clk, false);
|
|
|
+ pmu_pd_set(clk, false, PMU_VDEC_MASK);
|
|
|
+ if (clk->noc_ctrl == true)
|
|
|
+ vpu_noc_vdec_bus_control(clk, false);
|
|
|
+
|
|
|
+ DPRINTK("[VPUDRV] vpu_clk_disable\n");
|
|
|
}
|
|
|
-int vpu_clk_enable(struct clk *clk)
|
|
|
+
|
|
|
+#else /*STARFIVE_VPU_SUPPORT_CLOCK_CONTROL*/
|
|
|
+
|
|
|
+static int clk_check_err(struct clk *clk)
|
|
|
{
|
|
|
- if (!(clk == NULL || IS_ERR(clk))) {
|
|
|
- /* the bellow is for C&M EVB.*/
|
|
|
- /*
|
|
|
- {
|
|
|
- struct clk *s_vpuext_clk = NULL;
|
|
|
- s_vpuext_clk = clk_get(NULL, "vcore");
|
|
|
- if (s_vpuext_clk)
|
|
|
- {
|
|
|
- DPRINTK("[VPUDRV] vcore clk=%p\n", s_vpuext_clk);
|
|
|
- clk_enable(s_vpuext_clk);
|
|
|
- }
|
|
|
+ return !!(clk == NULL || IS_ERR(clk));
|
|
|
+}
|
|
|
|
|
|
- DPRINTK("[VPUDRV] vbus clk=%p\n", s_vpuext_clk);
|
|
|
- if (s_vpuext_clk)
|
|
|
- {
|
|
|
- s_vpuext_clk = clk_get(NULL, "vbus");
|
|
|
- clk_enable(s_vpuext_clk);
|
|
|
- }
|
|
|
- }
|
|
|
- */
|
|
|
- /* for C&M EVB. */
|
|
|
+int vpu_hw_reset(void)
|
|
|
+{
|
|
|
+ /*to do*/
|
|
|
+ DPRINTK("[VPUDRV] reset vpu hardware. \n");
|
|
|
+ return 0;
|
|
|
+}
|
|
|
|
|
|
- DPRINTK("[VPUDRV] vpu_clk_enable\n");
|
|
|
- //customers needs implementation to turn on clock like clk_enable(clk)
|
|
|
- return 1;
|
|
|
- }
|
|
|
|
|
|
- _clk_control(1);
|
|
|
+static int vpu_of_clk_get(struct platform_device *pdev, vpu_clk_t *vpu_clk)
|
|
|
+{
|
|
|
+ struct resource *pmu;
|
|
|
+ struct device *dev = &pdev->dev;
|
|
|
|
|
|
- return 0;
|
|
|
+ pmu = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu");
|
|
|
+ if (IS_ERR(pmu))
|
|
|
+ dev_warn(dev, "get pmu failed.\n");
|
|
|
+
|
|
|
+ vpu_clk->pmu_base = pmu->start;
|
|
|
+
|
|
|
+ vpu_clk->apb_clk = devm_clk_get(dev, "apb_clk");
|
|
|
+ if (clk_check_err(vpu_clk->apb_clk)) {
|
|
|
+ dev_err(dev, "apb_clk get failed.\n");
|
|
|
+ return PTR_ERR(vpu_clk->apb_clk);
|
|
|
+ }
|
|
|
+
|
|
|
+ vpu_clk->axi_clk = devm_clk_get(dev, "axi_clk");
|
|
|
+ if (clk_check_err(vpu_clk->axi_clk)) {
|
|
|
+ dev_err(dev, "axi_clk get failed.\n");
|
|
|
+ return PTR_ERR(vpu_clk->axi_clk);
|
|
|
+ }
|
|
|
+
|
|
|
+ vpu_clk->bpu_clk = devm_clk_get(dev, "bpu_clk");
|
|
|
+ if (clk_check_err(vpu_clk->bpu_clk)) {
|
|
|
+ dev_err(dev, "bpu_clk get failed.\n");
|
|
|
+ return PTR_ERR(vpu_clk->bpu_clk);
|
|
|
+ }
|
|
|
+
|
|
|
+ vpu_clk->vce_clk = devm_clk_get(dev, "vce_clk");
|
|
|
+ if (clk_check_err(vpu_clk->vce_clk)) {
|
|
|
+ dev_err(dev, "vce_clk get failed.\n");
|
|
|
+ return PTR_ERR(vpu_clk->vce_clk);
|
|
|
+ }
|
|
|
+
|
|
|
+ vpu_clk->aximem_128b = devm_clk_get(dev, "aximem_128b");
|
|
|
+ if (clk_check_err(vpu_clk->aximem_128b)) {
|
|
|
+ dev_err(dev, "aximem_128b get failed.\n");
|
|
|
+ return PTR_ERR(vpu_clk->aximem_128b);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (device_property_read_bool(&pdev->dev, "starfive,vdec_noc_ctrl")) {
|
|
|
+ vpu_clk->noc_bus = devm_platform_ioremap_resource_byname(pdev, "noc_bus");
|
|
|
+ if (IS_ERR(vpu_clk->noc_bus)) {
|
|
|
+ dev_err(&pdev->dev, "get noc_bus failed.\n");
|
|
|
+ return PTR_ERR(vpu_clk->noc_bus);
|
|
|
+ }
|
|
|
+ vpu_clk->noc_ctrl = true;
|
|
|
+ }
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
-void vpu_clk_disable(struct clk *clk)
|
|
|
+static vpu_clk_t *vpu_clk_get(struct platform_device *pdev)
|
|
|
{
|
|
|
- if (!(clk == NULL || IS_ERR(clk))) {
|
|
|
- DPRINTK("[VPUDRV] vpu_clk_disable\n");
|
|
|
- //customers needs implementation to turn off clock like clk_disable(clk)
|
|
|
- }
|
|
|
+ vpu_clk_t *vpu_clk;
|
|
|
|
|
|
- _clk_control(0);
|
|
|
-}
|
|
|
+ if (!pdev)
|
|
|
+ return NULL;
|
|
|
|
|
|
+ vpu_clk = devm_kzalloc(&pdev->dev, sizeof(*vpu_clk), GFP_KERNEL);
|
|
|
+ if (!vpu_clk)
|
|
|
+ return NULL;
|
|
|
|
|
|
+ if (vpu_of_clk_get(pdev, vpu_clk))
|
|
|
+ goto err_of_clk_get;
|
|
|
+
|
|
|
+ return vpu_clk;
|
|
|
+
|
|
|
+err_of_clk_get:
|
|
|
+ kfree(vpu_clk);
|
|
|
+ return NULL;
|
|
|
+}
|
|
|
+static void vpu_clk_put(vpu_clk_t *clk)
|
|
|
+{
|
|
|
+ if (!(clk_check_err(clk->apb_clk)))
|
|
|
+ clk_put(clk->apb_clk);
|
|
|
+ if (!(clk_check_err(clk->axi_clk)))
|
|
|
+ clk_put(clk->axi_clk);
|
|
|
+ if (!(clk_check_err(clk->bpu_clk)))
|
|
|
+ clk_put(clk->bpu_clk);
|
|
|
+ if (!(clk_check_err(clk->vce_clk)))
|
|
|
+ clk_put(clk->vce_clk);
|
|
|
+ if (!(clk_check_err(clk->aximem_128b)))
|
|
|
+ clk_put(clk->aximem_128b);
|
|
|
+}
|
|
|
+static int vpu_clk_enable(vpu_clk_t *clk)
|
|
|
+{
|
|
|
+ pmu_pd_set(clk, true, PMU_VDEC_MASK);
|
|
|
+
|
|
|
+ if (!(clk_check_err(clk->apb_clk)))
|
|
|
+ clk_prepare_enable(clk->apb_clk);
|
|
|
+ if (!(clk_check_err(clk->axi_clk)))
|
|
|
+ clk_prepare_enable(clk->axi_clk);
|
|
|
+ if (!(clk_check_err(clk->bpu_clk)))
|
|
|
+ clk_prepare_enable(clk->bpu_clk);
|
|
|
+ if (!(clk_check_err(clk->vce_clk)))
|
|
|
+ clk_prepare_enable(clk->vce_clk);
|
|
|
+ if (!(clk_check_err(clk->aximem_128b)))
|
|
|
+ clk_prepare_enable(clk->aximem_128b);
|
|
|
+
|
|
|
+ DPRINTK("[VPUDRV] vpu_clk_enable\n");
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void vpu_clk_disable(vpu_clk_t *clk)
|
|
|
+{
|
|
|
+ if (!(clk_check_err(clk->apb_clk)))
|
|
|
+ clk_disable_unprepare(clk->apb_clk);
|
|
|
+ if (!(clk_check_err(clk->axi_clk)))
|
|
|
+ clk_disable_unprepare(clk->axi_clk);
|
|
|
+ if (!(clk_check_err(clk->bpu_clk)))
|
|
|
+ clk_disable_unprepare(clk->bpu_clk);
|
|
|
+ if (!(clk_check_err(clk->vce_clk)))
|
|
|
+ clk_disable_unprepare(clk->vce_clk);
|
|
|
+ if (!(clk_check_err(clk->aximem_128b)))
|
|
|
+ clk_disable_unprepare(clk->aximem_128b);
|
|
|
+
|
|
|
+ pmu_pd_set(clk, false, PMU_VDEC_MASK);
|
|
|
+}
|
|
|
+#endif
|