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JPU: add jpu support for starfive jh7110 soc.

1) add .gitignore to ignore intermediate files.
2) add PM(clk/pmu ctrl) for jpu.
SaminGuo 2 years ago
parent
commit
a410661519

+ 161 - 0
codaj12/.gitignore

@@ -0,0 +1,161 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# NOTE! Don't add files that are generated in specific
+# subdirectories here. Add them in the ".gitignore" file
+# in that subdirectory instead.
+#
+# NOTE! Please use 'git ls-files -i --exclude-standard'
+# command after changing this file, to see if there are
+# any tracked files which get ignored after the change.
+#
+# Normal rules (sorted alphabetically)
+#
+.*
+*.a
+*.asn1.[ch]
+*.bin
+*.bz2
+*.c.[012]*.*
+*.dt.yaml
+*.dtb
+*.dtb.S
+*.dwo
+*.elf
+*.gcno
+*.gz
+*.i
+*.ko
+*.lex.c
+*.ll
+*.lst
+*.lz4
+*.lzma
+*.lzo
+*.mod
+*.mod.c
+*.o
+*.o.*
+*.patch
+*.s
+*.so
+*.so.dbg
+*.su
+*.symtypes
+*.tab.[ch]
+*.tar
+*.xz
+*.zst
+Module.symvers
+modules.builtin
+modules.order
+
+#
+# Top-level generic files
+#
+/tags
+/TAGS
+/linux
+/vmlinux
+/vmlinux.32
+/vmlinux.symvers
+/vmlinux-gdb.py
+/vmlinuz
+/System.map
+/Module.markers
+/modules.builtin.modinfo
+/modules.nsdeps
+
+#
+# RPM spec file (make rpm-pkg)
+#
+/*.spec
+
+#
+# Debian directory (make deb-pkg)
+#
+/debian/
+
+#
+# Snap directory (make snap-pkg)
+#
+/snap/
+
+#
+# tar directory (make tar*-pkg)
+#
+/tar-install/
+
+#
+# We don't want to ignore the following even if they are dot-files
+#
+!.clang-format
+!.cocciconfig
+!.get_maintainer.ignore
+!.gitattributes
+!.gitignore
+!.mailmap
+
+#
+# Generated include files
+#
+/include/config/
+/include/generated/
+/include/ksym/
+/arch/*/include/generated/
+
+# stgit generated dirs
+patches-*
+
+# quilt's files
+patches
+series
+
+# cscope files
+cscope.*
+ncscope.*
+
+# gnu global files
+GPATH
+GRTAGS
+GSYMS
+GTAGS
+
+# id-utils files
+ID
+
+*.orig
+*~
+\#*#
+
+# obj
+/obj/
+jpg_dec_test
+jpg_enc_test
+#
+# Leavings from module signing
+#
+extra_certificates
+signing_key.pem
+signing_key.priv
+signing_key.x509
+x509.genkey
+
+# Kconfig presets
+/all.config
+/alldef.config
+/allmod.config
+/allno.config
+/allrandom.config
+/allyes.config
+
+# Kconfig savedefconfig output
+/defconfig
+
+# Kdevelop4
+*.kdev4
+
+# Clang's compilation database file
+/compile_commands.json
+
+# Documentation toolchain
+sphinx_*/

+ 0 - 3
codaj12/build_for_riscv.sh

@@ -45,6 +45,3 @@ cp ${jpu_path}/jpg_enc_test ${jpu_path}/jpg_dec_test $obj_jpu
 
 #cp driver
 cp ${jpu_driver}/jpu.ko $obj_jpu_driver
-cp -rdvp jpu_driver ../../../freedom-u-sdk/work/buildroot_initramfs_sysroot/root/
-
-

+ 333 - 26
codaj12/jdi/linux/driver/jpu.c

@@ -48,9 +48,13 @@
 
 /* definitions to be changed as customer  configuration */
 /* if you want to have clock gating scheme frame by frame */
-#define JPU_SUPPORT_CLOCK_CONTROL
+//#define JPU_SUPPORT_CLOCK_CONTROL
 #define JPU_SUPPORT_ISR
 //#define JPU_IRQ_CONTROL
+
+/* if clktree is work,try this...*/
+//#define STARFIVE_JPU_SUPPORT_CLOCK_CONTROL
+
 /* if the platform driver knows the name of this driver */
 /* JPU_PLATFORM_DEVICE_NAME */
 #define JPU_SUPPORT_PLATFORM_DRIVER_REGISTER
@@ -106,6 +110,31 @@ typedef struct jpudrv_instance_pool_t {
 	unsigned char codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
 } jpudrv_instance_pool_t;
 
+#ifndef STARFIVE_JPU_SUPPORT_CLOCK_CONTROL
+typedef struct jpu_clkgen_t {
+	void __iomem *en_ctrl;
+	uint32_t rst_mask;
+} jpu_clkgen_t;
+#endif
+
+typedef struct jpu_clk_t {
+#ifndef STARFIVE_JPU_SUPPORT_CLOCK_CONTROL
+	void __iomem *rst_ctrl;
+	void __iomem *rst_status;
+	uint32_t en_shift;
+	uint32_t en_mask;
+	jpu_clkgen_t apb_clk;
+	jpu_clkgen_t axi_clk;
+	jpu_clkgen_t core_clk;
+#else
+	struct clk *apb_clk;
+	struct clk *axi_clk;
+	struct clk *core_clk;
+#endif
+	void __iomem *clkgen;
+	phys_addr_t pmu_base;
+} jpu_clk_t;
+
 #ifdef JPU_SUPPORT_RESERVED_VIDEO_MEMORY
 #include "jmm.h"
 static jpu_mm_t         s_jmem;
@@ -114,17 +143,17 @@ static jpudrv_buffer_t  s_video_memory = {0};
 
 
 static int jpu_hw_reset(void);
-static void jpu_clk_disable(struct clk *clk);
-static int jpu_clk_enable(struct clk *clk);
-static struct clk *jpu_clk_get(struct device *dev);
-static void jpu_clk_put(struct clk *clk);
+static void jpu_clk_disable(jpu_clk_t *clk);
+static void jpu_clk_enable(jpu_clk_t *clk);
+static jpu_clk_t *jpu_clk_get(struct platform_device *pdev);
+static void jpu_clk_put(jpu_clk_t *clk);
 // end customer definition
 
 static jpudrv_buffer_t s_instance_pool = {0};
 static jpu_drv_context_t s_jpu_drv_context;
 static int s_jpu_major;
 static struct cdev s_jpu_cdev;
-static struct clk *s_jpu_clk;
+static jpu_clk_t *s_jpu_clk;
 static int s_jpu_open_ref_count;
 #ifdef JPU_SUPPORT_ISR
 static int s_jpu_irq = JPU_IRQ_NUM;
@@ -774,7 +803,7 @@ static int jpu_probe(struct platform_device *pdev)
     }
 
     if (pdev)
-        s_jpu_clk = jpu_clk_get(&pdev->dev);
+        s_jpu_clk = jpu_clk_get(pdev);
     else
         s_jpu_clk = jpu_clk_get(NULL);
 
@@ -891,7 +920,8 @@ static int jpu_remove(struct platform_device *pdev)
 	return 0;
 }
 
-#ifdef CONFIG_PM
+//#ifdef CONFIG_PM
+#if 1
 static int jpu_suspend(struct platform_device *pdev, pm_message_t state)
 {
     jpu_clk_disable(s_jpu_clk);
@@ -912,6 +942,7 @@ static int jpu_resume(struct platform_device *pdev)
 #ifdef JPU_SUPPORT_PLATFORM_DRIVER_REGISTER
 static const struct of_device_id jpu_of_id_table[] = {
 	{ .compatible = "cm,codaj12-jpu-1" },
+	{ .compatible = "starfive,jpu" },
 	{}
 };
 
@@ -1000,40 +1031,316 @@ MODULE_LICENSE("GPL");
 module_init(jpu_init);
 module_exit(jpu_exit);
 
+/*pmu define*/
+#define PMU_BASE_ADDR		0x17030000
+#define PMU_JPU_MASK		(0x1 << 3)
+
+static void pmu_pd_set(jpu_clk_t *clk, int on_off, uint32_t pd_flag)
+{
+	const uint32_t flag_off = 0x0c;
+	const uint32_t sw_off = 0x44;
+	void __iomem *base = ioremap(clk->pmu_base, 0x100);
+
+	writel(pd_flag, base + flag_off);
+	writel(0xff, base + sw_off);
+	if (on_off) {
+		writel(0x05, base + sw_off);
+		writel(0x50, base + sw_off);
+	} else {
+		writel(0x0a, base + sw_off);
+		writel(0xa0, base + sw_off);
+	}
+
+	iounmap(base);
+}
+
+#ifndef STARFIVE_JPU_SUPPORT_CLOCK_CONTROL
+#define CLK_ENABLE_DATA		1
+#define CLK_DISABLE_DATA	0
+#define CLK_EN_SHIFT		31
+#define CLK_EN_MASK		0x80000000U
+
+#define SAIF_BD_APBS_BASE	0x13020000
+#define CODAJ12_CLK_AXI_CTRL	0x108U
+#define CODAJ12_CLK_APB_CTRL	0x110U
+#define CODAJ12_CLK_CORE_CTRL	0x10cU
+
+#define RSTGEN_SOFTWARE_RESET_ASSERT1	0x2FCU
+#define RSTGEN_SOFTWARE_RESET_STATUS1	0x30CU
+
+#define RSTN_AXI_MASK			(0x1 << 12)
+#define RSTN_CORE_MASK			(0x1 << 13)
+#define RSTN_APB_MASK			(0x1 << 14)
+
+static __maybe_unused uint32_t saif_get_reg(
+			const volatile void __iomem *addr,
+			uint32_t shift, uint32_t mask)
+{
+	u32 tmp;
+	tmp = readl(addr);
+	tmp = (tmp & mask) >> shift;
+	return tmp;
+}
+
+static void saif_set_reg(volatile void __iomem *addr, uint32_t data,
+			uint32_t shift, uint32_t mask)
+{
+	uint32_t tmp;
+
+	tmp = readl(addr);
+	tmp &= ~mask;
+	tmp |= (data << shift) & mask;
+	writel(tmp, addr);
+}
+
+static void saif_assert_rst(volatile void __iomem *addr,
+			const volatile void __iomem *addr_status, uint32_t mask)
+{
+	uint32_t tmp;
+
+	tmp = readl(addr);
+	tmp |= mask;
+	writel(tmp, addr);
+	do {
+		tmp = readl(addr_status);
+	} while ((tmp & mask) != 0);
+}
+
+static void saif_clear_rst(volatile void __iomem *addr,
+			const volatile void __iomem *addr_status, uint32_t mask)
+{
+	uint32_t tmp;
+
+	tmp = readl(addr);
+	tmp &= ~mask;
+	writel(tmp, addr);
+	do {
+		tmp = readl(addr_status);
+	} while ((tmp & mask) != mask);
+}
+
+static void jpu_clk_control(jpu_clk_t *clk, bool enable)
+{
+	if (enable) {
+		/*enable*/
+		saif_set_reg(clk->apb_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
+		saif_set_reg(clk->axi_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
+		saif_set_reg(clk->core_clk.en_ctrl, CLK_ENABLE_DATA, clk->en_shift, clk->en_mask);
+
+		/*clr-reset*/
+		saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
+		saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
+		saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->core_clk.rst_mask);
+	} else {
+		/*assert-reset*/
+		saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
+		saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
+		saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->core_clk.rst_mask);
+		/*disable*/
+		saif_set_reg(clk->apb_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
+		saif_set_reg(clk->axi_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
+		saif_set_reg(clk->core_clk.en_ctrl, CLK_DISABLE_DATA, clk->en_shift, clk->en_mask);
+	}
+}
+
+static void jpu_clk_reset(jpu_clk_t *clk)
+{
+	/*assert-reset*/
+	saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
+	saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
+	saif_assert_rst(clk->rst_ctrl, clk->rst_status, clk->core_clk.rst_mask);
+
+	/*clr-reset*/
+	saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->apb_clk.rst_mask);
+	saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->axi_clk.rst_mask);
+	saif_clear_rst(clk->rst_ctrl, clk->rst_status, clk->core_clk.rst_mask);
+}
+
+int jpu_hw_reset(void)
+{
+	if (!s_jpu_clk)
+		return -1;
+
+	jpu_clk_reset(s_jpu_clk);
+
+	DPRINTK("[VPUDRV] reset vpu hardware. \n");
+	return 0;
+}
+
+static int jpu_of_clk_get(struct platform_device *pdev, jpu_clk_t *jpu_clk)
+{
+	if (!pdev)
+		return -ENXIO;
+
+	jpu_clk->pmu_base = PMU_BASE_ADDR;
+
+	jpu_clk->clkgen = ioremap(SAIF_BD_APBS_BASE, 0x400);
+	if (IS_ERR(jpu_clk->clkgen)) {
+		dev_err(&pdev->dev, "ioremap clkgen failed.\n");
+		return PTR_ERR(jpu_clk->clkgen);
+	}
+
+	/* clkgen define */
+	jpu_clk->axi_clk.en_ctrl = jpu_clk->clkgen + CODAJ12_CLK_AXI_CTRL;
+	jpu_clk->apb_clk.en_ctrl = jpu_clk->clkgen + CODAJ12_CLK_APB_CTRL;
+	jpu_clk->core_clk.en_ctrl = jpu_clk->clkgen + CODAJ12_CLK_CORE_CTRL;
+	jpu_clk->en_mask = CLK_EN_MASK;
+	jpu_clk->en_shift = CLK_EN_SHIFT;
+
+	/* rstgen define */
+	jpu_clk->rst_ctrl = jpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_ASSERT1;
+	jpu_clk->rst_status = jpu_clk->clkgen + RSTGEN_SOFTWARE_RESET_STATUS1;
+	jpu_clk->axi_clk.rst_mask = RSTN_AXI_MASK;
+	jpu_clk->apb_clk.rst_mask = RSTN_APB_MASK;
+	jpu_clk->core_clk.rst_mask = RSTN_CORE_MASK;
+
+	return 0;
+}
+
+static jpu_clk_t *jpu_clk_get(struct platform_device *pdev)
+{
+	jpu_clk_t *jpu_clk;
+
+	jpu_clk = devm_kzalloc(&pdev->dev, sizeof(*jpu_clk), GFP_KERNEL);
+	if (!jpu_clk)
+		return NULL;
+
+	if (jpu_of_clk_get(pdev, jpu_clk))
+		goto err_get_clk;
+
+	return jpu_clk;
+err_get_clk:
+	kfree(jpu_clk);
+	return NULL;
+}
+
+static void jpu_clk_put(jpu_clk_t *clk)
+{
+	iounmap(clk->clkgen);
+}
+
+static void jpu_clk_enable(jpu_clk_t *clk)
+{
+	if (clk == NULL || IS_ERR(clk))
+		return;
+
+	pmu_pd_set(clk, true, PMU_JPU_MASK);
+	jpu_clk_control(clk, true);
+
+	DPRINTK("[VPUDRV] vpu_clk_enable\n");
+}
+
+static void jpu_clk_disable(jpu_clk_t *clk)
+{
+	if (clk == NULL || IS_ERR(clk))
+		return;
+
+	jpu_clk_control(clk, false);
+	pmu_pd_set(clk, false, PMU_JPU_MASK);
+
+	DPRINTK("[VPUDRV] vpu_clk_disable\n");
+}
+
+#else /* STARFIVE_JPU_SUPPORT_CLOCK_CONTROL */
+
 static int jpu_hw_reset(void)
 {
     DPRINTK("[JPUDRV] request jpu reset from application. \n");
     return 0;
 }
 
-
-struct clk *jpu_clk_get(struct device *dev)
+static int clk_check_err(struct clk *clk)
 {
-    return clk_get(dev, JPU_CLK_NAME);
+	return !!(clk == NULL || IS_ERR(clk));
 }
-void jpu_clk_put(struct clk *clk)
+
+static int jpu_of_clk_get(struct platform_device *pdev, jpu_clk_t *jpu_clk)
 {
-    if (!(clk == NULL || IS_ERR(clk)))
-        clk_put(clk);
+	struct resource *pmu;
+	struct device *dev = &pdev->dev;
+
+	pmu = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu");
+	if (IS_ERR(pmu))
+		dev_warn(dev, "get pmu failed.\n");
+
+	jpu_clk->pmu_base = pmu->start;
+
+	jpu_clk->apb_clk = devm_clk_get(dev, "apb_clk");
+	if (clk_check_err(jpu_clk->apb_clk)) {
+		dev_err(dev, "apb_clk get failed.\n");
+		return PTR_ERR(jpu_clk->apb_clk);
+	}
+
+	jpu_clk->axi_clk = devm_clk_get(dev, "axi_clk");
+	if (clk_check_err(jpu_clk->axi_clk)) {
+		dev_err(dev, "axi_clk get failed.\n");
+		return PTR_ERR(jpu_clk->axi_clk);
+	}
+
+	jpu_clk->core_clk = devm_clk_get(dev, "core_clk");
+	if (clk_check_err(jpu_clk->core_clk)) {
+		dev_err(dev, "core_clk get failed.\n");
+		return PTR_ERR(jpu_clk->core_clk);
+	}
+	return 0;
 }
-int jpu_clk_enable(struct clk *clk)
+
+
+static jpu_clk_t *jpu_clk_get(struct platform_device *pdev)
 {
+	jpu_clk_t *jpu_clk;
+
+	if (!pdev)
+		return NULL;
+
+	jpu_clk = devm_kzalloc(&pdev->dev, sizeof(*jpu_clk), GFP_KERNEL);
+	if (!jpu_clk)
+		return NULL;
+
+	if (jpu_of_clk_get(pdev, jpu_clk))
+		goto err_of_clk_get;
+
+	return jpu_clk;
+
+err_of_clk_get:
+	kfree(jpu_clk);
+	return NULL;
 
-    if (clk) {
-        DPRINTK("[JPUDRV] jpu_clk_enable\n");
-        // You need to implement it
-        return 1;
-    }
-    return 0;
 }
 
-void jpu_clk_disable(struct clk *clk)
+static void jpu_clk_put(jpu_clk_t *clk)
 {
-    if (!(clk == NULL || IS_ERR(clk))) {
-        DPRINTK("[JPUDRV] jpu_clk_disable\n");
-        // You need to implement it
-    }
+	if (!(clk_check_err(clk->apb_clk)))
+		clk_put(clk->apb_clk);
+	if (!(clk_check_err(clk->axi_clk)))
+		clk_put(clk->axi_clk);
+	if (!(clk_check_err(clk->core_clk)))
+		clk_put(clk->core_clk);
 }
 
+static void jpu_clk_enable(jpu_clk_t *clk)
+{
+	pmu_pd_set(clk, true, PMU_JPU_MASK);
+
+	if (!(clk_check_err(clk->apb_clk)))
+		clk_prepare_enable(clk->apb_clk);
+	if (!(clk_check_err(clk->axi_clk)))
+		clk_prepare_enable(clk->axi_clk);
+	if (!(clk_check_err(clk->core_clk)))
+		clk_prepare_enable(clk->core_clk);
 
+	DPRINTK("[VPUDRV] vpu_clk_enable\n");
+}
 
+static void jpu_clk_disable(jpu_clk_t *clk)
+{
+	if (!(clk_check_err(clk->apb_clk)))
+		clk_disable_unprepare(clk->apb_clk);
+	if (!(clk_check_err(clk->axi_clk)))
+		clk_disable_unprepare(clk->axi_clk);
+	if (!(clk_check_err(clk->core_clk)))
+		clk_disable_unprepare(clk->core_clk);
+
+	pmu_pd_set(clk, false, PMU_JPU_MASK);
+}
+#endif /* STARFIVE_JPU_SUPPORT_CLOCK_CONTROL */

+ 1 - 1
codaj12/jdi/linux/driver/jpu.h

@@ -21,7 +21,7 @@
 #define JDI_IOCTL_GET_INSTANCE_NUM                  _IO(JDI_IOCTL_MAGIC, 10)
 #define JDI_IOCTL_FLUSH_DCACHE                 		_IO(JDI_IOCTL_MAGIC, 11)
 
-#define MEM2SYS(addr) ((addr) > 0x80000000 && (addr) < 0x87FFFFFFF ? ((addr)+0xF80000000):(addr))
+#define MEM2SYS(addr) ((addr) > 0x40000000 && (addr) < 0x240000000 ? ((addr)+0x400000000):(addr))
 
 typedef struct jpudrv_flush_cache_t {
     unsigned long start;

+ 0 - 2
codaj12/jdi/linux/driver/jpu.mod

@@ -1,2 +0,0 @@
-/home/samin/data/startlight/freedom-u-sdk/soft_3rdparty/codaj12/jdi/linux/driver/jpu.o
-

+ 2 - 0
wave511/code/script/dec_128X128_265_10b.sh

@@ -0,0 +1,2 @@
+#!/bin/sh
+./dec_test --input stream/hevc_main10/small_size_128x128.yuv_main10_64.bin --output output/small_size_128x128.yuv_main10_64.bin.yuv --codec 12

+ 2 - 0
wave511/code/script/dec_144p_265.sh

@@ -0,0 +1,2 @@
+#!/bin/sh
+./dec_test --input stream/hevc/akiyo.cfg_ramain_tv0.cfg.265 --output output/akiyo.cfg_ramain_tv0.cfg.265.yuv --codec 12

+ 2 - 0
wave511/code/script/dec_240p_264.sh

@@ -0,0 +1,2 @@
+#!/bin/sh
+./dec_test --input stream/avc/bd_8b_01.cfg_0.264 --output output/bd_8b_01.cfg_0.264.yuv --codec 0

+ 2 - 0
wave511/code/script/dec_240p_264_10b.sh

@@ -0,0 +1,2 @@
+#!/bin/sh
+./dec_test --input stream/avc_main10/bd_10b_01.cfg_0.264  --output output/bd_10b_01.cfg_0.264.yuv --codec 0

+ 1 - 1
wave511/code/vdi/linux/driver/vpu.h

@@ -23,7 +23,7 @@
 #define VDI_IOCTL_GET_FREE_MEM_SIZE         _IO(VDI_IOCTL_MAGIC, 13)
 #define VDI_IOCTL_FLUSH_DCACHE				_IO(VDI_IOCTL_MAGIC, 14)
 
-#define DRAM_MEM2SYS(addr) ((addr) > 0x80000000 && (addr) < 0x87FFFFFFF ? ((addr)+0xF80000000):(addr))
+#define DRAM_MEM2SYS(addr) ((addr) > 0x40000000 && (addr) < 0x43FFFFFFF ? ((addr)+0x400000000):(addr))
 #define ioremap_nocache ioremap
 
 typedef struct vpudrv_flush_cache_t {

+ 0 - 50
wave511/code/vdi/linux/driver_test/Makefile

@@ -1,50 +0,0 @@
-# Comment/uncomment the	following line to disable/enable debugging
-#DEBUG = y
-
-# Add your debugging flag (or not) to CFLAGS
-ifeq ($(DEBUG),y)
-  DEBFLAGS = -O	-g # "-O" is needed to expand inlines
-else
-  DEBFLAGS = -O2
-endif
-
-export CC="$(CROSS_COMPILE)gcc"
-export AR="$(CROSS_COMPILE)ar"
-export CXX="${CROSS_COMPILE}g++"
-export AS="${CROSS_COMPILE}as"
-export LD="${CROSS_COMPILE}ld"
-export RANLIB="${CROSS_COMPILE}ranlib"
-export READELF="${CROSS_COMPILE}readelf"
-export STRIP="${CROSS_COMPILE}strip"
-
-
-EXTRA_CFLAGS +=	$(DEBFLAGS) -I$(LDDINCDIR) -Wno-unused-function
-
-ifneq ($(KERNELRELEASE),)
-# call from kernel build system
-
-obj-m	:= dma_test.o
-
-else
-
-KERNELDIR := /home/samin/freedom-u-sdk/work/linux
-
-PWD	  := $(shell pwd)
-
-default:
-	$(MAKE)	-C $(KERNELDIR)	M=$(PWD) LDDINCDIR=$(PWD)/../include modules
-
-endif
-
-
-
-clean:
-	rm -rf *.o *~ core .depend .*.cmd *.ko *.mod.c .tmp_versions
-
-depend .depend dep:
-	$(CC) $(CFLAGS)	-M *.c > .depend
-
-
-ifeq (.depend,$(wildcard .depend))
-include	.depend
-endif

+ 0 - 0
wave511/code/vdi/linux/driver_test/Module.symvers


+ 0 - 193
wave511/code/vdi/linux/driver_test/dma_test.c

@@ -1,193 +0,0 @@
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/of.h>
-#include <linux/wait.h>
-#include <linux/list.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/uaccess.h>
-#include <linux/cdev.h>
-#include <linux/slab.h>
-#include <linux/of_address.h>
-#include <linux/of_reserved_mem.h>
-#include <linux/sched.h>
-#include <linux/sched/signal.h>
-#include <linux/version.h>
-#include <linux/kfifo.h>
-#include <linux/kthread.h>
-#include <asm/io.h>
-#include <mach-u74/starfive_u74.h>
-
-#define VPU_PLATFORM_DEVICE_NAME "dma_test"
-
-
-struct device *vpu_dev;
-
-static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
-{
-	return 0;
-}
-
-static int vpu_open(struct inode *inode, struct file *filp)
-{
-    return 0;
-}
-
-/*static int vpu_ioctl(struct inode *inode, struct file *filp, u_int cmd, u_long arg) // for kernel 2.6.9 of C&M*/
-static long vpu_ioctl(struct file *filp, u_int cmd, u_long arg)
-{
-   
-    return 0;
-}
-
-static ssize_t vpu_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos)
-{
-
-    return -1;
-}
-
-static ssize_t vpu_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos)
-{
-    return -1;
-}
-
-static int vpu_release(struct inode *inode, struct file *filp)
-{
-   return 0;
-}
-
-static int vpu_fasync(int fd, struct file *filp, int mode)
-{
-	return 0;
-}
-
-struct file_operations vpu_fops = {
-    .owner = THIS_MODULE,
-    .open = vpu_open,
-    .read = vpu_read,
-    .write = vpu_write,
-    /*.ioctl = vpu_ioctl, // for kernel 2.6.9 of C&M*/
-    .unlocked_ioctl = vpu_ioctl,
-    .release = vpu_release,
-    .fasync = vpu_fasync,
-    .mmap = vpu_mmap,
-};
-
-
-struct dma_addr_t{
-	unsigned long phy;
-	unsigned long base;
-	int size;
-};
-struct dma_addr_t dma_addr[10] = {0};
-
-static int vpu_probe(struct platform_device *pdev)
-{
-    int err = 0;
-	int i = 0;
-
-    printk("[VPUDRV] dma_test vpu_probe\n");
-	if(pdev){
-		vpu_dev = &pdev->dev;
-		dev_info(vpu_dev,"device init.\n");
-	}
-    
-#if 0   //use reserved dma space
-	err = of_reserved_mem_device_init(vpu_dev);
-	if(err) {
-		dev_err(vpu_dev, "Could not get reserved memory\n");
-		goto ERROR_PROVE_DEVICE;
-	  }
-	 
-	  /* Allocate memory */
-	  dma_set_coherent_mask(vpu_dev, 0xFFFFFFFF);
-#endif
-	 for(i = 0;i<10;i++)
-	 {
-		 dma_addr[i].size = 10485760;	 
-	 }
-
-	 //alloc
-	for(i=0;i<10;i++){
-		dma_addr[i].base = (unsigned long)dma_alloc_coherent(vpu_dev, PAGE_ALIGN(dma_addr[i].size), (dma_addr_t *) (&dma_addr[i].phy), GFP_DMA | GFP_KERNEL);
-		printk("dma_alloc_coherent, physaddr:0x%lx,  virtual_addr:0x%lx size=%d \n",dma_addr[i].phy,dma_addr[i].base,dma_addr[i].size);
-	}
-	  
-	  //free
-	for(i=0;i<10;i++){	
-		dma_free_coherent(vpu_dev, PAGE_ALIGN(dma_addr[i].size), (void *)dma_addr[i].base, dma_addr[i].phy);
-		printk(" dma_free_coherent, physaddr:0x%lx,  virtual_addr:0x%lx size=%d \n",dma_addr[i].phy,dma_addr[i].base,dma_addr[i].size);
-	}
-
-    return 0;
-ERROR_PROVE_DEVICE:
-	printk("ERROR_PROVE_DEVICE\n");
-	return -1;
-}
-
-
-static int vpu_remove(struct platform_device *pdev)
-{
-	return 0;
-}
-
-static int vpu_suspend(struct platform_device *pdev, pm_message_t state)
-{
-	return 0;
-}
-
-static int vpu_suspend(struct device *dev)
-{
-	return 0;
-}
-static int  vpu_resume(struct device *dev)
-{
-	return 0;
-}
-
-static int vpu_resume(struct platform_device *pdev)
-{
-	return 0;
-}
-
-static const struct of_device_id cm_vpu_match[] = {
-    {
-        .compatible = "stf,dma_test",
-    },
-    {
-    },
-};
-MODULE_DEVICE_TABLE(of, cm_vpu_match);
-
-static const struct dev_pm_ops vpu_pm_ops = {
-	SET_RUNTIME_PM_OPS(vpu_suspend, vpu_resume, NULL)
-};
-
-static const struct of_device_id dw_dma_of_id_table[] = {
-	{ .compatible = "stf,dma_test"},
-	{}
-};
-MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
-
-static struct platform_driver vpu_driver = {
-    .driver = {
-           .name = VPU_PLATFORM_DEVICE_NAME,
-           .of_match_table = cm_vpu_match,
-		   	.pm = &vpu_pm_ops,
-    },
-    .probe = vpu_probe,
-    .remove = vpu_remove,
-    .suspend = vpu_suspend,
-    .resume = vpu_resume,
-};
-
-module_platform_driver(vpu_driver);
-
-MODULE_AUTHOR("dma test.");
-MODULE_DESCRIPTION("dma test.");
-MODULE_LICENSE("GPL");

+ 2 - 2
wave511/code/vdi/linux/vdi.c

@@ -54,8 +54,8 @@
 typedef pthread_mutex_t	MUTEX_HANDLE;
 
 
-#    define SUPPORT_INTERRUPT
-#        define VDI_SRAM_BASE_ADDR          0x00000000    // if we can know the sram address in SOC directly for vdi layer. it is possible to set in vdi layer without allocation from driver
+#define SUPPORT_INTERRUPT
+#define VDI_SRAM_BASE_ADDR          	0x00000000    // if we can know the sram address in SOC directly for vdi layer. it is possible to set in vdi layer without allocation from driver
 #define VDI_SYSTEM_ENDIAN                   VDI_LITTLE_ENDIAN
 #define VDI_128BIT_BUS_SYSTEM_ENDIAN        VDI_128BIT_LITTLE_ENDIAN